Abstract: A packet delay variation simulation system has a packet generator, a packet delay variation generator, and a packet delay analyzer to analyze delayed packets. The packet delay variation generator has multiple delay distribution modules that use both a deterministic delay process and a statistical delay process packet for determining a packet's delay. The packet delay variation generator may utilize different probability density functions to describe various portions of measured packet data. That is, measured packet delay information is analyzed and information from this analysis is used to construct a total delay model for a network. The delay may include a pre-determined deterministic delay offset as well as one or more variable statistical delay offsets.

Abstract: The present invention discloses a processor capable of alerting its life expectancy and its method. The processor is installed in an electronic device having a control circuit, a frequency divider circuit and a time counter. The control circuit is connected to the frequency divider circuit and the time counter. The frequency divider circuit receives a plurality of high frequencies from the control circuit and converts the high frequencies into a time unit. The time counter adds the time units one by one to obtain a use time. If the use time has reached a predetermined use time, the control circuit will issue a warning to indicate that the life expectancy of the processor is reached, so as to reflect the actual use time of the processor, prevent a change of use time by software, and allow users to timely take proper preventive measures before the processor exceeds its life cycle.

Abstract: At least one exemplary embodiment of the present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A method and system of determining forthcoming failure of transducers. At least some of the illustrative embodiments are methods comprising creating a first electrical signal representative of acoustic energy propagating between a first pair of transducers of a fluid meter, creating a second electrical signal representative of acoustic energy propagating between a second pair of transducers of the fluid meter (the creating the second electrical signal substantially concurrently with create the first electrical signal), calculating a value indicative of a relationship between a parameter of the first electrical signal a parameter of the second electrical signal, and determining whether performance of the first pair of transducers indicates upcoming failure of at least one transducer of the first pair of transducers, the determining using the value.

Abstract: Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by compar

Abstract: A trending system and method for trending data in a mechanical system is provided. The trending system includes a sliding window filter. The sliding window filter receives a data set of data points generated by the mechanical system. The sliding window filter partitions the data set into a plurality of data windows, and uses the data windows to calculate upper and lower confidence bounds for the data set. Specifically, the sliding window filter calculates an upper confidence bounds and lower confidence bounds for each data point using each of the multiple data windows that includes the data point. The sliding window filter then selects the upper confidence bounds and the lower confidence bounds that results in the smallest mean prediction confidence interval for that data point. This results in a smoothed estimated trend for the data set that can be used for prognostication and fault detection.

Abstract: A method for coding an event history is disclosed. Information relating to a real time state of an event is received. For a defined interval of time, it is determined whether the state of the event is in one of two states. In response to the event being in a first state, a data stream is appended with a first characteristic representative of the first state, and in response to the event being in a second different state, the data stream is appended with a second characteristic representative of the second state. The appended data stream is saved, and the process repeated for the next sequential defined interval of time.

Abstract: A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.

Abstract: The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted signal which comprises a test signal sequence with a high auto-correlation characteristic; then, receiving a received signal, and performing a correlation operation on the test signal and the received signal; finally, according to the result of the correlation operation, determining the impedance matching condition of the transmission medium.

Abstract: An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

Abstract: A 3-dimensional flipflop timing model is described, which allows a flipflop to be presented with a smaller setup time in comparison to a 2-dimensional timing model. Because of this, fewer timing errors will be encountered during chip timing analysis, fewer timing errors will have to be fixed, and the user can often avoid redesigning logic that fails to meet its timing specs, thus saving valuable design time. Furthermore, in many cases, the user can avoid the necessity of using larger standard cells that employ larger transistor sizes, thus minimizing chip size and chip power dissipation.

Abstract: This invention provides compositions and methods for producing low cholesterol poultry eggs using hypocholesterolemic compounds, cholesterol lowering supplements, and feeds therefrom. Preferably, this invention provides microbial statins without methyl group in C6, as shown in formula V, in order to produce low cholesterol poultry eggs. The invention allows producing low cholesterol poultry eggs without concomitant reduction of egg production by providing microbial statins, compactin and pravastatin as well as their derivatives, as cholesterol lowering components. This invention also provides methods for producing low cholesterol poultry eggs without huge increase of production cost since the effective amount of cholesterol lowering composition containing microbial statin costs 1/120-¼ of that of synthetic statin.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: A method, system and computer-readable medium are presented for creating unique clock waveform checking commands for an event simulator to validate that the logical creation matches the timing definitions. The method includes selecting one or more clock signals for validation; specifying timing definitions of the selected clock signals; automatically categorizing the selected clock signals based on their synchrony; automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions; specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.

Abstract: A method automatically sets initially-estimated rotational frequency for a motor frequency measuring system based on pulse signals output from an encoder. Initially, a counter is reset to zero, and a count threshold and an initially-estimated rotational frequency are set. The possible motor frequencies are divided into multiple frequency ranges with specific starting frequencies. A pulse width threshold is set according to the initially-estimated rotational frequency. A new motor frequency is calculated by the count threshold and a corresponding elapsed time. The initially-estimated rotational frequency is set to be a frequency in a frequency range higher than the new motor frequency. Therefore, the initially-estimated rotational frequency can be adaptively set according to an updated frequency measurement. Moreover, the count threshold can be monotonously increased with the updated frequency measurement to enhance measurement accuracy.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.

Abstract: A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.

Abstract: In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the signals having different pulsewidths. After driving each signal, the signal is sampled at or about a timing of the signal's sensor edge to thereby characterize the signal's sensor edge. The sensor edge characterizations corresponding to the different signals are then analyzed to quantify a timing error induced by an impedance variation of the signal path.

Abstract: A method and apparatus for measuring the absolute duty cycle of a signal are provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions and thus may be used in applications such as various time of flight systems.

Abstract: An interpolator testing system comprises an interpolator that generates M clock signals having phase shifts in increments of 360/M degrees relative to a reference clock signal and that outputs one of the M clock signals as a recovered clock signal. A recovered clock counter counts an attribute of the recovered clock signal, wherein the interpolator sequentially selects the M clock signals N times, wherein M and N are integers greater than one.

Abstract: A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.

Abstract: Non-intrusive speech quality assessment method and apparatus for: storing a sequence of intercepted packets associated with a call, each packet containing speech data, and an indication of a transmission time of the packet; storing with each intercepted packet an indication of an intercept time of the packet; extracting a set of parameters from the sequence of packets; and generating an estimated mean opinion score in dependence upon the set of parameters. The extracting step comprises the sub steps of: generating a jitter parameter for each packet of the sequence of stored packets; and generating a consecutive positive jitter parameter for the stored packet.

Abstract: Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with a threshold at the set sample point for a plurality of repetitions of the bit sequence, determining a distribution value on the base of the sum of the assigned digital values, shifting the sample point by a time increment, iteratively repeating determining the distribution value until the sample point has reached a second sampling position, determining from the distribution values a distribution function over the sample points, and determining the jitter property by using the distribution function.

Abstract: Apparatus and associated systems, methods and computer program products relate to isolating horizontal jitter component(s) from vertical jitter component(s). In preferred embodiments, at least one horizontal component of jitter is distinguished from at least one component of vertical jitter by fitting a curve to a digitally acquired waveform, determining the curve slope and statistical variance about the fitted curve over at least one time period, identifying a functional relationship between the variance and slope, and determining therefrom at least one horizontal component of jitter and at least one vertical component of jitter. Random and deterministic jitter components may be aggregated, in certain embodiments, so as to identify a vertical jitter component that reflects both deterministic and random jitter. In preferred implementations, the isolated vertical jitter component is subtracted from a total jitter measurement so as to better approximate actual signal jitter.

Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.

Abstract: Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

Abstract: In a method, system and apparatus for measuring an idle value of a Central Processing Unit (CPU) in an embedded system, the CPU increments a hardware counter in accordance with clock signals. The CPU also increments an idle counter during a predetermined period of time in accordance with the clock signals while an idle task is running. The CPU calculates the idle value as a ratio of total increments of the idle counter to total increments of the hardware counter after the predetermined period of time has expired.

Abstract: A modular metering system comprises a data processing module, a current module and a voltage module. The current and voltage modules include sensor memories characterizing the respective current and voltage sensors facilitating assembly and repair of the metering system.

Abstract: A method of pattern identification and bit level measurements for a high speed digital signal using an oscilloscope converts an input waveform into a bit stream sequence. From the bit stream sequence pre-defined patterns are identified and overlaid on each other to form a superimposed pattern. A center region for each bit of the superimposed pattern is identified, and appropriate voltage measurements within the respective center regions are taken for the bit levels.

Abstract: An improved method, apparatus, and computer instructions for generating trace data. In response to detecting a trace event, a determination is made as to whether identifiers for the trace event match recorded identifiers for a record in a set of previously recorded trace events. Location information for the record is placed in the trace data if a match between identifiers for the trace event and recorded identifiers for the record in the set of previously recorded trace events.

Abstract: A method of detecting pileups includes testing an instantaneous slope of a preamplifier signal against a noise trigger value and, after the instantaneous slope has been determined to exceed the noise trigger value, identifying a first subsequent portion of the preamplifier signal wherein the instantaneous slope of the preamplifier signal increases to a maximum. The method further includes, following the first subsequent portion, identifying a second subsequent portion of the preamplifier signal wherein the instantaneous slope still exceeds the noise trigger level but has decreased by more than the noise trigger level from the maximum, and, following the second subsequent portion and before the instantaneous slope declines below the noise trigger level, identifying a third subsequent portion of the preamplifier signal wherein the instantaneous slope of the preamplifier output signal increases by more than the noise trigger value, and, in response thereto, determining that a pileup has occurred.

Abstract: In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Abstract: This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

Abstract: A testing method of a communication device according to the present invention comprises: a step for transmitting and receiving a test signal generated based on a reference clock; a step for generating an anticipated value of the test signal based on the reference clock; a step for delaying the test signal; a step for comparing the delay test signal with the anticipated value and outputting the comparison results; a step for repeatedly performing the above steps and storing the comparison results for each delay time; a step for detecting the eye opening for the test signal based on the comparison results for each delay time; and a step for determining the quality of the communication device based on the detected eye opening.

Abstract: A signal delay time measurement device outputs, to a sound space, a measurement signal sound corresponding to a measurement signal such as a pulse signal, and obtains a response signal indicating a response thereof. By comparing the response signal with a predetermined threshold, the signal delay time measurement device measures a signal delay time in the sound space. The signal delay time in the above-mentioned sound space includes a delay time other than the delay time caused by a transmission of a signal sound to the sound space, and the response signal cannot theoretically reach the signal delay amount calculating unit during the delay time. Therefore, the delay time calculating unit does not perform the comparison in a no-response period in which the response signal has not reached the delay time calculating unit yet. Thereby, it can be prevented that the signal delay time is erroneously calculated by an effect of a background noise during the no-response period.

Abstract: A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing the signal being characterized/analyzed in the digital domain irrespective of it's starting format. The approach performs a voltage-to-time conversion using predetermined voltage thresholds, applying a time amplification to the digital time information, measuring the amplified time difference between events and converting the amplified time difference as required by the characterization/analysis. The method allows the capture of very high-speed signals with high resolution without the requirements of complex and high-speed electronics. As such the on-chip high-speed time domain digital analyzer can function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer.

Abstract: A trending system and method for trending data in a physical or clock system. The trending system includes a sliding window filter. The sliding window filter receives a data set of data points generated by the clock system. The sliding window filter partitions the data set into a plurality of data windows, and uses the data windows to calculate upper and lower confidence bounds for the data set. Specifically, the sliding window filter calculates upper confidence bounds and lower confidence bounds for each data point using each of the multiple data windows that includes the data point. The sliding window filter then selects the upper confidence bounds and the lower confidence bounds that result in the smallest mean prediction confidence interval for that data point. This results in a smoothed estimated trend for the data set that can be used for prognostication and fault detection.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: A method comprises the step of obtaining a first signal of the signal from a first position of a transmission channel, and a second signal of the signal from a second position of the transmission channel, determining a delay time between the first signal and the second signal by a first degree of alikeness of the first signal and the second signal trace, and determining a direction function vector of the signal by a second degree of alikeness of the first signal and the second signal trace.

Abstract: A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.