Abstract: A method of measuring discrete incremental feedback from motion systems that creates a discrete feedback pulse for every unit of motion that is accomplished by the motion system. The method comprises establishing a minimum feedback pulse sampling period, and accumulating feedback pulses during a sampling period. Upon the first feedback pulse after the minimum feedback pulse sampling period has passed, the current sampling period is ended, and the next sampling period is begun. The quantity of feedback pulses accumulated during the current sampling period is then determined.

Abstract: An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.

Abstract: A method for determining the phase characteristics of a nonlinear analog device includes application of a test signal, which may be linear-FM, to the nonlinear device. The converted signal is digitized and mathematically converted to baseband in ideal fashion. A digitized version of the original test signal and the downconverted signal are phase compared to determine the phase error.

Abstract: A means for determining long-term discharge performance, particularly in a lithium/silver vanadium oxide cell, by analyzing and characterizing the initial pulse voltage waveform, is described. The relationship between the initial P1 (Pmin) voltage drop and the extent of that initial voltage drop with Plast (the final voltage under load) is a reliable indication of long-term discharge performance.

Abstract: A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

Abstract: In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Abstract: There is provided a timing generator that outputs a second periodic signal having a desired phase difference to a first periodic signal by superimposing a voltage on a control voltage of a voltage-controlled oscillating unit of a PLL circuit for generating the second periodic signal. The timing generator includes an initializing unit for measuring a timing shift gain indicative of a ratio of a timing shift amount to a change of a superimposed voltage and a voltage generating unit for generating the superimposed voltage based on the desired phase difference and the timing shift gain.

Abstract: To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.

Abstract: The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A trasnsition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector includes first signal generator for generating a first binary signal ERRQ a second signal generator for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ?T2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA.

Abstract: In one embodiment, each of a plurality of stimulus signals is sequentially driven onto a number of stimulus signal paths. Each of the plurality of stimulus signals has a trigger edge. As each stimulus signal is driven onto the number of stimulus signal paths, a victim signal having a sensor edge is driven onto a victim signal path. After driving a corresponding stimulus and victim signal, the victim signal is sampled at or about a timing of the signal's sensor edge to thereby characterize the signal's sensor edge. The sensor edge characterizations corresponding to the different stimulus signals are then analyzed to quantify a timing error induced by crosstalk between the victim signal path and one or more of the stimulus signal paths.

Abstract: A bit error rate test on a transceiver is accelerated by adding a phase offset to data phase encoding and decoding in the transceiver and by mapping bit error rate test results from an elevated error rate condition to a normal error rate condition for the transceiver. The elevated error rate is accomplished by adjusting the phase of the phase encoder and decoder with the value of the phase offset so that the encoded data transmission signal is not as robust against noise as it normally would be. Noise in the form of an interference signal is introduced during the transmission, and the bit error rate is measured after the receiver has decoded the signal. The bit error rate (BER) data with an elevated propensity for error is mapped against bit error rate data for normal operations. A mapping function is built to map BERE (bit error rate elevated) data—data from the elevated error rate condition for data encoding, to BERN (normal bit error rate) data—data from the normal error rate condition for data encoding.

Abstract: A nonlinear hysteresis control system for controlling an actuator with nonlinear hysteresis effect is disclosed. An improved extended hysteresis effect profile further stores the displacement when a applied voltage of the actuator is from 0 voltage to a specific voltage and back to that specific voltage. Therefore, the system can be used under the condition of not very slow motion of the actuator.

Abstract: A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

Abstract: A system and related method for generating a test signal with controllable amounts of signal jitter includes a pattern generator, a programmable arbitrary waveform generator (AWG) and a phase modulator. The pattern generator is configured to generate a data signal characterized by a given data pattern, bit rate and pattern length. A trigger signal representative of initial timing information associated with the data signal is provided to the AWG which subsequently generates a modulation signal with a frequency equal to the bit rate divided by the pattern length of the data signal. This modulation signal is provided to the phase modulator, along with a reference clock signal, and the phase modulator generates a modulated clock signal controlled by a phase modulation means (e.g., a controllable delay line) fed by the modulation signal.

Abstract: A test measurement system and method which uses parallel digital samples of an input measurement signal to determine a trigger point for a predetermined trigger waveform. The system correlates the predetermined trigger waveform with digital samples of the input measurement signal. The result of this correlation is then used to identify a trigger point. Generally the point in time where the trigger waveform has the strongest correlation with the digital samples identifies the desired trigger point. This trigger point is then used to identify the selected measurement data, where the selected measurement data corresponds to the digital samples obtained at the trigger point time.

Abstract: A performance monitor includes at least one Monitor Mode Control Register (MMCR) and plural Performance Control Monitors (PMCs). Each PMC is controlled by the MMCR to pair or group the PMCs so that the overflow from one PMC can be directed to its pair/group. By coupling the PMCs so that overflow from one can be directed to another, the effective size of the counters can be increased.

Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.

Abstract: A performance monitor includes at least one Monitor Mode Control Register (MMCR) and plural Performance Control Monitors (PMCs). Each PMC is controlled by the MMCR to pair or group the PMCs so that the overflow from one PMC can be directed to its pair/group. By coupling the PMCs so that overflow from one can be directed to another, the effective size of the counters can be increased.

Abstract: Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The first bit sequence is transmitted through an optoelectronic device and compared with corresponding bit groups in the second bit sequence. The optoelectronic device is disabled and a count of compared bit groups is kept until the comparison indicates that the optoelectronic device is completely off. Using the count and one or more of the bit groups, a turn-off time is calculated. Alternatively, the method is used to calculate a turn-on time. The optoelectronic device is enabled and a count is kept from the time the device is enabled to when the comparison of the corresponding bit groups indicates that the optoelectronic device is completely on.

Abstract: Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to be measured. A signal fed through this mimic path will experience similar delay to a signal passing through the actual path, which can be affected by temperature and voltage variations during operation. A swept clock signal can be passed to a register latching the mimic signal data, producing output that can be fed to lead/lag logic to determine a current value of the delay through the mimic path. This delay can be compared to a previous delay determination to approximate an adjustment to be made to a sampling clock used to latch the actual data into the appropriate register at the middle of the latching window.

Abstract: An operation monitor device for a hardware component detects a load current that is changed due to the operation of the hardware component through a pulse width modulation (PWM) module; thereby generating a voltage variation. A monitoring unit outputs a detecting result to a system by detecting the voltage variation and generates a modulating signal in response to a monitor signal fed back by the system according to the detecting result, such that a controller generates a reference voltage variation according to the modulating signal. In this way, the load current changes as the load of the hardware component increases, such that the controller changes the generated reference voltage and further modulates the output voltage supplied to the hardware component by the PWM module, thus meeting the execution state of the hardware component and improving performance.

Abstract: For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.

Abstract: A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an output value and determining the delay from the output value. Preferably, each sample is weighted according to one or more characteristics of the event used to define the sample. The magnitude of the output value could be an indication of the delay, or there could be several output values each for a respective differently-delayed version of the second signal, in which case these could be evaluated to select which corresponds to the actual delay.

Abstract: Methods for estimating data-dependent jitter (DDJ) from measured samples of a transmitted data signal include a first exemplary step of obtaining a plurality of measurements (e.g., time tags and event counts for selected pulse widths in the data signal). Such measurements may be obtained at predetermined intervals within a transmitted signal or may be obtained at randomly selected intervals, and should yield measurements for each data pulse in a repeating data pattern. An average unit interval value representative of the average bit time of the transmitted signal is determined. Time interval error estimates representative of the timing deviation from each signal edge's measured value relative to its ideal value (determined in part from the calculated average unit interval value) are also determined, as well as a classification for each measured signal edge relative to a corresponding data pulse in the repeating data pattern.

Abstract: There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first variable delay circuit that delays a given reference clock to output a first set signal; a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal; an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal; and a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal.

Abstract: A method for computer aided design of semiconductor chips which minimizes sensitivity to latchup is provided. The method evaluates electron transmission, reflection and absorption at geometric shapes that represent components of the semiconductor.

Abstract: There is provided a delay amount measuring method of measuring a delay amount in an electronic device that outputs an output signal according to an input signal. The method includes a conversion step of converting the input signal and the output signal into digital data, a shift step of sequentially shifting the digital data of either of the input signal or the output signal in a time direction, an error computing step of computing a squared error of the digital data of the input signal and the digital data of the output signal with respect to each shift amount in the shift step, and a delay amount computing step of computing the shift amount when the squared error is a minimum value by means of a nonlinear least squares method and using the computed shift amount as the delay amount in the electronic device.

Abstract: An undersampling system can comprise an IC that has integrated, on the same physically contiguous IC, both an undersampler circuit and a receiver circuit whose input is to be monitored by undersampling. For a current phase of sample clocks relative to an input signal, the input signal is sampled until a sufficient number of samples are collected in a one dimensional histogram associated with the current phase. The phase of the sample clocks, relative to the input signal, can then be shifted. Such phase shift can be accomplished by a phase mixer. The phase shift can be small enough to provide sufficient resolution in a composite sampled image of the input signal. A mean value can be computed for each one dimensional histogram, resulting in a representation of the undersampled signal as a function of time that is suitable for further processing.

Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.

Abstract: An advanced trigger circuit includes two trigger decoders, each triggering on one of respective pluralities of continuous-time trigger events. In one embodiment, a programmable timer begins timing in response to an output signal of the first trigger decoder and generates an end-of-time signal at the expiration of its time period. A reset circuit resets the first trigger decoder if the second selected continuous-time trigger event failed to occur before the end-of-time signal was generated. In another embodiment, a reset decoder generates a reset signal in response to an occurrence of a selected continuous-time trigger event. The reset circuit is responsive to the reset signal for resetting the first trigger decoder if the second selected continuous-time trigger event failed to occur before the reset signal was generated. In other embodiments, the advanced trigger circuit triggers on a serial lane skew violation or on a beacon width violation.

Abstract: The present invention is a system and method that facilitates measurement of timing variations (e.g., timing delays) in a semiconductor chip. The timing variations are measured and presented as digital values without extensive off chip measurement and analysis equipment. The timing variation measurements provides insight into timing variations (e.g., delays) inside a semiconductor chip and across different chips, including timing impacts experienced in end use after manufacturing. A timing variation measurement system includes a variation test signal generator for passing a signal through a portion of a circuit and generating a variation test signal. A variation test signal tracking component digitally counts cycles in a variation test signal and a control component controls the counting (e.g., the length of time the cycles are counted). Timing variation information, including a digital value associated with the variation test signal cycle count, can be communicated via pins and/or a processor interface.

Abstract: Performing delay measurement between master and slave devices. The master transmits a delay measuring signal at a fixed timing relative to a synchronous pattern signal in an overhead and transmits a frame signal in which an internal delay time, associated with a frame signal generation, from a delay measurement start timing to a transmission timing of the delay measuring signal is stored in the delay measuring signal as a master offset value. The slave adds an internal delay time associated with a frame signal generation to the master offset value of the frame signal, making a slave offset value and transmits an updated delay measuring signal with the slave offset value. The master calculates a delay time by subtracting the slave offset value from a time difference between a timing at which the delay measuring signal transmitted from the slave is received and the delay measurement start timing.

Abstract: A power metering apparatus meters a power signal in a powered system. A low-pass filter receives the power signal and outputs a filtered signal. The filter implements a corner frequency programmable based on a first clocking signal and anti-aliases high frequency components of the power signal. An A/D converter receives the filtered signal and outputs a digital signal. The A/D converter samples the filtered signal according to a system clock based on a second clocking signal. A clocking element generates and outputs each of the first clocking signal and the second clocking signal. The first clocking signal is synchronous with the second clocking signal.

Abstract: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Abstract: The invention is directed to a device for calibrating signals, whereby at least two signal circuits are provided for generating signals. In order to calibrate the signals, elements are provided that evaluate the signals generated by the signal circuits and, dependent thereon, drive at least one of the at least two signal circuits such that the time reference of the signals generated by the signal circuits relative to one another is set corresponding to at least one prescribed value.

Abstract: A method and circuit for measuring a statistical value of jitter for a data signal having a data rate fD, comprises digitally sampling the data signal at a sampling rate, fS, to produce sampled logic values, where fD/fS is a predetermined non-integer ratio; and analyzing the sampled values to deduce a statistical value of the jitter.

Abstract: Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

Abstract: At least one exemplary embodiment of the present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count, and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire, the last edge appearance timing in the signal waveform of a victim whose noise value exceeds a limit value is compared with the last edge appearance timing in the signal waveform of an aggressor, to evaluate the noise value error in the victim. The apparatus is used in static noise checking of cell arrangement and inter-cell wiring after such cell arrangement and inter-cell wiring are performed at design of integrated circuits such as LSIs.

Abstract: A control system includes controllers that are coupled mutually by a communications network, on which information, transmitted from a master controller to a slave controller, is used to make timing corrections on the slave controller in order to synchronize event timers on the slave controller with that of the master controller. Timing accuracy for the occurrence of the event commanded by each controller is synchronized in narrow range of time, preferably within a few milliseconds depending on the specific application and system.

Abstract: A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM circuit may generate a calibration signal with intentional ripple, which may exercise a region of a transfer curve of the ADM to reduce local nonlinearities in measurements associated with the calibration of the system. Pulse trains of varying frequency and duty cycle may be generated to sweep the PWM circuit through an ADM range and to calculate an ADM linearity correction function, which may be used to perform gain and offset correction with respect to a best-fit line through an ADM transfer curve to reduce large signal nonlinearities. The PWM circuit may include a resistor divider circuit including a plurality of taps to calibrate small input ranges.

Abstract: A structure and related method for determining the uncertainty window associated with clock signals on a microprocessor using circuitry on the microprocessor die itself and external software. A target clock signal of interest is compared to a series of reference clock signals having the same frequency, but differing in phase relationship. Where the target clock signal makes state transitions with respect to the various reference clock signals over the course of several thousand comparisons is indicative of the uncertainty window for that target clock. By adjusting the phase relationship between the reference clock signals, and thereby adjusting the width of the time windows defined by corresponding features of the reference clock signals, the uncertainty window for the target clock signal may be iteratively determined.

Abstract: The remaining capacity of a battery obtained by integrating current and that obtained from the estimated open circuit voltage of the battery are weighted with a weight which varies depending on the operating conditions of the battery as needed and the weighted remaining capacities are combined into the final remaining capacity. Thus, the disadvantages of the remaining capacity based on current integration and those of the remaining capacity based on the estimated open circuit voltage cancel each other out and the advantages of the respective remaining capacities can be fully utilized. The uniform calculation accuracy can be ensured and the final remaining capacity can always be obtained with accuracy.

Abstract: The Smart Resolution Valve Pressure Control System allows any pressure control system using valve state pulsing to modify airflow at an optimum and consistent range of operation thereby enhancing control accuracy and increasing the useable cycle life of any valve combination used.

Abstract: Systems and methods can provide, in one aspect, a method for modulating the pulse width of control signals generated on a plurality of separate channels. In one practice, the methods described herein are suitable for execution on a microprocessor or micro controller platform that includes a timer interrupt mechanism which will generate an interrupt in response to a timer counting down a selected time interval or time period. In one practice, the timer is set to count down a period of time that is representative of a portion, or sub period, of the PWM cycle. Upon expiration of that time period, the timer executes an interrupt that causes the micro controller to enter an interrupt service routine (ISR) that can further modulate the PWM cycle of one or more signals.

Abstract: The invention relates to a method for process-variable-dependent identification signal emission for a closed-loop and/or open-loop control program with cyclic sampling of process variables from a technical process. A threshold value crossing time (ts1, ts3) is determined from at least two previous samples (AT1, AT2, AT5-AT7) of a process variable (P). At this time, an identification signal can be triggered, which can call up a single-stage or multi-stage command sequence. The threshold value crossing time (ts1-ts3) can likewise be determined with the aid of a mathematical approximation function and the samples (AT1, AT2, AT5-AT7). A timing mechanism can be started in the predicted sampling cycle (A12 to A89) preceding the threshold value crossing (SD1-SD3) using a time difference (ZD1-ZD3) remaining until the threshold value crossing (SD1-SD3).

Abstract: An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit adjusts the delay generated by an adjustable delay line, and adjusts the occurrence in time of the trailing edge of the output signal. A value which corresponds with a suitable delay to be generated by the adjustable delay line is stored in nonvolatile storage on the integrated circuit.

Abstract: An automated method and system for calculating the transit time of a pulsed signal transmitted from a first ultrasonic transducer to a second ultrasonic transducer is provided. The method includes measuring the amplitude of the pulsed signal received at the second transducer from the first transducer; measuring the amplitude of any noise proximate to the received pulsed signal; and calculating the signal to noise ratio of the received pulsed signal and the noise, respectively. If the signal to noise ratio is above a predetermined threshold, a first technique is automatically implemented for calculating the transit time of the received pulsed signal. If the signal to noise ratio is less than the predetermined threshold, a second different technique is automatically implemented for calculating the transit time of the received pulsed signal.

Abstract: A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.