Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.

Abstract: Embodiments of the present invention provide a system that characterizes the reliability of a computer system. The system first collects samples of a performance parameter from the computer system. Next, the system computes the length of a line between the samples, wherein the line includes a component which is proportionate to a difference between values of the samples and a component which is proportionate to a time interval between the samples. The system then adds the computed length to a cumulative length variable which can be used to characterize the reliability of the computer system.

Abstract: Meter electronics (20) for processing sensor signals in a flow meter is provided according to an embodiment of the invention. The meter electronics (20) includes an interface (201) for receiving a first sensor signal and a second sensor signal and a processing system (203) in communication with the interface (201) and configured to receive the first sensor signal and the second sensor signal, generate a ninety degree phase shift from the first sensor signal, and compute a frequency from the first sensor signal and the ninety degree phase shift. The processing system (203) is further configured to generate sine and cosine signals using the frequency, and quadrature demodulate the first sensor signal and the second sensor signal using the sine and cosine signals in order to determine the phase difference.

Abstract: A time series data dimensional compression apparatus performing dimensional compression for improving the efficiency of searching for time series data without losing the features of data. The compression is made to a determined dimension so that a larger volume of information may be extracted therein. A time series subsequence generating section (112) generates time series subsequences of a specified segment width into which a plurality of pieces of time series data generated at a time series data generating section (110) are divided. A singular value decomposition processing section (113) performs singular value decomposition on all of the time series subsequences. A dimensional compression time series data generating section (114) generates dimensional compression time series data by using high-order elements of the singular value decomposition as a representative value of the time series subsequence.

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closure, beyond a closure threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract: An apparatus for determining the torque imposed on a rotatable shaft. The shaft has at least four paired probes, paired horizontal probes and paired vertical probes. The horizontal probes are positioned 90 degrees apart from the vertical probes. If the shaft moves horizontally, the time of arrival detected by the first horizontal probes will be later than a nominal value and the time of arrival for the second horizontal probes will be earlier than a nominal value with the same amount of error. Combining data from the first and second horizontal probes will then automatically cancel out any error from horizontal motion. Similarly, combining data from vertical probes will eliminate the error due to vertical movement. Because any radial movement is a combination of horizontal and vertical movements, the use of the probes removes errors due to movement in any direction.

Abstract: A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: A method for determining the fill level (l) on the basis of the travel time (t) of a high-frequency measuring signal (SHF), which is transformed into a lower frequency, intermediate-frequency measuring signal (SZF), wherein the transformation factor (KT) is obtained from a difference frequency (fSweep) between a pulse repetition frequency (fPRF) and a sampling frequency (fsample) The pulse repetition frequency (fPRF) or the sampling frequency (fsample) is altered on the basis of a control with a control variable (c_var) through an appropriate control algorithm, such that a desired value (fSweep—setpoint) of the difference frequency is controlled to; wherein a gradient (grad) of at least two values is determined, and on the basis of the gradient (grad) and the difference frequency (fSweep), or difference time (tSweep), in the case of a set control variable (c_var), an operating point (OP) of the control is determined, and the control algorithm is adjusted accordingly thereto.

Abstract: Apparatus and methods are provided for analyzing surface characteristics of a test object using broadband scanning interferometry. Test objects amenable to these apparatus and methods include but are not limited to semiconductor wafers, semiconductor devices, metallic surfaces, and the like. An interferometry system is used to obtain an interferometry signal and related to data embodied in the signal representative of the test object surface. This signal and/or data is used to construct an n-dimensional function that includes an independent frequency variable and an independent time variable, and/or an n-dimensional function that includes an independent scale variable and an independent time variable, and/or a multi-domain function. These functions are compared with various models to obtain a best match that is then used to characterize the test object surface.

Abstract: A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing the signal being characterized/analyzed in the digital domain irrespective of it's starting format. The approach performs a voltage-to-time conversion using predetermined voltage thresholds, applying a time amplification to the digital time information, measuring the amplified time difference between events and converting the amplified time difference as required by the characterization/analysis. The method allows the capture of very high-speed signals with high resolution without the requirements of complex and high-speed electronics. As such the on-chip high-speed time domain digital analyzer can function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer.

Abstract: A method for rapidly extracting data file samples with an a signal monitor and an automatically adjusted decimation ratio is provided to solve the long-standing problems caused by large data files and small buffers by reducing a large data segment to a smaller, more manageable size automatically so that a lower resolution version of the data segment will be loaded into a fixed-size small buffer in the computer's working space buffer for further data editing. In accordance with the methods of this invention, the segment size will vary during the operation of a means for zooming-in and the decimation ratio is updated and adjusted automatically based on the variation of segment size. The present invention insures that the best resolution of the data segment will be achieved when fitting the varying large size data segment into the fixed small size buffer.

Abstract: Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

Abstract: In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Abstract: A computer program for performing a method of providing a parameter estimate from noisy data with aperiodic data arrival. The parameter of the measurement is estimated as a numerator divided by the denominator. The method involves setting a fixed time interval and then waiting for the time interval to expire or for a measurement to occur. If a measurement occurs before the time interval expires the numerator is estimated as a previous numerator plus the new measurement, and the denominator is estimated as a previous denominator plus one. Regardless of whether the measurement occurs or the time interval expires the numerator is estimated as a previous numerator times a step size and the denominator is estimated as a previous denominator times a step size. The method can be applied to numerous applications including assessing data temperature and predicting I/O response times.

Abstract: Real time battery impedance spectrum is acquired using one time record, Compensated Synchronous Detection (CSD). This parallel method enables battery diagnostics. The excitation current to a test battery is a sum of equal amplitude sin waves of a few frequencies spread over range of interest. The time profile of this signal has duration that is a few periods of the lowest frequency. The voltage response of the battery, average deleted, is the impedance of the battery in the time domain. Since the excitation frequencies are known, synchronous detection processes the time record and each component, both magnitude and phase, is obtained. For compensation, the components, except the one of interest, are reassembled in the time domain. The resulting signal is subtracted from the original signal and the component of interest is synchronously detected. This process is repeated for each component.

Abstract: A computer program for performing a method of providing a parameter estimate from noisy data with aperiodic data arrival. The parameter of the measurement is estimated as a numerator divided by the denominator. The method involves setting a fixed time interval and then waiting for the time interval to expire or for a measurement to occur. If a measurement occurs before the time interval expires the numerator is estimated as a previous numerator plus the new measurement, and the denominator is estimated as a previous denominator plus one. Regardless of whether the measurement occurs or the time interval expires the numerator is estimated as a previous numerator times a step size and the denominator is estimated as a previous denominator times a step size. The method can be applied to numerous applications including assessing data temperature and predicting I/O response times.

Abstract: A system for estimating a length of a conductor (110) having a first end (111) and a second end (112) includes a device (120) capable of placing an electric signal on the conductor, an impedance element (130) that maintains the electric signal within a predetermined voltage range, and a timer (140). The device places the electric signal on the conductor such that the electric signal travels along the conductor from the first end to the second end and back to the first end. The timer determines a time required for the electric signal to travel along the conductor from the first end to the second end and back to the first end. The length of the conductor may be estimated based on the time. A compensation factor may be determined based on the length or the time, and may be used to compensate for signal attenuation in the conductor.

Abstract: A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Abstract: A signal processing system may compensate for the relative phase difference between multiple frequency bands so that the combination of the bands is constructive throughout a substantial portion of the band overlap or crossover region. In one embodiment, a signal combining system may include a comparator for determining a relative phase difference between the two signals within a predefined crossover region, a phase adjusting element for adjusting a phase of one of the two signals; and a combiner for combining the phase-adjusted signal and the other of the two signals.

Abstract: An improved method, apparatus, and computer instructions for generating trace data. In response to detecting a trace event, a determination is made as to whether identifiers for the trace event match recorded identifiers for a record in a set of previously recorded trace events. Location information for the record is placed in the trace data if a match between identifiers for the trace event and recorded identifiers for the record in the set of previously recorded trace events.

Abstract: A signal processing system for detecting purposive signals includes an input receiving a signal having a signal characteristic subject to user manipulation. An activation detector compares a property of the signal characteristic to one or more signal characteristic property thresholds over time. A filter module determines whether the signal characteristic is purposively manipulated based on an amount of time preceding or following an occurrence of the property exceeding or falling below one or more signal characteristic property thresholds.

Abstract: A method determining a transient response includes providing a measured magnitude of the Fourier transform of a complex electric field temporal profile of a pulse sequence comprising a probe pulse and a dummy pulse, wherein the probe pulse is indicative of the transient response of a sample. The method further includes providing an estimated phase term of the Fourier transform of the complex electric field temporal profile of the pulse sequence and multiplying the measured magnitude and the estimated phase term to generate an estimated Fourier transform of the complex electric field temporal profile of the pulse sequence. The method further includes calculating an inverse Fourier transform of the estimated Fourier transform, wherein the inverse Fourier transform is a function of time, and calculating an estimated complex electric field temporal profile of the pulse sequence by applying at least one constraint to the inverse Fourier transform.

Abstract: Methods and apparatus provide for estimating leakage power as a function of delay times. Delay times and leakage power values may be measured for a test circuit of a given circuit design. A statistical sampling of the measurements may be obtained for the test circuit. The delay data and leakage power data may be correlated to express and estimate leakage power as a function of delay distribution. The test circuit may include a proposed circuit that is simulated, and the method and apparatus also may provide for: creating a schematic design of the test circuit, having, for example, defined poly gate lengths, on-chip devices, and power sources; incorporating a delay chain into the schematic design to get delay distribution data; and utilizing the schematic design, wherein the utilitzation may be a simulation.

Abstract: Labeling asymmetric network cables for improved network clock synchronization. Time asymmetries between pairs in a network cable are identified and associated with individual cables. This time asymmetry information is used to improve clock synchronization according to the IEEE-1588 standard. The time asymmetry information may be stored in a database and associated with a serial number on the cable, or may be associated with the cable in human and/or machine readable form.

Abstract: A circuit for a data processing apparatus is disclosed, said circuit comprising a data input operable to receive digital signal values, said circuit comprising: spurious signal detection logic operable to monitor a digital signal value within said circuit, and determine at least one of: a safe time window during which it is expected that said digital signal values input into said circuit may cause data transitions in said monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in said monitored digital signal value outside of said at least one safe time window or no data transition in said transition window, said spurious signal detection logic is operable to output a detection signal.

Abstract: A system and method for increasing the accuracy of time delay estimates of signals propagating through an environment. The system includes one or more sensors for receiving a plurality of signals, and a time delay estimator for measuring time delays between multiple pairs of signals. At least some of the multiple pairs of signals are received and measured at different points in time. The system further includes a data analyzer for analyzing time delay estimation data, for generating a statistical distribution of time delay estimates from the data, and for calculating a statistical estimate of time delay from the distribution. By increasing the number of signals employed by the system, the accuracy of the time delay estimation is increased. Further, by calculating the median or the mode of the statistical distribution, noise tolerance is improved.

Abstract: In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit. The apparatus operates in a benchmark mode to determine benchmark duty cycle information and then subsequently operates an a relative mode to determine relative duty cycle information of the clock signal at a selected node in comparison to the clock signal at an external input node.

Abstract: There is provided a calibration apparatus that calibrates a jitter measuring circuit for outputting a jitter measuring signal with a level according to an amount of jitter in an input signal based on the input signal and a delay signal obtained by delaying the input signal by means of a variable delay circuit. The calibration apparatus includes a delay control section that sequentially sets a first delay amount and a second delay amount in the variable delay circuit and a gain computing section that computes gain in the jitter measuring circuit based on the jitter measuring signal respectively output from the jitter measuring circuit for the first delay amount and the second delay amount.

Abstract: The invention relates to an automation device (100, 100?), in which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted.

Abstract: A method of determining the location in time of maxima and/or minima of an oscillatory signal. The method may have application to measurement of biological signals, in particular measurement of heart rate from a pulsatile blood signal. The method includes a first stage including the steps of observation over a measurement period, identifying large local maxima or minima and computing an average interval between the identified local maxima or minima. One or more exclusion periods are located in time in the oscillatory signal, having a duration dependent on the average interval, the exclusion periods used to reject false maxima or minima. Maxima or minima may also be detected as an absolute maximum or minimum between crossing points of a fast and a slow moving average of the oscillatory signal. An exclusion period may also be used to reject false maxima or minima when crossing points are used. Apparatus for performing the method is also claimed.

Abstract: An integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop.

Abstract: A dual source real time clock (RTC) synchronization system and method for implementation within automatic meter reading (AMR) systems that provide system-wide device time synchronization. In one embodiment, a microcontroller-implemented RTC counts elapsed seconds from a pre-determined system timestamp using a low-speed, low-accuracy crystal. A second source is used to compensate for the low-speed, low-accuracy crystal. This second source comprises a high speed clock in one embodiment. This dual source RTC system can synchronize the endpoint device.

Abstract: Embodiments of the present invention apply wavelets to radio frequency (RF) signals to extract specific characteristics (e.g., jitter, phase variations, frequency variations) so that their timing, phase, and frequency components can be characterized. In one embodiment of the present invention, a Haar wavelet is used to extract timing characteristics. In another embodiment, a Morlet wavelet is used to extract phase characteristics. In still another embodiment, a Morlet wavelet is used to extract frequency characteristics.

Abstract: Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.

Abstract: A process and apparatus for identification of the direction of rotation of two periodic electrical signals present on two electrical conductors, particularly of a three-phase power system. In this process, the signals are sampled from two conductors by two wires of the test apparatus provided with a connection to ground via a user of the apparatus. The direction of rotation is determined from information provided by the two signals. The direction of rotation is determined during the zero-crossing of the voltage between the two phase signals. The invention can be used in a apparatus for testing of the direction of rotation of the phases of a three-phase network.

Abstract: A Apparatus for Digital measurement of Quick break voltage and Magnetic pulse duration with microcontroller performs detection and measurement of both shot time (pulse duration) and quick break voltage, absolute value circuit makes detection polarity insensitive, allowing the magnetic pick up probe to be oriented either way in the customer's magnetizing unit coil, precision analog to digital convertor allows software peak detection of quick break voltage under software control of microcontroller, precision timebase of microcontroller allows accurate shot time (pulse duration) measurement, magnetic pick up probe serves as the input transducer for the for the noise free measurement of both shot time and quick break voltage, and microcontroller provides input blanking to ensure capturing the correct voltage spike for quick break voltage detection.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

Abstract: A time interval measurement apparatus and method counts the total number of full clock time periods between two measurement signals. Clock fractional time periods are generated between each of the two measurement signals and the next leading edge of a full clock time period. The total number of full clock time periods and the clock fractional time periods are converted to a time equivalent measurement and combined to generate the total time interval between the two measurement signals.

Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Abstract: A modulated laser light detector that converts laser light energy into electrical signals which exhibit a frequency that is substantially the same as the laser light modulation frequency, in which these signals allow the detector unit to determine a position where the laser light is impacting upon a photodiode array. A superheterodyne receiver circuit is used to provide high gain at an improved signal-to-noise ratio to improve the range at which the modulated laser light signal can be reliably detected. Various types of signal detection circuits are available. Various processing algorithms are disclosed, including a Discrete Fourier Transform with a simplified computational algorithm for use with a low-power processor device.

Abstract: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

Abstract: A method, an apparatus, and a system for phase jitter measurement circuits are described herein.

Abstract: A method and system for performing a bit error rate test on a device with substantial duty cycle output distortion are described herein.

Abstract: A phase based system and method for determining signal consistency (e.g., in a video signal processing system). Various aspects of the present invention may, for example, comprise receiving a first and second signal, each of which comprises a respective first sub-signal. A receiving module may, for example, effect such receiving. The first and second signals may be synchronized according to, at least in part, aspects of their respective first sub-signals. A signal synchronization module may, for example, effect such synchronization. Phase difference between respective sub-signals of the first and second synchronized signals may be determined (e.g., using sample-wise multiplication). Multiplication and accumulator modules may, for example, effect such a determination. A signal may be generated that is indicative of signal consistency based, at least in part, on the determination of phase difference between the respective sub-signals. An output module may, for example, effect such a signal generation.

Abstract: The present invention provides a circuit analysis device including: storage unit having stored therein: connection information about multiple components; delay information including information about the delay time of a discrete component and a chain delay time which is a delay time in the case in which a chain delay effect is generated by a connection with another component about each kind of the multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and data processing unit for: referring to the information stored in the storage unit; performing a total delay time calculation process of sequentially adding the delay times of the components along a signal path in the circuit; and if the chain effect propagating component is halfway through the signal path in the total delay time calculation process, examining a connection relation between components that prec

Abstract: In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit.

Abstract: Methods and apparatus are provided for measuring the duty cycle of a signal based on a data eye monitor. The duty cycle of a signal is estimated by sampling the signal for a plurality of different phases and evaluating the samples to identify when the signal crosses a predefined amplitude value. The duty cycle is estimated based on a statistical variation between the points of predefined amplitude crossing, such as points of zero crossing. The duty cycle can optionally be corrected based on the measured duty cycle value. The sampling of the signal may be performed, for example, using one or more latches.