Abstract: The disclosure provides for a method for identifying and measuring a signal pulse induced in a microcircuit due to ionizing radiation. The method comprises locating an ionizing radiation induced pulse across a microcircuit using a plurality of sensors on the microcircuit. The method further comprises radiating a radiation through the microcircuit to produce a pulse width. The method further comprises using a time to digital converter (TDC) to measure a duration of the pulse width to create a measured pulse width. The method further comprises using the TDC to convert the measured pulse width into a digital signal.

Abstract: A power circuit, information processing apparatus, and power control method are provided. The power circuit includes a determining unit configured to determine whether a control signal provided to control a power source has a fixed frequency characteristic, and an adjusting unit configured to randomly change time when a voltage transmitted to the power source is changed within a prescribed range when the determining unit determines that the control signal has the fixed frequency characteristic.

Abstract: Apparatus and methods of providing a selected sample rate for sensor measurements are provided, which in one aspect may include a circuit configured to receive sensor signals as a first series of count rates corresponding to sensor the sensor measurements, each count rate representing a value of a parameter of interest, at least two accumulators configured to alternately accumulate the count rates in the series of count rates over a time period that corresponds to a selected sample rate and a controller configured to control the time periods for the at least two accumulators.

Abstract: A method for estimating inter-channel delay and an apparatus for estimating inter-channel delay and an encoder are provided by the embodiments of the present invention. The method includes: obtaining signal sound field information from a cross-correlation function and a cumulative cross-correlation function of synthetic signals of left and right sound channels respectively; obtaining adjustment information of the cumulative cross-correlation function according to the sound field information that is respectively obtained; adjusting the cumulative cross-correlation function by using the adjustment information, so as to obtain the adjusted cumulative cross-correlation function; and determining a time corresponding to a maximum value in the adjusted cumulative cross-correlation function as an inter-channel delay. Therefore, the delay between the signals of the left and right sound channels can be estimated correctly, so as to improve the stability of the synthetic stereo sound field.

Abstract: A method of estimating battery lifetime includes monitoring a charge characteristic of a battery during a first time period, monitoring an operating condition of the battery, determining a first battery life value for the first time period based on the operating condition of the battery, the charge characteristic, and a duration of the first time period, determining an overall battery life value using the first battery life value and a second battery life value for a second time period, and estimating a remaining battery lifetime for the battery based on the overall battery life value.

Abstract: A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information.

Abstract: A method, device and computer program product for determining at least one property of a current (Ip) running through the primary winding of a transformer operating in saturation using an unreliable detected current (Is) running through the secondary winding of the transformer. According to the invention a first reliable extreme point (EP1) of a cycle of the current in the secondary winding is detected and compared with an absolute time reference. Based on the comparison a first property of the current running through the primary winding in the form of the phase angle is then determined.

Abstract: A system for monitoring the starter battery of a vehicle includes a central processing unit, a voltage sensor, a temperature sensor, a timer, a data store, and a display. A collection of computer software algorithms are executed by the central processing unit to ascertain the operational state of a vehicle's starter battery. The algorithms are operative to determine engine start time, initial start voltage drop, and the charge state of the battery.

Abstract: Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.

Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.

Abstract: Apparatus, having multiple motor modules, has an MCU module. Each motor module has an electronically controlled motor. The MCU module has an MCU and an interface for connecting to a bus from a CPU. In use the MCU module receives control signals from the CPU and in turn instructs a selected one of the motors to operate.

Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

Abstract: Provided is a sampling apparatus that samples a signal under measurement, including a sampling section that samples the signal under measurement with a plurality of sampling phases at non-uniform intervals for each sampling repetition cycle; and an inverting section that cancels out a replica that is not an observation target, from among the replicas in a sampling band of the signal under measurement and the replicas in the sampling band of a frequency component of the signal under measurement, by inverting signs of values of the signal under measurement sampled with at least one sampling phase from among the plurality of sampling phases.

Abstract: An X-ray detection signal processing apparatus of the present invention is such that after a signal from a preamplifier has been converted into a digital signal at a high speed by means of a high speed analog-to-digital converter (1), a process for removing influences brought about by a component that has been decayed by a differential time constant in the preamplifier is performed on a digital basis in a digital signal processing block (2). An event detecting unit (3) within the digital signal processing block (2), smoothen the signal from the high speed analog-to-digital converter (1) for a predetermined shaping time with the use of a filter function for high speed shaping, detects as an event information the timing at which the smoothened signal exceeds a predetermined threshold and attains the maximum value, and add such event information to the signal from the high speed analog-to-digital converter (1).

Abstract: The use time till a display unit including an hour meter (a time measuring device) is replaced can be continued even if the time measuring device fails, and false alteration after shipping can be prevented while infallibly resetting the hour meter to zero when the vehicle equipped with the hour meter is shipped from the factory. The cargo handling vehicle includes a first storage device for accumulatively storing the vehicle use time measured by a first time measuring device provided in a display unit of the vehicle and a second storage device for accumulatively storing the vehicle use time measured by a second time measuring device provided in a control device. The control device allows the first and second storage devices to communicate the accumulated use times stored therein when the electric power of the vehicle is turned on. The control device compares the accumulated use times and writes the longer accumulated use time in the storage device storing the shorter one.

Abstract: In one embodiment, a frequency generator produces an excitation signal, a local oscillator signal, and a reference signal at a difference frequency of the excitation signal and local oscillator signal. The excitation signal is applied to a physical system to produce a response signal, which is mixed with the local oscillator signal. A filter selects a difference frequency component. The frequencies of the excitation signal and/or local oscillator signal are varied, such that the magnitude of the difference frequency is constant, but a sign of the difference frequency changes from positive to negative. The phase shift of the difference frequency component, with respect to the reference signal, at each of the two signs of the difference frequency, is measured. The measured phase shift at the negative sign is subtracted from the measured phase shift at the positive sign, and the difference is divided in half, to produce a result.

Abstract: A system includes a processing module, a sampling module, a period determination module, and a speed determination module. The processing module generates time stamps when pulses are received from a sensor that senses a rotation of a device. The sampling module samples the time stamps during N predetermined intervals and stores N of the time stamps that correspond to the N predetermined intervals, where N is an integer that is greater than 2. The period determination module determines a plurality of periods, wherein each one of the plurality of periods is based on a difference between two of the N time stamps. The speed determination module determines a rotational speed of the device based on a difference between two of the plurality of periods.

Abstract: Methods of rapidly measuring an impedance spectrum of an energy storage device in-situ over a limited number of logarithmically distributed frequencies are described. An energy storage device is excited with a known input signal, and a response is measured to ascertain the impedance spectrum. An excitation signal is a limited time duration sum-of-sines consisting of a select number of frequencies. In one embodiment, magnitude and phase of each frequency of interest within the sum-of-sines is identified when the selected frequencies and sample rate are logarithmic integer steps greater than two. This technique requires a measurement with a duration of one period of the lowest frequency. In another embodiment, where selected frequencies are distributed in octave steps, the impedance spectrum can be determined using a captured time record that is reduced to a half-period of the lowest frequency.

Abstract: In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: An industrial process device for monitoring or controlling an industrial process includes a first input configured to receive a first plurality of samples related to a first process variable and a second input configured to receive a second plurality of samples related to a second process variable. Compensation circuitry is configured to compensate for a time difference between the first plurality of samples and the second plurality of samples and provide a compensated output related to at least one of the first and second process variables. The compensated output can comprise, or can be used to calculate a third process variable. The third process variable can be used to monitor or control the industrial process.

Abstract: A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices.

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract: A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.

Abstract: Media monitoring and measurement systems and methods are disclosed. Some embodiments of the present invention provide a media measurement system and method that utilizes audience data to enhance content identifications. Some embodiments analyze media player log data to enhance content identification. Other embodiments of the present invention analyze sample sequence data to enhance content identifications. Other embodiments analyze sequence data to enhance content identification and/or to establish channel identification. Yet other embodiments provide a system and method in which sample construction and selection parameters are adjusted based upon identification results. Yet other embodiments provide a method in which play-altering activity of an audience member is deduced from content offset values of identifications corresponding to captured samples.

Abstract: In a low voltage differential signal (LVDS) timing test system and method, a clock signal waveform and a data signal waveform are obtained. Clock cycles are selected from the clock signal waveform. Data bits transmitted within the selected clock cycles are identified from the data signal waveform. Accordingly, bit positions of the data bits are determined.

Abstract: The described apparatus and methods use Time Domain Reflectometry (TDR) to determine the absolute volumetric moisture content of various media. The effects of dispersion caused by conductive and dielectric properties of the medium on the waveform are extrapolated by detecting the bulk propagation time and the slope of the distorted transition of the characteristic reflected waveform. Fast transitions are injected by a differential step function generator into a two-conductor waveguide, which is immersed in soil or other medium of interest. Unlike previous single-ended TDR systems, a differential digitizer senses the probes. Timing control between the two digitizers is critical. Use of an integrated fully differential system eliminates the need for a coaxial cable and an associated balancing transformer, or balun. This enables a two-conductor probe that is more easily inserted into soil, rather than requiring three conductors.

Abstract: Various systems and methods for analysis of optical pulses are provided. In one embodiment, a method is provided including obtaining a plurality of traces produced by propagating an unknown pulse and a reference pulse along a pair of crossing trajectories through a spectrometer, where each trace is associated with a delay between the unknown pulse and the reference pulse. Each trace is spatially filtered to generate a plurality of spatially filtered electric field measurements, which are temporally filtered to generate a plurality of temporally filtered electric field measurements. The plurality of temporally filtered electric field measurements are concatenated based at least in part upon the delay associated with the corresponding trace to generate a concatenated wave form corresponding to the unknown pulse.

Abstract: Provided is a sampling apparatus that samples a signal under measurement, including a sample processing section that outputs sample data obtained by sampling the signal under measurement with a sampling timing at non-uniform intervals obtained by thinning a reference clock, a storage section that stores the sample data, and a waveform generating section that generates a waveform of the signal under measurement based on the sample data read from the storage section. The sample processing section includes a sampler that samples the signal under measurement in synchronization with the reference clock and a data thinning section that thins the sample data output by the sampler and outputs this thinned data as sample data with the sampling timing at non-uniform intervals.

Abstract: An in-situ gas flow measurement controller measures the temperature and rate of pressure drop upstream from a flow control device (FCD). The controller samples the pressure and temperature data and applies the equivalent of a decimating filter to the data to produce filtered data at a slower sampling rate. The controller derives timestamps by counting ticks from the sampling clock of the A/D converter that is sampling the pressure at regular intervals to ensure the timestamps associated with the pressure samples are accurate and do not contain jitter that is associated with software clocks. The controller additionally normalizes the temperature reading to account for power supply fluctuations, filters out noise from the pressure and temperature readings, and excludes data during periods of instability. It calculates the gas flow rate accounting for possible non-linearities in the pressure measurements, and provides the computed gas flow measurement via one of many possible interfaces.

Abstract: A circuit measures a time interval between a first event and a second event. One or more activity inputs receive a respective signal indicating the first and second events. For each activity input, a respective high-speed serial receiver includes a sampling circuit and a deserializer. The sampling circuit generates sample bits from sampling the respective signal at active edges of a clock signal. The deserializer converts the sample bits into a sequence of parallel data words. The sample bits undergo a first change in response to the first event and a second change in response to the second event. An arithmetic circuit receives the sequence of parallel data words from the respective high-speed serial receiver. The arithmetic circuit determines a number of the sample bits between the first and second changes in the sequence of parallel data words. The number measures the time interval between the first and second events.

Abstract: A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage.

Abstract: A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively.

Abstract: Disclosed is a system and related methodology for providing fast low frequency jitter rejection in the measurement of signals under test. A signal under test may be sampled alternately with a reference signal under similar conditions. The resulting sampled signal blocks may then be processed to subtract the known calibrated value of the reference signal from the average signal under test.

Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Abstract: A state switching device for switching the states of a device by detecting a battery voltage of the device is provided. The device includes a voltage dividing circuit to provide an output voltage in proportion to the battery voltage, and a detection unit which includes a voltage detection module, a comparison module, a control module and a state detection module to obtain the device's state. The voltage detection module produces a digital detection voltage according to the output voltage at normal time intervals, the comparison module detects whether the digital detection voltage is lower than a reference voltage corresponding to the state. If yes, the voltage detection module obtains digital detection voltage at abnormal time intervals. The comparison module compares a predetermined number of digital detection voltages with the reference voltage to produce comparison results. The control module determines whether to maintain the device's state according to the comparison results.

Abstract: At least a method and a system are described for monitoring and measuring one or more parameters in an integrated circuit chip by way of receiving a first voltage, a second voltage, and a control signal. In a representative embodiment, the first voltage is used for powering a probe and the second voltage is used as a voltage reference for voltage measurement within the integrated circuit chip. In one or more representative embodiments, the one or more parameters measured comprise minimum and maximum voltage levels of a signal, sampled voltage levels of a signal, a period of a signal, a duty cycle of a clock signal, a jitter of a clock signal, and/or a temperature at a location within the integrated circuit chip.

Abstract: A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.

Abstract: Touchscreen testing techniques are described. In one or more implementations, a piece of conductor (e.g., metal) is positioned as proximal to a touchscreen device and the touchscreen device is tested by simulating a touch of a user. This technique may be utilized to perform a variety of different testing of a touchscreen device, such as to test latency and probabilistic latency. Additional techniques are also described including contact geometry testing techniques.

Abstract: Methods, systems, and apparatus provide an accurate time constant for electroporation. A model voltage function is created (analog, digital, or combination) to provide a model voltage having the desired time constant. A voltage is applied to the sample. A comparing circuit compares the output voltage, which may be attenuated, to the model voltage and provides an output control signal. This output signal is used to modify a resistance in parallel with the sample, thereby altering the output voltage to approximate the model voltage, which has the desired time constant. In one aspect, the control signal may be used to turn on and off a transistor that is in series with a resistor in order to modify the parallel resistance.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device can issue two new general call commands, CALIBRATE and ZERO COUNTERS. The I2C Bus slave devices respond to the CALIBRATE command by counting the number of cycles its local, private oscillator makes through during the communication transfer period of the CALIBRATE command on the I2C Bus. All such I2C Bus slave devices measure the same communication transfer period on the I2C Bus, so the differences in the digital measurements obtained by each of them are proportional to their respective oscillator frequencies. The digital measurements are privately used by each I2C Bus slave device to calculate appropriate oscillator prescale factors, and to automatically load the values that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.

Abstract: A device and method corrects time data based on a clock signal affected by jitter. The error due to jitter in a time measurement of an event in the clock signal is determined at the time of the event or as an average over a number of events. A measurement is made of a time dependent reference variable associated with a long-time constant device, such as a capacitor, which is relatively immune to localized jitter. The measurement may be a reading of the voltage across a charging capacitor. The measured value is compared to an expected value, and the time error is based on the result. The expected value may be stored or calculated from known charging rates of the capacitor. The error due to jitter of a time measurement is approximately linearly proportional to the difference in voltage between the measured and the expected values of the capacitor.

Abstract: A system and method to measure a delay of an individual logic gate in an unmodified form on a chip using a digitally reconfigurable ring oscillator (RO) that is on the chip is provided. A system of linear equations is established for different configuration settings of the ring oscillator and solved to determine a delay of an individual gate.

Abstract: A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as a field programmable gate array (FPGA). The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions.

Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.

Abstract: An apparatus for detecting a real time clock frequency offset includes: an overlap detecting unit detecting an overlap signal having overlap information of a predetermined reference clock and a predetermined real time clock; an envelope signal creating unit creating an envelope signal having envelope information of the overlap signal; and a frequency counter unit calculating a frequency of the envelope signal that is a frequency offset of the real time clock, by using a first clock number created by counting the reference clock for one period of the envelope signal and a frequency of the reference clock.

Abstract: A magnetic field sensor including a bidirectional node is configured to perform at least one of generating sensor data, storing sensor data, or communicating sensor data in a serial data signal in response to a trigger signal received at the bidirectional node. An alternative sensor having a node that may or may not be a bidirectional node is configured to reset at least one of a sensor data signal, a clock, a register, or a counter in response to a trigger signal received at the node and is further configured to communicate the sensor data signal in response to the trigger signal.

Abstract: A time differential is estimated between a plurality of signals by determining a filter response of a first electrical signal with a first filter array, determining a filter response of a second electrical signal with a second filter array, and determining, based at least on the filter response of the first electrical signal and the filter response of the second electrical signal, a time differential between the first electrical signal and the second electrical signal. A first optical signal is converted into the first electrical signal and a second optical signal is converted into the second electrical signal. The filter response of the first electrical signal and the filter response of the second electrical signal are sampled and the time differential between the first electrical signal and the second electrical signal is determined based at least on the sampled filter response of the first electrical signal and the sampled filter response of the second electrical signal.

Abstract: Method, apparatus, and system, including computer program products, implementing and using techniques for time series analysis, wherein the time series exhibit trend and/or seasonality. Model parameters of the time series data are determined by selecting and/or suggesting a most appropriate combination of trend and seasonality of the time series data based on analysis of variances of transformed time series data.