Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.

Abstract: Two or more sets of measurement data can be independently collected from causally related characteristics or elements. Such measurements can be synchronized with one another through the identification of a correct offset between their measurement data. An identification of the nature of the causal relationship between the measured characteristics can identify relevant ranges within which the aggregate values of one of the measurements can be obtained. As the offset between the measurements is adjusted, the aggregate values can change and a derivative, or other meaningful function based on the aggregate values can be calculated. The meaningful function, or subsequent functional result of it, can inform a range of offsets within which a local extreme value can be identified. The offset corresponding to such a local extreme value can be the correct offset.

Abstract: An apparatus has an input section arranged to receive values representative of the total instantaneous supply of electrical current as a function of time from an alternating voltage supply. Current waveforms comprising sets of values representative of the cyclic waveform of the electric current supply are obtained. A delta waveform generator calculates the difference between a current waveform and an earlier current waveform. An edge detector is arranged to detect an edge or edges in the delta waveform. An analysis section is arranged to identify at least one appliance load based at least on information on the edge or edges detected by the edge detector, and to determine the electrical energy consumed by said appliance load. Another apparatus has an input section arranged to receive values representative of the current supplied to an installation, such as a house. A store contains appliance data characteristic of the use of electricity by each of a plurality of appliances.

Abstract: A failure determination device for a cell voltage monitor is provided. The cell voltage monitor detects cell voltages of a plurality of single cells. The failure determination device includes a minimum value determination unit for determining whether or not a present cell voltage which the cell voltage monitor detects is equal to or lower than a minimum detectable cell voltage, and a failure determination unit for determining that the cell voltage monitor has a failure. A failure is detected when the present cell voltage is equal to or lower than the minimum value cell voltage, and a cell voltage detected by the cell voltage monitor in the past and stored in the memory is greater than a determination cell voltage.

Abstract: In a low voltage differential signal (LVDS) timing test system and method, a clock signal waveform and a data signal waveform are obtained. Clock cycles are selected from the clock signal waveform. Data bits transmitted within the selected clock cycles are identified from the data signal waveform. Accordingly, bit positions of the data bits are determined.

Abstract: The invention is related to a method and a circuit for determining a value, particularly a duration, of a test signal, in which a timer is executed with a first clock-state change of a clock to apply a control signal to at least a first of at least two delay elements. The delay elements are executed to produce different time-delayed comparison signals. A comparator arrangement with at least one comparator with comparator inputs, to apply the differently delayed comparison signals and the instantaneous test signal, is designed to determine, from the respective applied comparison signal and the test signal, a comparison result, whereby the sequence of the comparison results forms a differential value for the test signal.

Abstract: A calculation method of electromagnetic interference reduction through spectrum diffusion that is for reducing the electromagnetic interference, in which, when a center frequency of a measurement bandwidth is changed so that a spectrum having the maximum amplitude is included in the measurement bandwidth, of a plurality of spectra generated from the frequency spectrum of an electromagnetic interference signal through the spectrum diffusion, the amplitudes of all spectra included in the measurement bandwidth are added up and the maximum total sum of the amplitudes is divided by the amplitude of the electromagnetic interference signal, hence to estimate the electromagnetic interference reduction.

Abstract: In a receiver of electromagnetic or other waves, scaling of received frequencies in proportion to the respective source distances, so as to reveal the source distances and permit isolation of signals from a particular source by simple spectral filtering. Phase differences between transmitted frequencies due to the common source path lead to chirp eigenfunctions registering in the receiver as scaled frequencies. The chirps are extracted by implementing exponentially varying path delays in autocorrelators and diffractive spectrometers say using a medium with variable refractive index. Analogous exponentially varying phase shifts are applied to successive samples in the kernel of discrete Fourier transform implementations. Advantage lies in enabling distance-dependent frequency scaling in autocorrelation spectroscopy, as well as in conventional diffractive or refractive spectrometers or digital signal processing with uniform sampling.

Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

Abstract: In one embodiment, a multi-path ultrasonic flow meter for determining the flow rate of a fluid in a conduit is disclosed comprising at least two transducer pairs attached to the conduit at two chord locations, one greater than and one less than a mid-radius chord, wherein the composite ratio the two path velocities to the flow rate is substantially constant over the range of Reynolds numbers. In another embodiment, a method of determining the flow rate of a fluid in a conduit is disclosed comprising the steps of determining a composite velocity by determining a weighted average of a plurality of path velocities, determining a chord velocity ratio based on the path velocities, determining a profile correction factor based on the composite velocity and the chord velocity ratio, and determining the flow rate based on the composite velocity and the profile correction factor.

Abstract: A time differential is estimated between a plurality of signals by determining a filter response of a first electrical signal with a first filter array, determining a filter response of a second electrical signal with a second filter array, and determining, based at least on the filter response of the first electrical signal and the filter response of the second electrical signal, a time differential between the first electrical signal and the second electrical signal. A first optical signal is converted into the first electrical signal and a second optical signal is converted into the second electrical signal. The filter response of the first electrical signal and the filter response of the second electrical signal are sampled and the time differential between the first electrical signal and the second electrical signal is determined based at least on the sampled filter response of the first electrical signal and the sampled filter response of the second electrical signal.

Abstract: Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

Abstract: Embodiments of the present invention relate to managing timestamps associated with received data. According to one embodiment, data is collected from a device that generates data at a specified rate, but which lacks a built-in clock. An accurate timestamp is assigned to the data by first taking an absolute timestamp from a reference clock, and then adding a calculated amount of time to each subsequent data point based on an estimate of the sampling frequency of the device. As the generated timestamp drifts from the actual reference clock time, the sampling frequency is re-estimated based on the amount of detected drift.

Abstract: A timing lock detection apparatus and method for digital broadcasting receiver are provided. The apparatus includes: a discrete value generator for cyclically selecting a discrete signal value from a continuous timing error signal; a differential calculator for obtaining a difference between the currently selected timing error signal value and a previously selected timing error signal that is a timing jitter signal; a sign variation detector for detecting variation in a sign of the timing jitter signal; a lock control signal generator for discriminating a period based on the detected sign changing time, and controlling a lock step of the loop filter according to a convergence mode of the timing jitter signal at each period; and a lock detection signal generator for generating a lock signal or an unlock signal according to whether the timing jitter signal reaches a steady state and using the current lock step signal.

Abstract: Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device is capable of issuing two new general call commands, MEASURE PULSE and RESET PRESCALE. The I2C Bus slave devices respond to the MEASURE PULSE command by returning a digital count related to the number of ticks its local, private oscillator cycles through during a signal pulse on the I2C Bus. All such I2C Bus slave devices measure the same signal pulse on the I2C Bus, so the differences in the digital measurements returned during the MEASURE PULSE command are proportional to their respective oscillator frequencies. The various digital measurements returned are used to calculate appropriate oscillator prescale factors that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.

Abstract: A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Abstract: A computer-implemented method of signal processing is provided. The method includes generating one or more masking signals based upon a computed Fourier transform of a received signal. The method further includes determining one or more intrinsic mode functions (IMFs) of the received signal by performing a masking-signal-based empirical mode decomposition (EMD) using the at least one masking signal.

Abstract: An integrated circuit and method for monitoring and controlling power and for identifying an open circuit state at an output port is disclosed. A circuit is implemented to determine whether an open circuit state exists based on a comparison of data received from the output port and attached loads. The data received from the output port and attached loads is compared to a minimum open circuit current value of the output port, wherein the minimum open circuit current value is based on the hardware characteristics of the output port and attached loads. A possible open circuit state at the output port is reported based on the comparison.

Abstract: Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by compar

Abstract: A demodulation apparatus that demodulates an amplitude-phase-modulated signal having a level and a transition phase selected from among a plurality of levels and a plurality of phases according to transmission data, comprising a clock recovering section that receives the amplitude-phase-modulated signal and recovers a clock signal synchronized with the amplitude-phase-modulated signal; an amplitude and phase detecting section that detects, with the clock signal as a reference, the level and the transition phase of the amplitude-phase-modulated signal; a data output section that outputs data corresponding to the level and the transition phase detected by the amplitude and phase detecting section; and a phase difference correcting section that outputs a correction signal for correcting an oscillation frequency of the clock signal output by the clock recovering section, according to the transition phase detected by the amplitude and phase detecting section.

Abstract: A controllable delay element is coupled in parallel with a calibration circuit. The calibration circuit receives a periodic reference signal and generates a series of sample voltages responsive to a time-varying analog voltage, the periodic reference signal, and the delayed periodic signal at the output of the controllable delay element. The calibration circuit distributes the series of sampled voltages for determining the components of a first vector. The first vector components are used to calculate the phase that results from a control signal applied to the controllable delay element. After the control signal is modified, a second vector is used to calculate the phase that results from the control signal. The delay can be determined by the product of the period of the reference signal and the difference in phase.

Abstract: A mechanism for measuring the absolute duty cycle of a signal is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: A system for acquiring an ultrasound signal comprises a signal processing unit adapted for acquiring a received ultrasound signal from an ultrasound transducer having a plurality of elements. The system is adapted to receive ultrasound signals having a frequency of at least 20 megahertz (MHz) with a transducer having a field of view of at least 5.0 millimeters (mm) at a frame rate of at least 20 frames per second (fps). The signal processing can further produce an ultrasound image from the acquired ultrasound signal. The transducer can be a linear array transducer, a phased array transducer, a two-dimensional (2-D) array transducer, or a curved array transducer.

Abstract: A method and an apparatus for calculating the separation time of the arcing contacts of a high-voltage switchgear which is operatively coupled to a synchronous switching device and to an auxiliary switch having auxiliary contacts operatively connected to the arcing contacts. During execution of a predefined test condition the separation time of the arcing contacts and of the auxiliary contacts is measured. The time delay between the measured separation time of the arcing contacts and of the auxiliary contacts is calculated. Upon separation of the arcing contacts under an operating condition other than the predefined test condition, the separation time of the auxiliary contacts is measured. Then, the separation time of the arcing contacts is calculated as the difference between the separation time of the auxiliary contacts measured during the operating condition other than the predefined test condition and the calculated time delay.

Abstract: A method and apparatus for anti-islanding of distributed power generation systems having an inverter comprising a phase locked loop (PLL), a phase shift generator for injecting a phase shift into the PLL during at least one sample period, and a phase error signature monitor for monitoring at least one phase error response of the PLL during the at least one sample period.

Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: Systems and methods are described for transmitting a waveform having a controllable attenuation and propagation velocity. An exemplary method comprises: generating an exponential waveform, the exponential waveform (a) being characterized by the equation Vin=De?ASD[x?vSDt], where D is a magnitude, Vin is a voltage, t is time, ASD is an attenuation coefficient, and vSD is a propagation velocity; and (b) being truncated at a maximum value. An exemplary apparatus comprises: an exponential waveform generator; an input recorder coupled to an output of the exponential waveform generator; a transmission line under test coupled to the output of the exponential waveform generator; an output recorder coupled to the transmission line under test; an additional transmission line coupled to the transmission line under test; and a termination impedance coupled to the additional transmission line and to a ground.

Abstract: A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect.

Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator.

Abstract: An incoming LAN traffic management system comprising: an I/O adapter configured to receive incoming packets from an Ethernet; a plurality of hosts coupled to the I/O adapter and each having a host buffer; a data router configured to block information received by the I/O adapter into memory locations from an SBAL associated with at least one of the plurality of hosts and in accordance with blocking parameters for the at least one of the plurality of hosts, the data router including an expiration engine configured to expire the SBAL before it is full if at least one predetermined threshold is exceeded.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: A frequency error estimation algorithm is presented for use in radio receivers, for example. The present algorithm utilizes irregular time intervals between pilot symbols to improve the frequency range of the estimate. First, a first phase rotation indicator comprising information on phase rotation of a received signal within a first time interval is estimated. Then, a second phase rotation indicator comprising information on phase rotation of the received signal within a second time interval of a different length than the first time interval is estimated. A frequency error estimate is calculated from the phase difference between the first phase rotation indicator and the second phase rotation indicator, for example by dividing the phase difference by the difference in the lengths of the first and the second time interval.

Abstract: Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

Abstract: A technique includes determining a first difference between a time that a first network element of a seismic acquisition network receives a first frame pulse from a second network element of the seismic acquisition network and a time that the first network element transmits a second frame pulse to the second network element. The technique includes determining a second difference between a time that the second network element receives the second frame pulse and a time that the second network element transmits the first frame pulse. The technique includes determining a transmission delay between the first and second network elements based on the first and second time differences.

Abstract: A reference signal generator generating a reference signal for high-resolution measurement/control in real time includes a means for calculating the rotational trend, e.g. increase/decrease in the r.p.m.

Abstract: Potentials at both ends of an exciter coil to which an exciting signal is sent by a push-pull method are compared, and at least one of a short circuit to ground and a short circuit to a power supply of a signal line for the exciting signal is detected based on the duty cycle of a rectangular-wave signal indicating the result of comparison. Alternatively, a predetermined reference potential is compared with a potential of at least one of two phase detection signals before detection, and at least one of a short circuit to the ground and a short circuit to the power supply of a signal line for the at least one of the detection signals is detected based on the duty cycle of a rectangular-wave signal indicating the result of comparison.

Abstract: Systems, processes and apparatus are described through which signals are received from a controller, where the signals include a power ON signal. A time measurement element is started responsive to the power ON signal to assess a current duration of operation of the system. An existing cumulative record of system operation is recalled from a non-volatile memory in the system and the existing cumulative record is combined with the current duration to provide a representation of a running elapsed time, which is recorded in the non-volatile memory and is compared to a threshold to provide an indication when the running elapsed time has traversed the threshold.

Abstract: A method for estimating values assumed at a certain instant of each period by currents flowing respectively in two distinct windings of a poly-phase load controlled in a space vector modulation (SVM) mode, using a same measuring device, may include coupling the measuring device to the first winding and measuring a current flowing therethrough with an anticipation from the certain instant smaller than or equal to an SVM half-period. The method may also include coupling the measuring device to the second winding, measuring a current flowing therethrough at the certain instant, coupling the measuring device to the first winding, and measuring a current flowing therethrough with a delay equal to the anticipation. The method may also include estimating a value assumed at the certain instant by the current flowing through the first winding based upon the two measured values with the anticipation and with the delay respectively.

Abstract: A system and method to measure, with increased precision, the transit time position(s) of pulses in a time domain data. An example data set would be the transit time of pulses in Time-Domain Terahertz (TD-THz) data. The precision of the pulse timing directly affects the precision of determined sample properties measurements (e.g., thickness). Additionally, an internal calibration etalon structure and algorithm method provides for continuous system precision/accuracy check method to increase sample measurement integrity. The etalon structure can improve the precision of sample property measurements (e.g., absolute thickness). Various hardware and system implementations of the above are described.

Abstract: A system and method for monitoring a condition and an operation of a periodically moving object is provided. Herein a synchronized time average is calculated for a measurement signal, the signal containing periodical variations and obtained from the object response. In general, a frequency response is determined based on the periodical variations of the measurement signal. A signal component representing the determined frequency response is filtered from the measurement signal. The filtered signal is used as a synchronizing signal. A synchronized time average of sequences, determined by dividing the measurement signal by the synchronizing signal, is calculated.

Abstract: A method for identifying a delay-susceptible control path in the control of a steam generator and a device constructed for carrying out the method are provided. A model structure of the steam generator is specified, consisting of an unknown time-variable Nth-order delay element and a known integrator. Also used for the identification are measurements of the fuel mass flow, the turbine stream mass flow, and the live stream pressure which arises in the steam accumulator behind the steam generator after the removal of the turbine steam mass flow. Using these online measurements and the model structure, the live steam mass flow at the output of the steam generator is derived by calculation. In this way, the input value and the output value of the Nth-order delay element are determined and, using an estimation method, the parameters of a continuous transmission function of the Nth-order delay element are also determined online.

Abstract: A system and method for determining one of a plurality of power line phase conductors to which a remote device is electrically connected via a low voltage power line and transformer, and wherein each power line conductor carries a different phase of power is provided. In one embodiment, the method includes transmitting a different data beacon at a zero crossing of a voltage of the power of each of a plurality of power line phase conductors and storing in a memory information of the data beacon transmitted at the zero crossing of each phase conductor. At the remote device the method includes receiving a first data beacon, determining whether the first data beacon was received at a zero crossing of the voltage, and if the first data beacon was received at a zero crossing of the voltage, transmitting a phase notification that includes information of the first beacon and information identifying the remote device from the remote device.

Abstract: Using fabrication-time variation predicting means that predicts this fact, the variation is predicted beforehand at the design stage prior to fabrication and is stored in variation prediction storage means. Rather than measuring a delay, testing an operation is performed (by a pass/fail determination) by actual-speed logic operation testing means for checking, after fabrication, whether a flip-flop (FF) operates at a specified operation frequency. As a result, the variation is estimated using the non-operation flip-flop (FF) information and the predicted value of the variation from the fabrication-time variation predicting means, and a delay value which corrects for the variation is inserted into a fabricated semiconductor integrated circuit by post-fabrication delay insertion position/value determining means using the variation value that has been estimated.

Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.

Abstract: A system and method for determining one of a plurality of power line conductors to which a remote device is electrically connected is provided. In one embodiment the method includes transmitting a data beacon, determining a relative time period associated with each power line conductor between a zero crossing of the voltage of the power line conductor and the transmission of the data beacon, receiving the data beacon with the remote device, determining a first time period between reception of the data beacon and a zero crossing of a voltage at the first remote device, and transmitting data of the first time period to a computer system. The method further includes with the computer system receiving the data of the first time period, determining that the first time period satisfies a similarity threshold with a relative time period associated with a first power line conductor, and storing in a memory information associating the first remote device with the first power line conductor.