Abstract: Using fabrication-time variation predicting means that predicts this fact, the variation is predicted beforehand at the design stage prior to fabrication and is stored in variation prediction storage means. Rather than measuring a delay, testing an operation is performed (by a pass/fail determination) by actual-speed logic operation testing means for checking, after fabrication, whether a flip-flop (FF) operates at a specified operation frequency. As a result, the variation is estimated using the non-operation flip-flop (FF) information and the predicted value of the variation from the fabrication-time variation predicting means, and a delay value which corrects for the variation is inserted into a fabricated semiconductor integrated circuit by post-fabrication delay insertion position/value determining means using the variation value that has been estimated.

Abstract: A system and method for determining one of a plurality of power line conductors to which a remote device is electrically connected is provided. In one embodiment the method includes transmitting a data beacon, determining a relative time period associated with each power line conductor between a zero crossing of the voltage of the power line conductor and the transmission of the data beacon, receiving the data beacon with the remote device, determining a first time period between reception of the data beacon and a zero crossing of a voltage at the first remote device, and transmitting data of the first time period to a computer system. The method further includes with the computer system receiving the data of the first time period, determining that the first time period satisfies a similarity threshold with a relative time period associated with a first power line conductor, and storing in a memory information associating the first remote device with the first power line conductor.

Abstract: A method of detecting a pileup in an energy-dispersive radiation spectrometry system, wherein a filter of the system generates a first pulse in response to a preamplifier signal, and wherein the system has one or more fast channels having an energy of full efficiency wherein substantially all photons received having at least the full efficiency energy are detected. The method includes measuring an above threshold time duration of the filter, determining that the fast channels have not made any detections while the first pulse is above the minimum detectable threshold energy of the filter, in response thereto, declaring a pileup if the above threshold time duration exceeds a longest expected pulse duration that is a duration of a second pulse that would be output by the filter in response to a single photon having an energy equal to the energy of full efficiency being received by the system.

Abstract: A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the “LUT delay chain”), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Abstract: An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control of the loaded value by counting the pulses of the first clock signal and a second clock signal and captures the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the differences of the captured counts taken at two different occurrences of the control signal.

Abstract: A signal generator device for generating at least one periodic signal for use in a data eye scan system. The signal generator comprises a clock input, at least one output and at least one signal generator coupled with the clock input and with the output. The signal generator is at least one token ring with a predetermined number of positions and is operable to propagate at least one token in the ring by moving the token from its current position to a following position dependent on a clock signal from the clock input. The signal generator further comprises a predetermined number of signal value units that each represent a respective predetermined signal value of a predetermined signal waveform and are operable to provide the signal value at an output of the signal generator dependent on a current position of the at least one token in the token ring.

Abstract: A time-of-flight PET nuclear imaging device (A) includes radiation detectors (20, 22, 24), electronic circuits (26, 28, 30, 32) for processing output signals from each of detectors (20), a coincidence detector (34), a time-of-flight calculator (38) and image processing circuitry (40). A calibration system (48) includes an energy source (50, 150) which generates an electrical or optical calibration pulse. The electrical calibration pulse is applied at an input to the electronics at an output of the detector and the optical calibration pulse is applied to a preselected point adjacent a face of each optical sensor (20) of the detectors. A calibration processor (52) measures the time differences between the generation of the calibration pulse and the receipt of a trigger signal from the electronic circuitry by the coincidence detector (34) and adjusts adjustable delay circuits (44, 46) to minimize these time differences.

Abstract: Systems and methods are provided for acquiring seismic data using a wireless network and a number of individual data acquisition modules that are configured to collect seismic data and forward data to a central recording and control system. In one implementation, a number of remote modules (301) are arranged in lines. Base station modules (302) receive information from the lines and relay the information to a central control and recording system (303). Radio links operating on multiple frequencies (F1-F12) are used by the modules (301). For improved data transfer rate, radio links from a remote module (301) leap past the nearest remote module to the next module closer to the base station.

Abstract: An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.

Abstract: A D/U ratio is measured for desired and undesired signals in a wireless video transmission system at a shared channel frequency based on a received signal at a geographic location in proximity to regions within respective service areas for the desired and undesired signals. A video tuner demodulates the received signal to generate a baseband video signal. A leveling circuit normalizes the baseband signal. A video processor identifies horizontal sync pulses within the baseband signal, generates a sampled signal comprising the horizontal sync pulses, and removes components of the desired signal from the sampled signal to generate an undesired signal component. A D/U analyzer determines a Fourier transform having a plurality of bins in response to the undesired signal component, identifies at least one of the bins having a spectral peak corresponding to an undesired signal, and calculates the D/U ratio in response to a magnitude of the identified peak.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: A communication system is provided which is capable of easily setting a transmission speed between a signal transmitter and a signal receiver to carry out information communication. A transmitting device transmits one frame of measuring data which contains a start bit to be added to a head of the data and a stop bit to be added to an end of the data and which is used for a signal receiver to measure a transmission speed. A framing error detector in a receiving device receives the measuring data for detection, at every measuring point, of a framing error which occurs when a transmission speed of the signal transmitter does not coincide with a transmission speed of the signal receiver and normal detection of a stop bit is impossible and generates information about detection of a framing error. A transmission speed measurer measures a transmission speed of the transmitting device based on information about detection of a framing error and measuring point interval time.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device is capable of issuing two new general call commands, MEASURE PULSE and RESET PRESCALE. The I2C Bus slave devices respond to the MEASURE PULSE command by returning a digital count related to the number of ticks its local, private oscillator cycles through during a signal pulse on the I2C Bus. All such I2C Bus slave devices measure the same signal pulse on the I2C Bus, so the differences in the digital measurements returned during the MEASURE PULSE command are proportional to their respective oscillator frequencies. The various digital measurements returned are used to calculate appropriate oscillator prescale factors that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.

Abstract: The invention relates to a method and to a switching device (4) and a measurement system (1). In the method according to the invention for determining time differences between measurement signals measured by at least two couple measurement devices (2, 3), a time basis signal is first generated for the measurement devices (2, 3). A common reference signal is further generated by a signal generator (5). The common reference signal is fed to measurement signal inputs (8, 9) of the coupled measuring devices (2, 3) via the switching device (4). A measurement signal is then fed to said measurement signal inputs (8, 9) of the coupled measuring devices (2, 3) and the time position of the measurement signals relative to the reference signal is determined in each of the coupled measuring devices (2, 3).

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

Abstract: Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

Abstract: A user configured measurement display system and method for a non-destructive testing device and instrument (NDT/NDI) with high input data rate is disclosed. The system and the method provide the means for NDT/NDI instruments display measurement values that satisfies user designated measurement criterion occurring during any measurement time intervals (MTIs). The present disclosure overcomes the shortcomings of conventional ways of picking and displaying measurement values at fixed MTIs, by which the values truly satisfying the measurement criterion that occurs at random MTIs (other than scheduled MTIs) are often skipped.

Abstract: A method for testing a data transfer rate of an electronic device includes: receiving data transmitted from the electronic device and converting the data into test data; analyzing the test data; encoding the analyzed data to generate output data; and displaying a state of the data transfer rate based on the output data.

Abstract: A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

Abstract: A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measurements and serially sent out. The measurements are illustratively accomplished using a reference clock and a phase locked loop.

Abstract: An apparatus and a method for detecting a nonlinearity in a cable plant and for determining cable length to a source of the nonlinearity are disclosed. Upstream signal peaks are detected by averaging upstream signal waveforms. The upstream signal peaks are generated at the source of the nonlinearity from naturally occurring downstream signal peaks propagating in the cable plant. The downstream signal peaks occur due to constructive superposition of the downstream channel signals. Acquisition of the upstream signal waveforms is triggered by the downstream signal peaks. The cable length to the source of nonlinearity is determined from a time delay between the downstream signal peaks and the upstream signal peaks.

Abstract: A cable testing system that tests cable includes a pulse generation module that transmits a first pulse on a first communications channel of the cable. A sampling module waits a predetermined time period after the pulse generation module transmits the first pulse and then detects a first amplitude of a reflected signal on a second communications channel of the cable. A time domain reflection (TDR) module receives the first amplitude and verifies proper operation of the cable based on the first amplitude. The predetermined time period corresponds with an estimated roundtrip propagation delay of the first pulse when the first pulse is reflected back to the cable testing system after traveling a first predetermined distance along the cable. The sampling module incrementally increases the predetermined time period during subsequent iterations of a cable test in order to verify proper operation of a predetermined segment of the cable.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: In one embodiment, a frequency generator produces an excitation signal, a local oscillator signal, and a reference signal at a difference frequency of the excitation signal and local oscillator signal. The excitation signal is applied to a physical system to produce a response signal, which is mixed with the local oscillator signal. A filter selects a difference frequency component. The frequencies of the excitation signal and/or local oscillator signal are varied, such that the magnitude of the difference frequency is constant, but a sign of the difference frequency changes from positive to negative. The phase shift of the difference frequency component, with respect to the reference signal, at each of the two signs of the difference frequency, is measured. The measured phase shift at the negative sign is subtracted from the measured phase shift at the positive sign, and the difference is divided in half, to produce a result.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

Abstract: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Abstract: At least one exemplary embodiment of to present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count, and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.

Abstract: Apparatus and methods for discriminating late software commands sent to hardware from software executed by a processor. The apparatus, in particular, includes a storage device configured to receive information concerning a timing requirement for software commands transmitted from a microprocessor, where the timing requirement is dependent on a system time. A time counter is also included and configured to determine the system time. The apparatus further includes a comparator configured to determine whether the timing requirement has been met, and a switching circuit configured to selectively allow the software command to be issued from the processor to a hardware circuit based on the determination of whether the timing requirement has been met. Complementary methods are also disclosed.

Abstract: A delay amount estimating apparatus includes a delay value search section that searches for a first delay value smaller than a delay setting value at which a given correlation value between an input signal and a feedback signal is provided, and also for a second delay value greater than the delay setting value, the feedback signal coming from a signal processing apparatus that applies signal processing on the input signal, wherein respective correlation values of the first delay value and the second delay value satisfy a given condition; and a delay estimating section that estimates a delay amount of the feedback signal relative to the input signal based on the first delay value and the second delay value.

Abstract: Non-intrusive speech quality assessment method and apparatus for storing a sequence of intercepted packets associated with a call, each packet containing speech data, and an indication of a transmission time of the packet; storing with each intercepted packet an indication of an intercept time of the packet; extracting a set of parameters from the sequence of packets; and generating an estimated mean opinion score in dependence upon the set of parameters. The extracting step comprises the sub steps of: generating a jitter parameter for each packet of the sequence of stored packets; generating a long term average jitter parameter for the stored packet; and generating a differential jitter parameter in dependence upon the jitter parameter for the stored packet and the long term average jitter parameter.

Abstract: A method for detecting a leading edge blanking parameter of a power management chip includes generating a pulse signal and inputting the pulse signal to the power management chip, wherein the amplitude of the pulse signal will cause a PWM signal of the power management chip to change its duty cycle; detecting the PWM signal to generate a detecting result; when the detecting result indicates that the duty cycle of the PWM signal does not change, adjusting a pulse width of the pulse signal to generate an adjusted pulse signal, inputting the adjusted pulse signal to the power management chip and detecting the PWM signal; and when the detecting result indicates that the duty cycle of the PWM signal changes, determining the leading edge blanking parameter of the power management chip according to the pulse width of the pulse signal.

Abstract: A method for calculating the Specific Absorption Rate (SAR) caused in a body by the electric field of a wireless communications device, and comprises using a model of said body. The device is placed in the proximity of the model, and the electric field is measured at discrete points. The method comprises measuring the magnitude of the electric field in points of a first and a second surface in the model. By means of the measured magnitudes, the phase in said points is determined, so that the complex electric field in said points is determined, and the complex electric field in said points is used to determine the complex electric field in said model. The complex electric field is used in order to calculate the SAR value caused by the device.

Abstract: The accumulated change in values representative of actions taken by a processor, such as the number of email messages processed by an email server, in a given time period is determined. Actions are represented as data points on a plot. Look-ahead intervals are defined for each point. Candidate pairs of points are determined for each look-ahead interval by comparing the first value in the look-ahead interval with other values in the look-ahead interval. A candidate pair comprises the first point and another point having a lesser value. If a candidate pair has a value therebetween, the candidate pair is discarded. If, however, a candidate pair has no value therebetween, the first value of the candidate pair is a peak value for the look-ahead interval. The accumulated change is determined by calculating the sum of the peak values, plus the final value, minus the initial value, for the given time period.

Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.

Abstract: In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

Abstract: A time interval analyzer includes a phase comparator which decides whether a measured signal contains a delay quantity for either a positive delay or a negative delay relative to a characteristic value, and a processor circuit which outputs a ratio of a number of the measured signals containing the positive delay and a number of the measured signals containing the negative delay.

Abstract: Systems and methods for midstream determination of varying available bandwidth for streaming content between two network entities are described. During content streaming, a client requests a server to surge the content transmission rate. One or more bandwidth measurements are taken during the surge to determine if the increased transmission rate can be adequately managed. If the increased transmission rate can be adequately managed, the client may request the server to transmit remaining content at a transmission rate that is not greater than the increased, or surged, transmission rate. In a multi-bitrate file scenario, the surge rate may be higher than the rate of the fastest useable stream. In such a case, the fastest useable stream is selected. If the increased transmission rate is not suitable for future transmission, then the rate may remain at the original transmission rate.

Abstract: A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and ?1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: A delay time calculation apparatus that enables all of speaker units constituting a speaker array to contribute to the formation of a combined wavefront directed to an area specified by a user. The delay time calculation apparatus includes a delay time calculation unit that calculates delay times of delayed audio signals supplied to the speaker units such that a ratio at which an evaluation object area is occupied by an area to which an acoustic wave output from each speaker unit reaches earlier than acoustic waves output from the other speaker units falls within a predetermined range. The evaluation object area is a target area to which a combined wavefront of acoustic waves output from the speaker units is directed, or is a perspective projection image of the target area onto a predetermined evaluation plane.

Abstract: Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

Abstract: The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data collection, monitoring, control and response to commands from a tool host with statistically repeatable performance and precision. Embodiments described use prioritized real time operating systems to control of semiconductor manufacturing tools and data collection from tool associated with the sensors. Statistically repeatable responsiveness to selected commands and to sensor inputs during selected recipe steps effectively reduces jitter.

Abstract: The invention relates to a method for producing a time base for a microcontroller and a simple circuit arrangement therefor, which comprises an RC-element having a specific time constant, said element being connected to a connection of the microcontroller. According to said method, the capacitor of the RC element is charged to an initial voltage in a first step, then in a second step, the number of timed impulses is counted until the voltage on the capacitor falls below the initial voltage to a determined percentage of the initial voltage or a voltage threshold value, and then in a third step, the counted number of timed impulses is used as a time base.

Abstract: A testing device for testing a device under test is disclosed. The testing device includes a microprocessor, a measuring module and a computing module. The microprocessor provides a testing signal to the device under test and determines a testing result for the device under test according to at least one signal measurement result. The device under test further generates at least one measuring signal after receiving the testing signal. The measuring module is coupled to the device under test, and measures the at least one measuring signal and generates at least one voltage measurement result and at least one period measurement result. The computing module obtains the at least one voltage measurement result and the at least one period measurement result according to a predetermined manner and generates the at least one signal measurement result.

Abstract: Provided is a signal measurement apparatus, including sampling sections that each sample a signal under measurement having a cycle T with a threshold value, where the threshold values of at least two of the sampling sections are different from each other; a waveform reconfiguring section that shapes a reconfigured waveform having the cycle T by rearranging ordinal ranks of sample values corresponding to each threshold value obtained by the sampling sections, a distribution generating section that generates a timing distribution of edges in the reconfigured waveform corresponding to each threshold value; and a calculating section that calculates rise time or fall time of the signal under measurement based on the timing distribution corresponding to each threshold value.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

Abstract: A biometric apparatus and a method thereof using bio signals are provided. The apparatus includes an ADC, a periodic signal extractor, a template storing portion, a comparator. The ADC performs sampling of an input bio signal to convert the sampled bio signal into a digital signal. The periodic signal extractor extracts the periodic signals from the digital signal. The template storing portion registers a plurality of users and stores periodic signals for the respective registered users in a form of templates. The comparator computes similarity between the periodic signals outputted from the periodic signal extractor and the respective templates to select a template whose similarity is greatest and recognizes a user that corresponds to the selected template as a user who corresponds to the input bio signal.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.