Abstract: Data analysis systems and related methods. An implementation of a method of determining a relationship between a variable of interest and one or more process variables represented by a corresponding plurality of tags may include accessing a data historian including historical data including a variable of interest and a plurality of tags. The method may include defining a plurality of bins, retrieving historical data corresponding with the plurality of bins using the data historian, filtering the historical data for each of the plurality of bins using one or more filters to produce filtered historical data, generating an output display using the filtered historical data for the variable of interest and each of the plurality of tags, and determining which of the plurality of tags correlate with the variable of interest using the output display. The output display may include an overlay CUSUM chart and a correlation plot.

Abstract: A method and apparatus for identifying an islanding condition. In one embodiment, the method comprises altering a phase error response within a phase locked loop (PLL), and determining whether the islanding condition exists based on the altered phase error response.

Abstract: An element damage determination unit calculates a cumulative value of a damage value using a Manson-Coffin law for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Manson-Coffin law change unit changes a Manson-Coffin law based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time.

Abstract: A method and apparatus is provided for setting time positions of measurement gates on a signal under test. Signal transition data is calculated by a processor for multiple signal transitions. Measurement gate start and end positions are set relative to the multiple signal transitions based on the received signal transition data.

Abstract: The method uses a location device and a timing element to determine the location of a protection device at various periods of time. During these periods of time, the human may be participating in a variety of activities and positions.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase.

Abstract: A method of analysis wherein molecular interactions at one or more sensing surface areas are detected and respective response curves representing the progress of each interaction with time are produced, and wherein a resulting set of response curves is subjected to a quality assessment procedure which comprises representing the response curves with one or more quality descriptors, applying a quality classification method to the descriptors to find outliers, and removing the outliers. The invention also relates to an analytical system including means for classifying the response curves with regard to quality, a computer program for performing the classification, and a computer program product containing the program.

Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Abstract: A signal acquisition probe stores compressed or compressed and filtered time domain data samples representing at least one of an impulse response or step response characterizing the signal acquisition probe. The compressed or compressed and filtered time domain data samples of the impulse response or the step response are provided to a signal measurement instrument for compensating the signal measurement instrument for the impulse or step response of the signal measurement instrument.

Abstract: Real-time battery impedance spectrum is acquired using a one-time record. Fast Summation Transformation (FST) is a parallel method of acquiring a real-time battery impedance spectrum using a one-time record that enables battery diagnostics. An excitation current to a battery is a sum of equal amplitude sine waves of frequencies that are octave harmonics spread over a range of interest. A sample frequency is also octave and harmonically related to all frequencies in the sum. The time profile of this signal has a duration that is a few periods of the lowest frequency. The voltage response of the battery, average deleted, is the impedance of the battery in the time domain. Since the excitation frequencies are known and octave and harmonically related, a simple algorithm, FST, processes the time record by rectifying relative to the sine and cosine of each frequency. Another algorithm yields real and imaginary components for each frequency.

Abstract: A method determines a transient response of a sample. The method includes providing a measured magnitude of the Fourier transform of a complex electric field temporal profile of a pulse sequence comprising a first pulse indicative of the transient response of the sample and a second pulse. The method further includes providing an estimated phase term of the Fourier transform of the complex electric field temporal profile of the pulse sequence. The method further includes multiplying the measured magnitude and the estimated phase term to generate an estimated Fourier transform of the complex electric field temporal profile of the pulse sequence. The method further includes calculating an inverse Fourier transform of the estimated Fourier transform, wherein the inverse Fourier transform is a function of time. The method further includes calculating an estimated complex electric field temporal profile of the pulse sequence by applying at least one constraint to the inverse Fourier transform.

Abstract: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A strobe offset control circuit is disclosed. The control circuit comprises a strobe signal input to receive a strobe signal and a data receiver to receive a data signal in response to a sample signal derived from the strobe signal. A calibration enable input is provided to receive a calibration enable signal. The calibration enable signal places the strobe offset control circuit in one of a calibration mode or a receiver mode. In the calibration mode, a phase offset between the data signal and the sample signal is adjusted based on output from the receiver. In the receiver mode, the phase offset between the data signal and the sample signal is not adjusted based on output from the receiver.

Abstract: Disclosed herein are an apparatus and method for synchronizing a signal analyzer. The apparatus includes an Analog-to-Digital Converter (ADC), a signal storage unit, a trigger signal generation unit, a signal acquisition control unit, a signal analysis unit, and a time error control unit. The ADC converts the input signal into a corresponding digital signal. The signal storage unit stores therein the digital signal received from the ADC. The trigger signal generation unit generates a trigger signal for each predetermined period. the signal acquisition control unit acquires the digital signal from a signal acquisition time point. The signal analysis unit calculates the start position of a frame from the digital signal. The time error control unit calculates a time error between the time point at which each trigger signal is generated and the start position of the digital signal, and sets a subsequent signal acquisition time point based on the calculated time errors.

Abstract: The invention as disclosed is of a method to authenticate identify and trace sonar transmissions and echoes by embedding transparent, secure and robust digital watermarks in signal space, where the additional information incurs no cost in bandwidth. The complex short time Fourier transform is selected as the domain for embedding the digital watermark, secured by a secret key, in the time frequency representation of the signal. The watermark is designed through an iterative optimization step. This step insures that the watermarked sonar is also realizable. Selection of the time frequency region for watermarking is driven by avoidance of interference with the sonar itself, or in case of network operation, other watermarks. In addition, the selected time-frequency region remains robust to sound channel and other transmission effects. Sonar echoes are authenticated in the time-frequency plane by a correlation receiver tuned to the watermarked region using the secret key.

Abstract: The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data collection, monitoring, control and response to commands from a tool host with statistically repeatable performance and precision. Embodiments described use prioritized real time operating systems to control of semiconductor manufacturing tools and data collection from tool associated with the sensors. Statistically repeatable responsiveness to selected commands and to sensor inputs during selected recipe steps effectively reduces jitter.

Abstract: A method of estimating the average response time and average I/O size that can be used as an alternative for or addition to existing response time and I/O estimation techniques. One method involves initializing values for an average response time and an average I/O size, and initializing an angle. Measurements of the I/O size and response times are received. The technique involves adjusting the average I/O size using the current value of the average I/O size and the received I/O size measurement. The average response time is adjusted using the current value for the average response time and the received response time measurement. The angle value is adjusted using the adjusted average I/O size, the current angle value and the I/O size and time measurements. The slope and y-intercept of a line, formed by plotting the average I/O size verses response time, can then be reported.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

Abstract: If there are a plurality of activation paths on which a signal propagates during a delay test, multiple-input cells receiving two or more activation paths are extracted by an extraction unit. For the extracted multiple-input cells, whether there is a possibility of occurrence of a multiple-input switching in a multiple-input cell is determined by a determination unit, based on an input timing to each signal multiple-input cell in the two or more activation paths. Then, an occurrence situation of a multiple-input switching is analyzed as one delay cause by an analysis unit, based on a determination result by the determination unit and a result of the delay test.

Abstract: A system including a platform having a receptacle adapted to a bottom of a shoe or foot; securing mechanism, associated therewith; a sole for contacting a ground surface; a mechanism associated with the sole and a platform bottom, including: motor and a thrusting element, activated by the motor, the thrusting element adapted to move between the sole and the platform to apply an upward force against the platform bottom, thereby changing a platform height with respect to the sole; a sensor device adapted to associate with a lower limb, and to produce a locomotion data signal, and a microprocessor, operatively connected to the sensor device and motor, adapted to: receive locomotion information based on the signal; process the locomotion information to determine a locomotion phase, and control a timing of the mechanism, based on the determination, to change the height during a locomotion swing phase.

Abstract: A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.

Abstract: A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latch circuit latches the signal to be tested at an edge timing of an output signal of the oscillator. A gate circuit is provided between a clock terminal of the latch circuit and the oscillator, and makes the output signal of the oscillator pass therethrough for a predetermined period. A clock transfer circuit loads the output signal of the latch circuit at an edge timing of the output signal of the oscillator and performs retiming on the output signal of the latch circuit by using a reference clock.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.

Abstract: A system for storing time series data in a database using round robin includes a user input interface and a round robin database file manager. The interface receives inputs specifying a time period and a sample rate for collection of delta samples. Each sample represents a difference between two subsequent values of the time series data. The manager accumulates the samples over the time period in accordance with the sample rate, calculates a field size for storing the samples for the time period based on a maximum one of the samples, and writes the delta values to the database using the calculated field size. The database is relatable to a plurality of records. Each record corresponds to a respective time period for delta sample collection and has an adjustable field size for delta sample storage based on a maximum delta sample value for the respective time period.

Abstract: There is provided a jitter amplifier circuit for amplifying jitter included in an input signal. The jitter amplifier circuit includes a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate a harmonic component of the input signal, and a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.

Abstract: A model-based system and method for analyzing power source performance and optimizing operational costs are provided. Data from the power source (such as a battery) and/or a device associated with the power source is analyzed and processed to predict an operating life of the power source. This could allow, for example, a power source replacement schedule to be generated for the device. If the analysis indicates that abnormal conditions exist or that any user-defined alerts are warranted, a message could also be sent to an operator terminal. The system and method may continue to monitor the device and thus provide real-time data. The data may also be stored in memory, collected over time, and analyzed or used in various ways. The system and method thus provide a cost effective and reliable analysis of power source performance and any associated operational and replacement costs.

Abstract: A method of power factor correction without using current sensing or a multiplier is disclosed. A generated predictive pulse is used to charge and discharge a power factor correction (PFC) inductor so that the current in the PFC inductor has a similar phase angle as the input AC voltage. Each ON portion of the pulse is used for charging while each OFF portion is used for discharging. As the input voltage increases in phase, the predictive pulse gradually increases in ON time duty and the PFC inductor is charged in increasing amount and discharged in decreasing amount per pulse. When peak is reached the duty ratio is reduced each pulse and the PFC inductor current is reduced along with the input AC voltage source until phase angle reaches 180 degrees and the ON time becomes zero.

Abstract: A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.

Abstract: A system and method of phase compensating transient performance data are provided. Transient performance data are collected for a plurality of parameters, and two of the parameters are selected. A transfer function is applied to the transient performance data for at least one of the selected parameters to thereby generate phase compensated performance data that is representative of a steady state relationship between the selected parameters.

Abstract: A method to achieve an accurate, extremely low power state classification implementation is disclosed. Embodiments include a sequence that matches the data flow from the sensor transducer, through analog filtering, to digital sampling, feature computation, and classification.

Abstract: A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: A method for characterizing a desired property of a fluid downhole is described. In some non-limiting examples, the method comprises receiving an input signal representing sound speed of a fluid downhole, processing the input signal using a correlation equation expressing the desired property in terms of at least sound speed to produce an output signal representing the desired property, and outputting the output signal. In some examples, the correlation equation is derived through a chemometric analysis of a training data set, the training data set comprises a plurality of input values and a plurality of output values derived from said input values, between the desired fluid property and the first measured property, and the output values are calculated from the input values using a series of correlation equations. In at least one example, the desired property is gas oil ratio. In another example, the desired property is gas brine ratio.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

Abstract: In an example configuration, a power supply manager receives an output current value representing an amount of output current supplied by one or more power converter phases to a load. The power supply manager also receives a duty cycle value representing a duty cycle for controlling operation of the at least one power converter phase. The power supply manager produces an estimate of input current supplied to the power supply circuit based at least in part on multiplying the output current value by the duty cycle value. Contrary to conventional methods such as physically measuring an input current using complex measuring circuitry, embodiments herein include utilizing parameter information such as output current information and duty cycle information to deduce an amount of input current.

Abstract: A method and system for continuously predicting an input line power waveform frequency of alternating current having maximum and minimum values, and a reference value located therebetween by specifying an outer window defining a sense point of the waveform between lower and upper limits of the outer window, the sense point being located away from the reference value and having a corresponding predicted sense point time; providing an inner window having an inner time interval less than an outer time interval corresponding to time between the lower and upper limits; positioning the inner window at the predicted sense point time; identifying an actual sense point time of a measured inner sense point value and excluding one or more identified actual outer sense point values being both outside of the inner time interval and within the outer time interval; and calculating the frequency of a future cycle of the waveform.

Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of threshold voltage VT logic libraries. Each hardware performance monitor is associated with one of the plurality of threshold voltage VT logic libraries and provides a signal that measures a performance of its respective threshold voltage VT logic library die temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and provided to an advanced power controller for use in providing adaptive voltage scaling for the integrated circuit system.

Abstract: Systems and methods for locating the shooter of supersonic projectiles are described. The system uses at least five, preferably seven, spaced acoustic sensors. Sensor signals are detected for shockwaves and muzzle blast, wherein muzzle blast detection can be either incomplete coming from less than 4 sensor channels, or inconclusive due to lack of signal strength. Shooter range can be determined by an iterative computation and/or a genetic algorithm by minimizing a cost function that includes timing information from both shockwave and muzzle signal channels. Disambiguation is significantly improved over shockwave-only measurements.

Abstract: A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit.

Abstract: Provided is a deterministic component model determining apparatus that determines a type of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; a theoretical value calculating section that calculates a theoretical value of a spectrum for each of a plurality of predetermined types of deterministic components, based on the null frequency; a measured value calculating section that calculates a measured value of the spectrum for the deterministic component included in the probability density function, based on the standard deviation and the spectrum; and a model determining section that determines the type of the deterministic component included in the probability density function

Abstract: Disclosed is a method and apparatus for calibrating a time vernier in an automatic test equipment (ATE) system, the method including generating a data signal and a reference signal whose periods differ by a small amount (dt), using precession of the data signal and reference signal to create accurate delay increments, and creating a trigger signal for Bit Error Rate Test (BERT) counting, the trigger signal having a select frequency such than an integer number (N) of triggers are generated with a precession period (TPREC). Upon occurrence of each trigger, a BERT is initiated for measuring data to determine strobe positions with respect to the data signal.

Abstract: A system for testing a fan interface on a motherboard is provided. A fan simulator receives a PWM signal from a fan interface of the motherboard, converts the PWM signal to a TACH signal and outputs the TACH signal to a computer via a fan connector. A difference between the actual rotation speed from the TACH signal and a preset desired rotation speed of the fan simulator is determined and analyzed by comparing the difference with a preset allowable error margin.

Abstract: A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.

Abstract: The present invention relates to a method and apparatus for measuring a frequency or a phase of a measuring signal, wherein the frequency (fg) or the phase (?g) are estimated by approximating the relationship between a collecting clock (c) and a gating clock (g) based on a non-linear step-shaped function. Thereby, the estimation error can be improved with almost negligible complexity increase in signal processing.

Abstract: The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted signal which comprises a test signal sequence with a high auto-correlation characteristic; then, receiving a received signal, and performing a correlation operation on the test signal and the received signal; finally, according to the result of the correlation operation, determining the impedance matching condition of the transmission medium.