Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl

Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.

Abstract: A method for detecting a design-impacting defect in an integrated circuit substrate is disclosed. In one implementation, a controller determines a distribution of intended geometric features in a design window of the integrated circuit substrate based on proximities of a plurality of points of interest in the design window to the intended geometric features. The controller obtains a set of intended contours from the distribution. The controller obtains a set of imaged contours from one or more images of the integrated circuit substrate. The controller compares the set of imaged contours to the set of intended contours to obtain a set of potential design-impacting defects in the intended geometric features. The controller determines a probability that a potential design-impacting defect from the set of potential design-impacting defects is a valid design-impacting defect. The controller takes a corrective action based on the determined probability.

Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

Abstract: A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also include displaying, at a graphical user interface, the one or more violations in a ranked order.

Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.

Abstract: Systems, apparatuses, and methods for reducing the toggle rates on buses are disclosed. A computing system includes a source which provides packets for transmission on a bus. The packet is compressed by a compression engine. The compressed data format of the packet includes locations (bit positions) referred to as holes which do not include valid data. A bus configuration module identifies the locations of the holes and replaces the holes with information from a previous packet transmitted earlier on the bus. The bus configuration module also determines a new transmission bus width for the packet for lowering the bus toggle rate on the bus during transmission.

Abstract: An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.

Abstract: Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. At least one of the global iterations comprises local iterations for a subcircuit of the circuit design. The local iterations suspend when voltage values on nets of the subcircuit are not changed from one local iteration to a next local iteration or one preset condition is met. The propagated voltage values are then analyzed to detect problems in the circuit design.

Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.

Abstract: This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design. Each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification. Each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently. The computing system can generate a graphical presentation of the covergroup. The graphical presentation include nodes, each of which corresponding to the coverpoints or the coverage crosses. The nodes can be arranged in the graphical presentation based on connectivity between the coverpoints and the coverage crosses and clustered in the graphical presentation based on the occurrences of the coverpoints and coverage crosses during the functional verification of the circuit design.

Abstract: A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. The circuit stencil includes layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit. Simulation is performed on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment. A layout of at least a portion of the second integrated circuit corresponding to the circuit segment is generated responsive to performing the simulation.

Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

Abstract: A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes a method of hardware emulation on a computer. The method may include reading in, by the computer, a hardware description language file and a low power intent file and compiling the hardware description language file and the low power intent file into an emulation image. Embodiments may include loading, the emulation image into an emulator, running, the emulation image under a test environment including using a coverage counter specific to low power coverage, created based on the hardware description language file and the low power intent file, using the coverage counters to inform the test environment, generating, by the computer, a report file including a set of low power coverage metrics based on a low power coverage data item, and presenting the report file to a user via a user interface.

Abstract: Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

Abstract: A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Abstract: A method, system, and computer program product for increasing the life of a NAND flash, the method comprising selecting a set of internal control parameters for the NAND flash and optimizing the set of internal control parameters with a genetic algorithm to find an improved set of control parameters.

Abstract: A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

Abstract: An apparatus, method and the like which enables to represent a pipe network transporting a fluid by use of electrical circuit network is provided. The pipe network analysis apparatus includes; processing circuitry configured to receive a pipe network model that represents a pipe network being constituted by one or more piping elements, convert at least one piping element to an element of an electric circuit being configured to represent a non-linear relation between a pressure and a flow rate of the fluid in the piping elements by use of a relation between a voltage and a current, and generate a model representing an electric circuit network expressing the pipe network, by use of the element of the electric circuit; and an output device configured to provide the model analyzable by a specific electric circuit simulator.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. Load instructions having a nonzero offset can be executed in an address generation stage as is conventional. To avoid conflicts between a current load instruction with zero offset and a previous load instruction with nonzero offset, the current instruction can be rescheduled or sent through a separate dedicated load pipe. An alternative technique permits a load instruction with zero offset to be issued one cycle earlier than it would need to be if it had a nonzero offset, thus reducing load latency.

Abstract: The present disclosure relates to a system and method for use with an electronic circuit design. The method may include providing, using at least one processor, an electronic design and modeling the electronic design to obtain a characteristic distribution associated with the electronic design, wherein modeling includes randomly varying one or more parameters associated with the electronic design. The method may further include identifying at least one key parameter from the modeled electronic design and reducing the electronic design only to the at least one key parameter. The method may also include in response to reducing, randomly varying the one or more parameters and re-modeling the reduced electronic design with the randomly varied one or more parameters.

Abstract: Systems, methods, computer-readable media, and apparatuses for identifying and executing one or more interactive condition evaluation tests to generate an output are provided. In some examples, user information may be received by a system and one or more interactive condition evaluation tests may be identified. An instruction may be transmitted to a computing device of a user and executed on the computing device to enable functionality of one or more sensors that may be used in the identified tests. A user interface may be generated including instructions for executing the identified tests. Upon initiating a test, data may be collected from one or more sensors in the computing device. The data collected may be transmitted to the system and may be processed using one or more machine learning datasets to generate an output.

Abstract: Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. Each processor core model is executed in a different corresponding thread and advances a local core time within the sliding time window. The sliding time window advances by updating a start time of the sliding time window based on the local core time of each processor core model. One or more hardware models and a simulation kernel are executed in a separate thread having a simulation time and simulation events. The start time of the sliding time window is updated based further on an event time of a next event of the simulation events scheduled in the separate thread.

Abstract: Systems and methods are disclosed for routing messages to one or more of a plurality of user devices associated with a particular user to whom a particular message is to be provided. The message destination user device(s) may be determined by evaluating the user interactions on each of the plurality of user device. The message destination user device(s) may be selected as the user device(s) that are predicted to have a relatively high level of interaction and/or activity with the user to whom the message is to be provided or is in relative proximity of the user to whom the message is to be provided. When the message destination user device(s) are determined, the message may be transmitted to that/those message destination user device(s) for rendering to the user to whom the message is to be provided.

Abstract: A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.

Abstract: A system and method of electronic component authentication or component classification can reduce the vulnerability of systems (e.g., satellites, weapons, critical infrastructure, aerospace, automotive, medical systems) to counterfeits. Intrinsic deterministically random property data can be obtained from a set of authentic electronic components, processed, and clustered to create a classifier that can distinguish whether an unknown electronic component is authentic or counterfeit.

Abstract: Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.

Abstract: A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated.

Abstract: A method of extracting an Integrated Circuit (IC) current is provided. The method includes generating a transfer function value by using a voltage measured in a node nearest an input terminal of the IC, substituting the generated transfer function value for a reverse fast Fourier transform function, so as to extract the IC voltage, and extracting the IC current from the extracted IC voltage through a simulation in a time domain.

Abstract: A method executable by a computer processor is provided for determining stability of non-linear radio frequency (RF) circuit. The method includes identifying key devices of the RF circuit which open feedback loops when turned off; defining a generalized Bode's return ratio matrix with respect to the key devices over a range of small signal frequencies at a large signal operating point; determining stability margins for gain and phase of the RF circuit based on eigenvalues of the Bode's return ratio matrix; and determining overall stability of RF circuit using the Nyquist locus of a normalized determinant function based on the determinant of the generalized Bode's return ratio matrix.

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netl

Abstract: A system for monitoring electronic circuit configured to monitor circuit parameters of an electronic circuit is provided. The system for monitoring electronic circuit includes an observing point monitoring circuit, a system control circuit, and a signal measuring circuit. The observing point monitoring circuit includes a plurality of sensor circuits arranged in an array. The sensor circuits respectively sense the circuit parameters of a plurality of observing points in the electronic circuit. The system control circuit selects at least one of the sensor circuits to sense the circuit parameters. One of the selected sensor circuits outputs a sensing signal. The signal measuring circuit receives the sensing signal and analyzes an electrical characteristic of the sensing signal to obtain a monitoring result of the circuit parameters. A method for monitoring electronic circuit is also provided.

Abstract: A calculating device including; a controller configured to execute, for a multicore processor, a first calculation process of calculating a first performance value of a first code executed by the first core and including a first access instruction by executing a first simulation, a second calculation process of calculating a second performance value of a second code executed by the second core and including a second access instruction by executing a second simulation, a synchronization process of synchronizing the first and the second simulations when the first access instruction is executed in the first simulation, and a correction process of correcting the first performance value, by executing a third simulation to simulate an operation of the cache memory when the first core accesses the main memory through the cache memory in accordance with the first access instruction, after the synchronization by the synchronization process.

Abstract: Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.

Abstract: Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) that include one or more image processing components that acquire images generated by an inspection subsystem for a wafer, a main user interface component that provides information generated for the wafer and the reticle to a user and receives instructions from the user, and an interface component that provides an interface between the one or more image processing components and the main user interface. Unlike currently used systems, the one or more image processing components are configured for performing repeater defect detection by applying a repeater defect detection algorithm to the images acquired by the one or more image processing components, and the repeater defect detection algorithm is configured to detect defects on the wafer using a hot threshold and to identify the defects that are repeater defects.

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

Abstract: In one example, a method for evaluating a system includes constructing a macro-model of the system comprising a multiple-order polynomial equation that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the macro-model.

Abstract: An envelope behavioral model is developed and used in a system and method that simulates and predicts outputs of a non-linear component. An analyzer generates a test signal which is provided as input to the non-linear component. Model kernels representative of static and dynamic parts of the model are extracted from an output of the non-linear component responsive to the test signal. The dynamic part represents memory effects of the non-linear component. The model kernels are then used by a simulator to predict the output of the non-linear component responsive to signals of a modulation type.

Abstract: A method may include receiving functional model information regarding a set of functional blocks associated with a functional model. The functional model may include a streaming algorithm for exchanging streaming data. The method may include receiving architectural model information regarding physical devices included in a target device from a hardware-software co-design platform. The physical devices may include a software based processing device and a hardware based processing device. The method may include mapping the functional blocks to the physical devices to allow the streaming data to be communicated between the software based processing device and the hardware based processing device. The method may include generating a streaming interface to model communication of the streaming data between the software based processing device and the hardware based processing device.

Abstract: The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

Abstract: A load analysis includes analyzing, based on a finite element method, a load characteristic when a load is inputted to a cylindrical object to be analyzed in an axial direction, and for the analyzing, applying an analysis model in which a disposition direction of mesh cells of the analysis model is inclined with respect to the axial direction.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract: Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.

Abstract: An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.