Abstract: Techniques of safety assurance using fault trees for identifying dormant system failure states are provided. Both operational failure events, as well as diagnostic failure events are included in a fault tree and the operational failure events are then correlated with the diagnostic failure events, which enables an identification of the dormant system failure states. A component fault tree can be used.

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl

Abstract: A first device for playing media synchronously with a second device, includes a hardware clock having an adjustable clock frequency; a software clock configured to derive time in dependence on the hardware clock; a controller configured to: determine a synchronization error between the software clock and a clock of the second device; and adjust the clock frequency of the hardware clock in dependence on the synchronization error; and a media playout device for playing media and configured to be clocked by the hardware clock.

Abstract: Given a sequential resource allocation system (RAS) topology structure, a state space, called an impulse state space, corresponding to the impulse response of a linear time-invariant system (LTS), is computed by small enough configuration of the considered RAS. Given an initial resource configuration of a RAS which corresponds to an input of an LTS, a complete state enumeration can be obtained by defining the convolution of this configuration with the pre-computed impulse state space. One example embodiment reduces central processing unit (CPU) time to process instructions that compute a target state space of a RAS includes constructing an initial RAS and an initial state space, and extending the initial state space iteratively under a target resource configuration.

Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.

Abstract: A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.

Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.

Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.

Abstract: Processing speeds for generating a model can be enhanced. For example, the model can be generated by using regression coefficient values as weights for independent variables in the model. The regression coefficient values can be determined using a coordinate descent method to find a minimum value of a least absolute shrinkage and selection operator cost function. Each iteration of the coordinate descent method can include determining a starting coordinate based on (i) a previous starting coordinate or a previous regression coefficient value from an immediately prior iteration of the coordinate descent method; (ii) a current regression coefficient value associated with a current iteration of the coordinate descent method; and (iii) a refinement factor configured to minimize a result of a univariate algorithm. Each iteration can also include performing a coordinate descent using the starting coordinate to determine a next regression coefficient value for a next iteration of the coordinate descent method.

Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

Abstract: A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit.

Abstract: A physical level-based security system for data security of a security terminal and a method using the system. The security system includes at least one normal terminal corresponding to an external network, a security terminal corresponding to an internal network and storing sensitive data, and an interface device for transmitting input information of a user to any one of the at least one normal terminal and the security terminal, and providing unidirectional transmission service from the at least one normal terminal to the security terminal.

Abstract: A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.

Abstract: A display includes an integrated strain-gauge layer in or on the display for measuring the strain at a plurality of locations on the display. The display is deformable and secured to a display device by a first chassis. A method includes measuring, over a period of time, strain of the display of a first device at the plurality of locations and recording the strain measurements in a memory of the display device. Strain measurements associated with a failure of the display may be identified. The method may include simulating a dynamic system including a model of a second device. The model of the second device includes a model of a second chassis different than the first chassis and a model of the display associated with the failure. Simulating the dynamic system may include simulating deformation of the model of the display based on the identified strain measurements.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: A system includes operational circuit blocks associated with configurable counter circuits. A configurable counter circuit is configured to control event signal when counting expires and includes a mode input configured to receive a setting of a programmable control event asynchronous mode and a programmable control event synchronous mode. Depending on the programmed mode and whether a control event has occurred in a previous synchronization period, the configurable counter circuit processes an associated operation responsive to issuance of a synchronization instruction or to issuance of a subsequent control event.

Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.

Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Abstract: Systems and methods for device compatibility testing and reporting are disclosed. An exemplary method includes outputting, by a testing computer station, instructions for executing a plurality of certification tests on a device under test. The method includes receiving result indications and corresponding certification test identifiers corresponding to each of the plurality of certification tests, and generating, by the testing computer station, compressed test results for each of the plurality of certification tests. The method includes combining at least a portion of the compressed test results into a reduced data report. The method includes sending, by a computer network in communication with the testing computer station and a remote server, the reduced data report to the remote server.

Abstract: An authenticating circuit includes a first and second challenge vector input, a first and second highly variable process-dependent circuit and a logic circuit. The first highly variable process-dependent circuit receives a first vector from the first challenge vector input and generates a first output that is a function of the first vector and at least one process-dependent feature of a component of the first highly variable process-dependent circuit. The second highly variable process-dependent circuit receives a second vector from the second challenge vector input and generates a second output that is a function of the second vector and at least one process-dependent feature of a component of the second highly variable process-dependent circuit. The logic circuit generates a response output that is a function of the first output and the second output. The function operates so that the response output is independent of environmental conditions of the authenticating circuit.

Abstract: A system and method are provided that reduce the amount of time required to perform transient circuit and envelope transient circuit simulations. The total simulation time is partitioned into n simulation segments of equal lengths of time and adjacent simulation segments are overlapped in time by a predetermined overlap time period, Tov. The simulation segments are then simulated in parallel and the simulation results are merged into a final simulation waveform. The predetermined overlap time period Tov is determined using a non-iterative process that can be performed very quickly. Consequently, the overall amount of time that is required to perform the simulation is greatly reduced.

Abstract: A coupled-domains method for generating disturbance matrices used in correcting topography proximity effects (TPE) for integrated circuit (IC) designs that include inhomogeneous substrates. The IC design is modeled and divided into domains (z-direction regions), each domain defined by upper/lower horizontal domain boundaries and optical properties generated by its associated geometry and material composition. Fourier-space representations are utilized to determine discrete electrical and magnetic field components for each domain that are integrated to derive domain transfer matrices, which are then multiplied to produce a total transfer matrix, which is then used to generate the disturbance matrix. The disturbance matrix may then be utilized by a model-based mask correction tool to calculate light intensity values in the photoresist layer. The corrected mask design is then used to generate a physical mask utilized in the subsequent fabrication of an IC device based on the IC design.

Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Abstract: An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against expected events. Based on the comparison detecting at least one of the expected events being absent in the sequence chart, providing the optimal global quantum value as being smaller than the provisional global quantum value. Based on the comparison detecting no difference between the events in the sequence chart and the expected events, providing the optimal global quantum value as being larger than the provisional global quantum value.

Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

Abstract: Systems and methods offer an efficient approach to computing similarity rankings in bipartite graphs. An example system includes at least one processor and memory storing a bipartite graph having a first set and a second set of nodes, with nodes in the first set being connected to nodes in the second set by edges. The memory also stores instructions that, when executed by the at least one processor, cause the system to assign each node in the second set to one of a plurality of categories and, for each of the plurality of categories, generate a subgraph. The subgraph comprises of a subset of nodes in the first set and edges linking the nodes in the subset, where the nodes in the subset are selected based on connection to a node in the second set that is assigned to the category. The system uses the subgraph to respond to queries.

Abstract: The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

Abstract: Technologies are generally provided to integrate hardware accelerators in datacenters. In some examples, a datacenter customer may provide a hardware accelerator configuration to be implemented at a datacenter. The hardware accelerator configuration may include, for example, one or more customer accelerator blocks and one or more accelerator blocks. The datacenter may retrieve the accelerator block(s), integrate the accelerator block(s) with the customer accelerator block(s) to form the hardware accelerator, and then implement the hardware accelerator. In other examples, the datacenter may charge the customer for use of the accelerator block(s), but refrain from providing the accelerator block(s) to the customer.

Abstract: Disclosed is a method for controlling the voltage of an electrical apparatus of a motor vehicle. The method includes the steps of measuring (E2) the voltage at the terminals of the apparatus and measuring (E3) the strength of the output current of the apparatus, calculating (E4) the values of resistance, inductance and capacitance of the equivalent circuit on the basis of the measured current strength and the measured voltage, comparing (E7, E8, E9) the calculated values of resistance, inductance and capacitance with the values of resistance, inductance and capacitance, respectively, stored in a storage area of the electronic control unit, and initiating (E12) an action if the difference between at least one of the calculated values and the corresponding stored value is above a predetermined threshold.

Abstract: When a communication unit of an FPGA receives emulated signals of a design under test that are to be transmitted to another FPGA, the communication unit analyzes each signal to determine whether a signal event has occurred for the signal. The communication unit transmits to the other DUT FPGA a packet indicating for which signals a signal event has occurred. Subsequently, the communication unit transmits a packet for each signal for which an event has occurred.

Abstract: Systems and methods are disclosed for routing messages to one or more of a plurality of user devices associated with a particular user to whom a particular message is to be provided. The message destination user device(s) may be determined by evaluating the user interactions on each of the plurality of user device. The message destination user device(s) may be selected as the user device(s) that are predicted to have a relatively high level of interaction and/or activity with the user to whom the message is to be provided or is in relative proximity of the user to whom the message is to be provided. When the message destination user device(s) are determined, the message may be transmitted to that/those message destination user device(s) for rendering to the user to whom the message is to be provided.

Abstract: According to an exemplary embodiment of the present disclosure, a method of generating a network-on-chip (NoC) in an electronic device includes clustering a plurality of cores based on total communication energy comprising first communication energy between a plurality of voltage-frequency-islands (VFIs) and second communication energy inside the plurality of VFIs.

Abstract: To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance in a way that emulates the bus behavior of a legacy device when executing the legacy application.

Abstract: A system for verifying applications for Real-Time Execution (RTE) devices is provided. The system includes a memory, at least one processor coupled to the memory, and a simulation component executable by the at least one processor. The simulation component may be configured to receive device simulation information for an RTE device, the device simulation information including device configuration information, application information, and targeted performance information, configure a virtual device simulator to simulate performance of the RTE device, run the virtual device simulator to process one or more simulated events, and output simulation results.

Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

Abstract: Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.