Circuit Simulation Patents (Class 703/14)
  • Patent number: 10402523
    Abstract: A system for monitoring electronic circuit configured to monitor circuit parameters of an electronic circuit is provided. The system for monitoring electronic circuit includes an observing point monitoring circuit, a system control circuit, and a signal measuring circuit. The observing point monitoring circuit includes a plurality of sensor circuits arranged in an array. The sensor circuits respectively sense the circuit parameters of a plurality of observing points in the electronic circuit. The system control circuit selects at least one of the sensor circuits to sense the circuit parameters. One of the selected sensor circuits outputs a sensing signal. The signal measuring circuit receives the sensing signal and analyzes an electrical characteristic of the sensing signal to obtain a monitoring result of the circuit parameters. A method for monitoring electronic circuit is also provided.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 3, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Shi-Yu Huang, Hua-Cheng Fu, Hua-Xuan Li
  • Patent number: 10402510
    Abstract: A calculating device including; a controller configured to execute, for a multicore processor, a first calculation process of calculating a first performance value of a first code executed by the first core and including a first access instruction by executing a first simulation, a second calculation process of calculating a second performance value of a second code executed by the second core and including a second access instruction by executing a second simulation, a synchronization process of synchronizing the first and the second simulations when the first access instruction is executed in the first simulation, and a correction process of correcting the first performance value, by executing a third simulation to simulate an operation of the cache memory when the first core accesses the main memory through the cache memory in accordance with the first access instruction, after the synchronization by the synchronization process.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shinya Kuwamura
  • Patent number: 10401406
    Abstract: A method executable by a computer processor is provided for determining stability of non-linear radio frequency (RF) circuit. The method includes identifying key devices of the RF circuit which open feedback loops when turned off; defining a generalized Bode's return ratio matrix with respect to the key devices over a range of small signal frequencies at a large signal operating point; determining stability margins for gain and phase of the RF circuit based on eigenvalues of the Bode's return ratio matrix; and determining overall stability of RF circuit using the Nyquist locus of a normalized determinant function based on the determinant of the generalized Bode's return ratio matrix.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: September 3, 2019
    Assignee: Keysight Technologies, Inc.
    Inventor: Fangyi Rao
  • Patent number: 10401397
    Abstract: A method of extracting an Integrated Circuit (IC) current is provided. The method includes generating a transfer function value by using a voltage measured in a node nearest an input terminal of the IC, substituting the generated transfer function value for a reverse fast Fourier transform function, so as to extract the IC voltage, and extracting the IC current from the extracted IC voltage through a simulation in a time domain.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sang-Ho Lim, Sang-Ho Lee, Chea-Ok Ko, Jong-Wan Shim, Jeong-Nam Cheon
  • Patent number: 10402505
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netl
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • Patent number: 10395000
    Abstract: Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, Richard J. O'Donovan
  • Patent number: 10395358
    Abstract: Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) that include one or more image processing components that acquire images generated by an inspection subsystem for a wafer, a main user interface component that provides information generated for the wafer and the reticle to a user and receives instructions from the user, and an interface component that provides an interface between the one or more image processing components and the main user interface. Unlike currently used systems, the one or more image processing components are configured for performing repeater defect detection by applying a repeater defect detection algorithm to the images acquired by the one or more image processing components, and the repeater defect detection algorithm is configured to detect defects on the wafer using a hot threshold and to identify the defects that are repeater defects.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 27, 2019
    Assignee: KLA-Tencor Corp.
    Inventors: Bjorn Brauer, Eugene Shifrin, Ashok Mathew, Chetana Bhaskar, Lisheng Gao, Santosh Bhattacharyya, Hucheng Lee, Benjamin Murray
  • Patent number: 10387596
    Abstract: In one example, a method for evaluating a system includes constructing a macro-model of the system comprising a multiple-order polynomial equation that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the macro-model.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Emrah Acar, Colin J. Parris
  • Patent number: 10387605
    Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 20, 2019
    Assignee: Synopsys, Inc.
    Inventors: Maher Mneimneh, Scott Cotton, Mohamed Shaker Sarwary, Fahim Rahim, Sudeep Mondal, Paras Mal Jain
  • Patent number: 10387584
    Abstract: A method may include receiving functional model information regarding a set of functional blocks associated with a functional model. The functional model may include a streaming algorithm for exchanging streaming data. The method may include receiving architectural model information regarding physical devices included in a target device from a hardware-software co-design platform. The physical devices may include a software based processing device and a hardware based processing device. The method may include mapping the functional blocks to the physical devices to allow the streaming data to be communicated between the software based processing device and the hardware based processing device. The method may include generating a streaming interface to model communication of the streaming data between the software based processing device and the hardware based processing device.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: August 20, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Katalin Maria Popovici, Rajiv Ghosh-Roy, Senthilkumar Manickavasagam, Wang Chen, Girish Venkataramani, Wei Zang, Abhijeet H. Gadkari, Matthew H. Fornero
  • Patent number: 10387592
    Abstract: An envelope behavioral model is developed and used in a system and method that simulates and predicts outputs of a non-linear component. An analyzer generates a test signal which is provided as input to the non-linear component. Model kernels representative of static and dynamic parts of the model are extracted from an output of the non-linear component responsive to the test signal. The dynamic part represents memory effects of the non-linear component. The model kernels are then used by a simulator to predict the output of the non-linear component responsive to signals of a modulation type.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: August 20, 2019
    Assignee: Keysight Technologies, Inc.
    Inventor: Jan Verspecht
  • Patent number: 10380294
    Abstract: The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Aaron Mitchell Spratt, William Scott Cranston, Rajat Kanti Mitra, Chandrashekar Lakshminarayanan Chetput
  • Patent number: 10378981
    Abstract: A load analysis includes analyzing, based on a finite element method, a load characteristic when a load is inputted to a cylindrical object to be analyzed in an axial direction, and for the analyzing, applying an analysis model in which a disposition direction of mesh cells of the analysis model is inclined with respect to the axial direction.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 13, 2019
    Assignee: SUBARU CORPORATION
    Inventors: Satoshi Ikeda, Mitsumasa Kuwabara
  • Patent number: 10380292
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kenneth Robert Willis, Jing Wang, Hui Qi, Xuegang Zeng, Zhen Mu
  • Patent number: 10372870
    Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 6, 2019
    Assignee: Mentor Graphics Corporation
    Inventor: Sandeep Koranne
  • Patent number: 10372867
    Abstract: Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 6, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Jun Wang, Randy Bishop, Jingyu Xu, Dick Liu, Hu Cai, Jun Lu
  • Patent number: 10372869
    Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
  • Patent number: 10360330
    Abstract: An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 23, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Thu Nguyen
  • Patent number: 10359773
    Abstract: Techniques of safety assurance using fault trees for identifying dormant system failure states are provided. Both operational failure events, as well as diagnostic failure events are included in a fault tree and the operational failure events are then correlated with the diagnostic failure events, which enables an identification of the dormant system failure states. A component fault tree can be used.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 23, 2019
    Assignee: SIEMENS AKTIENGESELSCHAFT
    Inventors: Kai Höfig, Jean-Pascal Schwinn, Marc Zeller
  • Patent number: 10359825
    Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 23, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Iain Singleton, John Alexander Osborne Netterville, Ashish Darbari
  • Patent number: 10353424
    Abstract: A first device for playing media synchronously with a second device, includes a hardware clock having an adjustable clock frequency; a software clock configured to derive time in dependence on the hardware clock; a controller configured to: determine a synchronization error between the software clock and a clock of the second device; and adjust the clock frequency of the hardware clock in dependence on the synchronization error; and a media playout device for playing media and configured to be clocked by the hardware clock.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Martin Woodhead, Arnold Mark Bilstad
  • Patent number: 10352988
    Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ning Lu
  • Patent number: 10346572
    Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Kyle Corbett, Khang K. Dao
  • Patent number: 10346214
    Abstract: Given a sequential resource allocation system (RAS) topology structure, a state space, called an impulse state space, corresponding to the impulse response of a linear time-invariant system (LTS), is computed by small enough configuration of the considered RAS. Given an initial resource configuration of a RAS which corresponds to an input of an LTS, a complete state enumeration can be obtained by defining the convolution of this configuration with the pre-computed impulse state space. One example embodiment reduces central processing unit (CPU) time to process instructions that compute a target state space of a RAS includes constructing an initial RAS and an initial state space, and extending the initial state space iteratively under a target resource configuration.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Macau University of Science and Technology
    Inventors: Zhiwu Li, Oussama Karoui, Naiqi Wu, Mohamed Khalgui
  • Patent number: 10338138
    Abstract: A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 2, 2019
    Inventor: Chinsong Sul
  • Patent number: 10339242
    Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takumi Uezono, Tadanobu Toba, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoshi Nishikawa, Toru Motoya
  • Patent number: 10325058
    Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moo-Kyung Lee, Jaeick Son, Sunghoon Kim
  • Patent number: 10325047
    Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: June 18, 2019
    Assignee: Sage Software, Inc.
    Inventor: Mau-chung Chang
  • Patent number: 10324122
    Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Kurtz, Ronald D. Rose, Sanjay Upreti
  • Patent number: 10303818
    Abstract: Processing speeds for generating a model can be enhanced. For example, the model can be generated by using regression coefficient values as weights for independent variables in the model. The regression coefficient values can be determined using a coordinate descent method to find a minimum value of a least absolute shrinkage and selection operator cost function. Each iteration of the coordinate descent method can include determining a starting coordinate based on (i) a previous starting coordinate or a previous regression coefficient value from an immediately prior iteration of the coordinate descent method; (ii) a current regression coefficient value associated with a current iteration of the coordinate descent method; and (iii) a refinement factor configured to minimize a result of a univariate algorithm. Each iteration can also include performing a coordinate descent using the starting coordinate to determine a next regression coefficient value for a next iteration of the coordinate descent method.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: May 28, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Jun Liu, Ruiwen Zhang, Zheng Zhao
  • Patent number: 10303385
    Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Michael Keilson, Stephen P. Rozum, Ryan A. Linderman, Pradip Kar
  • Patent number: 10296687
    Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
  • Patent number: 10289798
    Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ronalu Augusta Nunes Barcelos, Hudson Dyele Pinheiro de Oliveira, Mirlaine Aparecida Crepalde, Lucas Luz Reckziegel, Glauber Tadeu de Sousa Carmo, Augusto Amaral Mafra, Regina Mara Amaral Fonseca, Guilherme Henrique de Sousa Santos, Valdir Antoniazzi Júnior
  • Patent number: 10289793
    Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Arnold Jean Marie Gustave Ginetti, Steven Roberts Durrill
  • Patent number: 10284690
    Abstract: A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: May 7, 2019
    Assignee: Cavium, LLC
    Inventors: Wilson Parkhurst Snyder, II, Daniel Adam Katz
  • Patent number: 10263956
    Abstract: A physical level-based security system for data security of a security terminal and a method using the system. The security system includes at least one normal terminal corresponding to an external network, a security terminal corresponding to an internal network and storing sensitive data, and an interface device for transmitting input information of a user to any one of the at least one normal terminal and the security terminal, and providing unidirectional transmission service from the at least one normal terminal to the security terminal.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 16, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yunkoo Lee, Donggeon Lee, Minkyu Joo, Sangwoon Yang
  • Patent number: 10262093
    Abstract: A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 16, 2019
    Assignee: Zipalog, Inc.
    Inventors: Felicia James, Michael Krasnicki
  • Patent number: 10248581
    Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 2, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jan M. J. Janssen, Thorsten H. Grötker, Christoph Schumacher, Rainer Leupers
  • Patent number: 10247970
    Abstract: A display includes an integrated strain-gauge layer in or on the display for measuring the strain at a plurality of locations on the display. The display is deformable and secured to a display device by a first chassis. A method includes measuring, over a period of time, strain of the display of a first device at the plurality of locations and recording the strain measurements in a memory of the display device. Strain measurements associated with a failure of the display may be identified. The method may include simulating a dynamic system including a model of a second device. The model of the second device includes a model of a second chassis different than the first chassis and a model of the display associated with the failure. Simulating the dynamic system may include simulating deformation of the model of the display based on the identified strain measurements.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rohit Krishna Koppal, Chandrashekar Gernipalli Subba
  • Patent number: 10241958
    Abstract: A system includes operational circuit blocks associated with configurable counter circuits. A configurable counter circuit is configured to control event signal when counting expires and includes a mode input configured to receive a setting of a programmable control event asynchronous mode and a programmable control event synchronous mode. Depending on the programmed mode and whether a control event has occurred in a previous synchronization period, the configurable counter circuit processes an associated operation responsive to issuance of a synchronization instruction or to issuance of a subsequent control event.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: March 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Avdhesh Chhodavdia, Michael S. Fenton, Sheethal Somesh Nayak
  • Patent number: 10223485
    Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Patent number: 10216870
    Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. S. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
  • Patent number: 10216552
    Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jatin Bhartia, Matthias D. Heizmann, Ajit S. Honnungar, Parminder Singh
  • Patent number: 10216879
    Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan-Yi Chen, Li-Chung Hsu, Ting-Sheng Huang, Ke-Wei Su, Chung-Kai Lin, Min-Chie Jeng
  • Patent number: 10211993
    Abstract: An authenticating circuit includes a first and second challenge vector input, a first and second highly variable process-dependent circuit and a logic circuit. The first highly variable process-dependent circuit receives a first vector from the first challenge vector input and generates a first output that is a function of the first vector and at least one process-dependent feature of a component of the first highly variable process-dependent circuit. The second highly variable process-dependent circuit receives a second vector from the second challenge vector input and generates a second output that is a function of the second vector and at least one process-dependent feature of a component of the second highly variable process-dependent circuit. The logic circuit generates a response output that is a function of the first output and the second output. The function operates so that the response output is independent of environmental conditions of the authenticating circuit.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 19, 2019
    Assignee: Georgia Tech Research Corporation
    Inventors: Sabyasachi Deyati, Abhijit Chatterjee, Barry John Muldrey
  • Patent number: 10210064
    Abstract: Systems and methods for device compatibility testing and reporting are disclosed. An exemplary method includes outputting, by a testing computer station, instructions for executing a plurality of certification tests on a device under test. The method includes receiving result indications and corresponding certification test identifiers corresponding to each of the plurality of certification tests, and generating, by the testing computer station, compressed test results for each of the plurality of certification tests. The method includes combining at least a portion of the compressed test results into a reduced data report. The method includes sending, by a computer network in communication with the testing computer station and a remote server, the reduced data report to the remote server.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: February 19, 2019
    Assignee: Google LLC
    Inventor: Zhonglei Wang
  • Patent number: 10204197
    Abstract: A coupled-domains method for generating disturbance matrices used in correcting topography proximity effects (TPE) for integrated circuit (IC) designs that include inhomogeneous substrates. The IC design is modeled and divided into domains (z-direction regions), each domain defined by upper/lower horizontal domain boundaries and optical properties generated by its associated geometry and material composition. Fourier-space representations are utilized to determine discrete electrical and magnetic field components for each domain that are integrated to derive domain transfer matrices, which are then multiplied to produce a total transfer matrix, which is then used to generate the disturbance matrix. The disturbance matrix may then be utilized by a model-based mask correction tool to calculate light intensity values in the photoresist layer. The corrected mask design is then used to generate a physical mask utilized in the subsequent fabrication of an IC device based on the IC design.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Nikolay B. Voznesenskiy, Ralf Juengling
  • Patent number: 10204196
    Abstract: A system and method are provided that reduce the amount of time required to perform transient circuit and envelope transient circuit simulations. The total simulation time is partitioned into n simulation segments of equal lengths of time and adjacent simulation segments are overlapped in time by a predetermined overlap time period, Tov. The simulation segments are then simulated in parallel and the simulation results are merged into a final simulation waveform. The predetermined overlap time period Tov is determined using a non-iterative process that can be performed very quickly. Consequently, the overall amount of time that is required to perform the simulation is greatly reduced.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: February 12, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Philippe Torregrossa, Arnaud Soury
  • Patent number: 10199077
    Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Axis AB
    Inventor: Henrik Hovmoller
  • Patent number: 10185799
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: January 22, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz