Event-driven Patents (Class 703/16)
  • Patent number: 10762265
    Abstract: Using a high-level language (HLL) callable library for multiple instances of a core includes detecting, using computer hardware, a reference to an HLL library for a core within an HLL application, determining, using the computer hardware, a plurality of instances of the core by detecting function calls within the HLL application correlated to each of the plurality of instances of the core, and generating, using the computer hardware, interface code within the HLL application for each of the plurality of instances of the core using the HLL library. An executable version of the HLL application is generated, using the computer hardware, wherein the interface code for each of the plurality of instances of the core is bound to the respective instance of the core. The function calls can specify different parameterization files corresponding to the plurality of instances of the core.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Zhenman Fang, James L. Hwang, Alfred Huang, Michael Gill, Tom Shui
  • Patent number: 10762083
    Abstract: Techniques for performing a database search using a rewritten and annotated query are disclosed herein. In example embodiments, a profile lexicon is generated from a set of raw user profiles. A click-through lexicon is generated from a raw query log. A machine-learning model is trained for entity prediction using selected data. Query tagger data is generated using the profile lexicon, the click-through lexicon, and the machine-learning model. A raw query is received. The raw query is rewritten as an annotated query based on the generated query tagger data. A search of a database is performed using the annotated query. Results of the search are returned in response to the receiving of the raw query for presentation in a user interface.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 1, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hamed Firooz, Lin Guo
  • Patent number: 10747932
    Abstract: A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10740526
    Abstract: A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: August 11, 2020
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang
  • Patent number: 10733343
    Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 4, 2020
    Assignee: LAMBDA LOGIC LIMITED
    Inventor: Graham Clemow
  • Patent number: 10719644
    Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Amit Sharma, Rohith MS, Prashanth Srinivasa
  • Patent number: 10678974
    Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
  • Patent number: 10657209
    Abstract: Provided are a method of generating a functional coverage model from a hardware description language (HDL) code for a circuit design and performing verification of the circuit design by using the functional coverage model, and a computing system in which the method is performed.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-young Kim
  • Patent number: 10650109
    Abstract: Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 12, 2020
    Assignee: Synopsys, Inc.
    Inventor: William Clark Naylor, Jr.
  • Patent number: 10627444
    Abstract: An integrated circuit having an integrated logic analyzer can include a match circuit including at least one match cell, wherein each match cell is programmable at runtime to detect a signal state from a plurality of signal states for a probed signal. The integrated circuit can include a combine circuit configured to generate a first match signal indicating an occurrence of a first trigger condition based upon the detected signal state of each match cell, a capture and control circuit configured to determining addressing for storing trace data corresponding to the probed signal, and a trace storage memory configured to the store trace data at addresses determined by the capture and control circuit.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Michael E. Peattie, Bradley K. Fross
  • Patent number: 10581852
    Abstract: A system and method for hardware implementations of policy-based secure computing environments for Internet enabled devices. The present invention facilitates a secure computing environment for any Internet enabled device where policy rules can be described as hardware components that allow or deny access to resources on the device. A compiler produces a hardware description language (HDL) of the hardware components based on given policy rules for that component. The system may be partially or completely implemented in hardware to address inherent limitations of a software only solution. The invention provides greater flexibility to the overall system in terms of performance, security, and expressiveness of the policy rules that must be executed.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 3, 2020
    Assignee: Sequitur Labs, Inc.
    Inventors: Daniel Schaffner, Simon Curry, Paul Chenard, Philip Attfield
  • Patent number: 10572617
    Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
  • Patent number: 10534883
    Abstract: A database is constructed based on a batch PBA performed on a plurality of paths of an integrated circuit. A local PBA is performed on a portion of a selected path. A selected optimization move is identified on the portion of the selected path, based on a result of the local PBA that best meets a set of constraints. A path-wide PBA is performed for an updated path that is based on the selected path incorporating the selected optimization move. The selected optimization move is committed in a netlist associated with the integrated circuit.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 14, 2020
    Assignee: Avatar Integrated Systems, Inc.
    Inventors: Geng Bai, Chao-Yung Wang, Ping-San Tzeng
  • Patent number: 10528512
    Abstract: Systems and methods for performing asynchronous input/output (I/O) operations. An example method comprises: initializing a list of sockets that are ready for performing I/O operations; traversing the list of sockets, wherein a traversal operation of the list includes, for each socket referenced by the list: performing I/O operations using the socket, updating a state flag associated with the socket to reflect a state of the socket, updating one or more observed I/O performance statistics of the socket; and responsive to detecting less than a threshold number of I/O operation errors during the traversal operation, updating the list of sockets based on updated endpoint state flags and observed I/O performance statistics.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: January 7, 2020
    Assignee: Parallels International GmbH
    Inventors: Sergey Pachkov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10503395
    Abstract: The inertia system provides a common platform and application-programming interface (API) for applications to extend the input received from various multi-touch hardware devices to simulate real-world behavior of application objects. To move naturally, application objects should exhibit physical characteristics such as elasticity and deceleration. When a user lifts all contacts from an object, the inertia system provides additional manipulation events to the application so that the application can handle the events as if the user was still moving the object with touch. The inertia system generates the events based on a simulation of the behavior of the objects. If the user moves an object into another object, the inertia system simulates the boundary characteristics of the objects. Thus, the inertia system provides more realistic movement for application objects manipulated using multi-touch hardware and the API provides a consistent feel to manipulations across applications.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 10, 2019
    Assignee: MICROSOFT TECHNOLOGY, LLC
    Inventors: Reed L. Townsend, Xiao Tu, Bryan Scott, Todd A. Torset, Kenneth W. Sykes, Samir S. Pradhan, Jennifer A. Teed
  • Patent number: 10489540
    Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
  • Patent number: 10445448
    Abstract: Embodiments of the present disclosure provide a method, a system and a computer readable storage medium for circuit simulation, comprising: partitioning circuit into a subcircuit-1 and a subcircuit-2 which are connected through at least one port; generating equivalent circuit of subcircuit-1 based on port current/port voltage, subcircuit-1 port voltage under port open-circuit condition/subcircuit-1 port current under port short-circuit condition, and impulse-response of subcircuit-1 port voltage to port current/impulse-response of subcircuit-1 port current to port voltage; simulating a simplified circuit comprising the subcircuit-2 and the equivalent circuit. Comparing with prior art, this disclosure reduces circuit scale by equivalence of linear portion of circuit. Thereby computation amount for circuit simulation is reduced and the computation time for circuit simulation is shortened.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 15, 2019
    Inventor: Yu Tian
  • Patent number: 10432177
    Abstract: A circuit device includes an oscillation circuit that generates an oscillation signal by using an resonator, a clocking circuit that generates clocking data which is real-time clock information based on the oscillation signal, a verification data generation circuit that generates verification data for verifying the clocking data based on the oscillation signal, and an interface circuit that outputs the clocking data and the verification data.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: October 1, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Toshiya Usuda
  • Patent number: 10387603
    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 20, 2019
    Assignee: Altera Corporation
    Inventors: Nishanth Sinnadurai, Gordon Raymond Chiu
  • Patent number: 10372860
    Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 6, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Balkrishna R. Rashingkar, Leonardus J. van Bokhoven, Peiqing Zou
  • Patent number: 10360263
    Abstract: Methods, systems, and computer-readable storage media for receiving data representative of the temporal graph, the data representing vertices, edges between vertices, and temporal features, determining a set of earliest-arrival dependencies, each earliest arrival dependency including an earliest feasible edge between vertices from a list of edges of the temporal graph, providing data representative of an edge-scan-dependency graph (ESD-graph) based on the data representative of the temporal graph, and the set of earliest-arrival dependencies, the ESD-graph including vertices representing edges of the temporal graph, and edges representing earliest-arrival dependencies between vertices, providing data representative of a level-assigned ESD-graph including a level assigned to each vertex of the ESD-graph, and determining earliest-arrival times between a source vertex, and each vertex of the temporal graph by executing a parallel edge scan of the level-assigned ESD-graph.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 23, 2019
    Assignee: SAP SE
    Inventors: Peng Ni, Chen Wang
  • Patent number: 10339244
    Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventors: Benjamin Gamsa, Gordon Raymond Chiu
  • Patent number: 10311192
    Abstract: A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 4, 2019
    Assignee: Synopsys, Inc.
    Inventors: Shekaripuram V. Venkatesh, Sanjay Gulati, Vishal Keswani, Manish Goel, Nitin Sharma
  • Patent number: 10303836
    Abstract: An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10248534
    Abstract: In one embodiment of the present invention, a thread is scheduled for execution by a processor, and the thread includes instructions for testing functionality of a feature of the processor. A workload location on the thread is determined. A hook is placed on the determined workload location. The thread is executed by the processor. In response to encountering the hook during the execution of the thread, a workload is selected from a pool, and the pool includes two or more workloads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Purushotam Bheemanna, Niraj K. Pandey
  • Patent number: 10176284
    Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component; obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Yen-Pin Chen, Chung-Hsing Wang
  • Patent number: 10162913
    Abstract: The present invention relates to a simulation method and device. According to the present invention, a simulation method using a plurality of blocks comprises: a dividing step of dividing a simulation into computation operations for performing unique operations on the blocks and communication operations for data exchanges between different blocks; a grouping step of performing a grouping between the interdependent computation and communication operations; and a simulation performing step of performing an operation included in each group using the blocks according to whether or not the level of interdependency between the computation and communication operations is resolved.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Hoon Kim, Joong Baik Kim, Seung Wook Lee
  • Patent number: 10146899
    Abstract: A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Harald Folberth, Sven Nitzsche
  • Patent number: 10061881
    Abstract: A design efficiency is improved by enabling existing design resources to be utilized.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Wen Li, Akio Yamamoto
  • Patent number: 9928324
    Abstract: A system, method, and computer program product for modeling a receiver load in static timing analysis of digital circuits. Embodiments separate total receiver charge into static and dynamic components, and extract both from an improved library model. The receiver load is effectively modeled with a static capacitance and a current source connected in parallel. A method of extracting load model characteristics from a standard timing library is also provided. The improved receiver model reflects the physical phenomena not currently modeled, and enables a more accurate description of circuit behavior while still using a simple approximation of the transistor level circuit. The complete circuit switching response is found through a perturbative approach, combining a linear response using constant capacitance values with a correction having time-dependent charges for modeling physical phenomena such as the back-Miller effect.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 27, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Igor Keller, William Franson Scott
  • Patent number: 9928321
    Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
  • Patent number: 9922156
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 20, 2018
    Assignee: Altera Corporation
    Inventors: Scott James Brissenden, Paul McHardy
  • Patent number: 9868393
    Abstract: Method and system are provided for vehicle accident avoidance carried out with respect to a host vehicle by modeling behavior. The method includes: monitoring a surrounding environment of the host vehicle and detecting other vehicles in a vicinity of the host vehicle by at least one visual sensor. The method further includes: estimating a speed and direction of each of the detected vehicles; calculating one or more projected paths of each of the detected vehicles based on their current estimated speed and direction, the current monitored surrounding environment, and other vehicle projected paths; estimating a probability of intersection of each projected path with the host vehicle; and providing an alert or action to the host vehicle if there is a high probability of intersection.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohamed A. Bahgat, Ossama Emam, Ayman S. Hanafy, Sara A. Noeman
  • Patent number: 9846587
    Abstract: A system includes a host data processing system and a target platform coupled to the host data processing system. The target platform includes an emulation system. The emulation system includes a processor system, an emulation circuit coupled to the processor system through an integrated circuit (IC) interconnect, and a performance monitor coupled to the IC interconnect. The emulation system receives, from the host data processing system, a software emulation model and a data traffic pattern. The emulation system emulates a system architecture by executing the software emulation model within the processor system and implementing the data traffic pattern over the IC interconnect using the emulation circuit. The emulation system provides, to the host data processing system, measurement data collected by the performance monitor during the emulation.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 19, 2017
    Assignee: XILINX, INC.
    Inventors: Paul R. Schumacher, Graham F. Schelle, Patrick Lysaght, Yi-Hua Yang
  • Patent number: 9825779
    Abstract: A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 21, 2017
    Assignee: ARTERIS, Inc.
    Inventors: Xavier van Ruymbeke, Monica Tang, Jonah Probell, Aliaksei Chapyzhenka
  • Patent number: 9823905
    Abstract: Techniques for generating software code for event processing applications are described herein. In one example, a method can include detecting, via a processor, a concept model, wherein the concept model comprises concept data related to an actor, an event, a domain, and a fact. The method can also include detecting, via the processor, a logic model comprising logic data related to event derivation and fact computation, wherein the logic model is not based on an operating environment. The method can also include creating, via the processor, a set of inferences that indicate a relationship between the concept data and the logic data. In addition, the method can include validating, via the processor, an accuracy of the logic model based on validation data, and generating, via the processor, software code based on the concept model and the logic model.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Opher Ezion, Fabiana Fournier, Sarit Arcushin, Jeffrey M. Adkins, Larry Goldberg, Barbara von Halle
  • Patent number: 9767239
    Abstract: System and methods for achieving a timing closure in a design of an integrated circuit in presence of manufacturing variation. The method includes running a timing engine of a statistical timing analysis tool performing at least one optimization to fix at least one violation of at least one timing quantity at an integrated circuit location. The method includes choosing at least one optimization to apply and finding at least one failing timing quantity, where the quantity is failing due to at least one source of variability which the optimization would impact. The optimization is applied to at least one section of the path leading to the failing timing quantity, where the section contributes to the source of variability. Statistical sensitivity information in canonical form guides the optimization by providing a fully parameterized canonical form of the identified timing violations.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
  • Patent number: 9753484
    Abstract: A SAT filter builder and method for building a SAT filter is provided. Hash functions are utilized to map elements of a domain subset to a set of literals which are in turn used to create a set of equations. These equations are conjoined to provide a satisfiability instance. The satisfiability instance is provided to an equation solver and the solution is provided to an array to build the filter. A query tool is also provided which allows the filter built by the SAT filter to test an element for set membership. The query tool utilizes the same hash functions used by the SAT filter builder to map the element to be tested to a set of literals. These literals are used to create an equation. The solution identified by the SAT builder tool is then provided to the equation created by the query tool and set membership is determined by determining whether the equation provided by the query tool is satisfied by the solution provided by the SAT filter builder.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: September 5, 2017
    Inventors: Victor W. Marek, Andrew J. Mayer, Katrina J. Ray, Sean A. Weaver
  • Patent number: 9721058
    Abstract: A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: August 1, 2017
    Assignee: Synopsys, Inc.
    Inventors: Mohamed Shaker Sarwary, Hans-Jorg Peter, Barsneya Chakrabarti, Fahim Rahim, Mohammad Homayoun Movahed-Ezazi
  • Patent number: 9696377
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 4, 2017
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Patent number: 9665678
    Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-we Cho, Dal-hee Lee, Ha-young Kim, Jae-woo Seo, Jin-tae Kim
  • Patent number: 9633151
    Abstract: Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaoyang Sun, Marcus Vinicius da Mata Gomes, Andrea Iabrudi Tavares, Lawrence Loh, Fabiano Peixoto
  • Patent number: 9633147
    Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Stanley John, Sandeep Kumar Goel, Tze-Chiang Huang, Yun-Han Lee
  • Patent number: 9619600
    Abstract: The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 11, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Charles W. Selvidge, Krishnamurthy Suresh, Sanjay Gupta
  • Patent number: 9548103
    Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 17, 2017
    Assignee: Altera Corporation
    Inventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
  • Patent number: 9536038
    Abstract: CAD software examines delays of paths in a design from design engineers and first selects the longest paths. Then all paths that converge with these longest paths are examined for delays, and a fastest converging path is selected for each of the longest paths. The longest paths are again sorted by the fastest converging delay, and paths with slower converging paths are selected to be Functional Critical Paths (FCP's). Functional critical path timing sensors are added to each FCP to test setup time with an added margin delay. When the margined path delays fail to meet setup requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. The CAD software can replicate some of the FCP's and add toggle pattern generators and timing sensors and a margin controller to adjust the margin delay.
    Type: Grant
    Filed: July 4, 2015
    Date of Patent: January 3, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Bradley Quinton, Trent McClements, Andrew Hughes, Sanjiv Taneja
  • Patent number: 9535120
    Abstract: An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 3, 2017
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Jianguo Ren, Chong Dai, Fengguo Gao, Shang-Bin Huang, Wen-hao Hsueh
  • Patent number: 9529950
    Abstract: Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 27, 2016
    Assignee: Altera Corporation
    Inventors: Maryam Sadooghi-Alvandi, Dmitry Nikolai Denisenko, Andrei Mihai Hagiescu Miriste
  • Patent number: 9524365
    Abstract: A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the remaining statistical samples with a computer-operated Monte Carlo circuit simulation tool in decreasing failure probability order, wherein the sample most likely to fail is simulated first. Progressive comparisons of the simulated yield against a yield target eventually verify the yield at a required confidence level, halting the simulation and triggering tangible output of the comparison results. A potential ten-fold decrease in overall yield verification time without loss of accuracy may result.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Wangyang Zhang
  • Patent number: 9483342
    Abstract: A method for supporting failure mode and effects analysis includes storing a meta-model in a computer-readable storage medium. The meta-model includes generic parts of technical systems, generic failure modes, and associations between the generic parts and the generic failure modes. The associations indicate, for each generic part, one or more generic failure modes associated with the generic part. Each generic failure mode identifies a type of failure for a respective generic part. A processor instantiates the generic parts and the generic failure modes to generate part instances and failure mode instances specifying a technical system. The part instances and the failure mode instances are stored, such as in the computer-readable storage medium.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: November 1, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventor: Kai Höfig