Abstract: A method and apparatus for providing a graphical user interface for simulating designs with mixed signals is described. The present invention provides graphical information to a circuit designer as to the solution of the equation(s) that describe or model the design. The graphical information allows the designer to see convergence and convergence rates of the analog circuit simulation. By providing the designer with information related to the convergence of solutions for the modeling equations, the designer is better able to debug the design because he or she can view the timing and situations related to convergence and divergence.

Abstract: In a structure and a designing method of a memory integrated with a logic, a memory macro comprises L memory array blocks 1-1, 1-2, . . . 1-L each including memory cell arrays each with a storage capacity of K bits and sense amplifiers. Memory array power source driver blocks 4-1, 4-2, . . . 4-L each including a circuit for generating a driver power source which drives a sense amplifier are arranged in a corresponding manner to memory array blocks 1-1, 1-2, . . . 1-L. The memory array blocks 1-1, 1-2, . . . 1-L are arranged along a column direction in an adjacent manner to one another and DQ line pairs extending along a column direction are arranged on the memory array blocks 1-1, 1-2, . . . 1-L. Source line blocks 6a-L, 6b-L, 7a, 7b, 8a, 8b are arranged at an end of the memory array blocks in a row direction. According to such a design, short design turnaround for design and shrinkage of occupying area of a memory macro can be realized.

Abstract: A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, each having a selection input, first and second data inputs, and an output. Each of the plurality of logic cells has a first input and an output, the output of each logic cell in the series being respectively electrically coupled to the first input of a next logic cell in the series. The output of a last logic cell in the series is electrically coupled to the first input of a first logic cell in the series to form a ring. The selection input of each multiplexer of the plurality of multiplexers is electrically coupled to the output of one logic cell in the series, with the output of each multiplexer being electrically coupled to the first input of the next logic cell in the series.

Abstract: The objective is to accurately determine the effective value of channel width in accordance with the design value of channel width when the channel width is scaled down, thereby accurately modeling the electrical characteristic of a MOSFET. An error &Dgr;W1 based on the length of the region extending from the field oxide film to the gate oxide film, an error &Dgr;W2 based on the “effect of stress” that occurs when the design value W of channel width is scaled down, and an error &Dgr;W3 based on the “effect of lithography” that occurs when the design value L of channel length is scaled down, are predetermined with respect to various values of W and L, and the effective value We of channel width is determined according to an equation: We=W−&Dgr;W1+&Dgr;W2+&Dgr;W3. The resulting effective value We is used to model the electrical characteristic of the device.

Abstract: Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis.

Abstract: Exceptions allow a circuit designer, working with a circuit synthesis system, to specify certain paths through the circuit to be synthesized as being subject to non-default timing constraints. The additional information provided by the exceptions can allow the synthesis system to produce a more optimal circuit. A tag-based timing analysis tool is presented, which implements exceptions, and can be used in a synthesis system. A circuit is analyzed in “sections,” which comprise a set of “launch” flip flops, non-cyclic combinational circuitry and a set of “capture” flip flops. The tag-based static timing analysis of the present invention is performed in four main steps: preprocessing, pin-labeling, RF timing table propagation and relative constraint analysis. Preprocessing converts the exceptions written by the circuit designer into a certain standard form in which paths through the circuit to be synthesized are expressed in terms of circuit “pins.

Abstract: According to the present invention, an automated method to tailor an ASIC core to meet the needs of an individual system on a chip design is disclosed. The preferred method starts with a technology-independent hardware description language (HDL) representation of the core des i on. This high-level design is subdivided into functions, or blocks. Blocks which cannot be removed without impacting the integrity of the core design an are ta b y ed with “must-keep” indicators. The execution of all application code that will employ the core is simulated on the high-level model. The simulation process accumulates information about what blocks in the model are used by the application code, and which are unused, information about which blocks are unused is combined with information about what blocks are not removable. The high-level core design is then tailored by deleting blocks in the core design that are both unused and removable.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: The present invention provides stimuli generators, methods of analyzing a cell, methods of generating at least one stimuli, and methods of characterizing delay of a cell. One method of analyzing a cell in accordance with the invention includes providing a truth table which includes plural lines defining the logical behavior of a cell, the truth table comprising stimulus for application to the cell and output information generated by the cell responsive to applied stimulus; providing a preselected condition; and selectively extracting at least one stimuli from the truth table responsive to the preselected condition.

Abstract: A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

Abstract: A simulator includes a timing simulation section executing timing simulation for a logic circuit of an electronic component, a time management section extracting logical operation time at an output terminal of the electronic component from a result of the simulation, a transmission line simulation section executing simulation of a transmission line connected to the output terminal from the logical operation time extracted by the time management section, and a simulation result processing section combining the result of the simulation by the timing simulation section and a result of the transmission line simulation by the transmission line simulation section.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

Abstract: A method for the simulation of responses of a nonlinear amplifier provides for measuring characteristics of nonlinearity of amplitude and of amplitude/phase-shift conversion of the amplifier, each measurement being made at an amplitude that is constant in input. The method further includes measuring the characteristics at different frequencies, developing the characteristics in sequences of direct transfer functions, computing frequency correctors for the direct transfer functions, measuring characteristics of distortion of amplitude modulation, each measurement being performed by modulating the input amplitude, computing modulation transfer functions reproducing the distortion amplitudes at output according to the input modulation amplitudes and correcting the direct transfer functions when the input amplitude is modulated in order to simulate the envelope memory effect. There is a direct application of the invention to the field of the simulation of high efficiency microwave amplification.

Abstract: A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.

Abstract: A simulation method of performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit, on the basis of a positional relationship between transistors, well contact interconnections, and sub-contact interconnections of the layout data. Parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of the transistors are evaluated. A simulation apparatus for performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit is also disclosed.

Abstract: An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40).

Abstract: An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information.

Abstract: The present invention is a method of recovering a gate-level netlist from a transistor-level netlist by functionally describing each gate to be recovered using a first transistor model; generating a signature for each gate to be recovered; receiving the transistor-level netlist; selecting a set of connected components from the transistor-level netlist; functionally describing the set of connected components using the first transistor model; generating a signature for the set of connected components; comparing the signature of the set of connected components to the signature of each gate to be recovered; if the signature of the set of connected components matches a signature of a to be recovered then determining if the corresponding functional descriptions match; if a match occurs then functionally describing the set of connected components using a second transistor model; comparing the functional descriptions generated for the set of connected components using the first and second transistor models; identifyi

Abstract: A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.

Abstract: Verification systems which employ automata-theoretic formal verification use a model automaton made from a system process (203) representing the system and a task automaton (205) representing the task and use the model automaton to test (217) whether the language of the system process is contained in the language of the task automaton. An improved technique reduces the computational complexity of the language containment testing by producing a model (216) which represents a system which has been automatically localized with regard to a task. Another technique reduces the computational complexity of stepwise refinement (208). In stepwise refinement, the system automaton is refined a step at a time until it reaches the complexity of a practical implementation. The computational complexity of the stepwise refinement is reduced by a technique which permits language containment to be tested using a set of models made from process-automaton pairs rather than process-process pairs.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.

Abstract: Data in a data base that describe a logic circuit are converted to a simulation model, and simulations are performed based on them. When it is desired to change a part of the circuit while a simulation is in progress, a tentative correction is made by directly changing the simulation model without entering logics to the data base again. Simulation is continued based on the changed simulation model, then, after the action has been confirmed, the contents of the change are reflected on the data base. In this way, a circuit can easily be changed while simulation is in progress.

Abstract: A simulation device comprises an equation generating unit for generating a simultaneous linear equation by application of the implicit integration formula and the Newton iteration method to the description data of an electronic circuit to be simulated, a plurality of block ILU factorization units for performing incomplete LU factorization processing in parallel on each block in a coefficient matrix of the generated simultaneous linear equation, a plurality of fill-in adding units for adding a plurality of fills-in generated by the incomplete LU factorization to a combined portion of coefficient matrices, in parallel, a plurality of line collection ILU factorization units for ILU-factorizing each of several line collections on the combined portion where the fills-in are added, and a convergent solution judging unit for repeating a series of the above processing until convergence of a solution in the simultaneous linear equation generated by the equation generating unit is reached.

Abstract: A verification apparatus which verifies whether or not a finite state machine indicating the operation of a synchronous sequential machine satisfies the property indicating the functional specification repeats the image computation in the M and the computation of a set product by q starting with the state set p when the finite state machine M, the subset q of the state of the M, and the subset p of the q are given; and checks the relation of the state set of the computation process. As a result, it can be determined, starting with a certain state in the p, whether or not a state transition path which eternally does not exceed the q exists.

Abstract: A method and equipment provide an extended logic simulation result which can be effectively displayed on one screen. The method of displaying a logic simulation result designates a display point in one cycle which corresponds to a clock signal and which is used in executing a logic simulation. At each cycle corresponding to the clock signal, the signal data at the display point are fetched and displayed continuously on a display unit. Efficiency of work on the display unit is enhanced by analyzing a result of a performed logic simulation during design and examination of logic circuits.

Abstract: A method is presented for generating functional tests for a microprocessor having several operating modes and features. A test module template file includes a basic set of instructions required to configure the microprocessor to operate in any one of the several operating modes and with any of the several features enabled. A user modifies a copy of the test module template file to form a test module file which provides a desired operating environment and causes the microprocessor to perform a desired activity and to produce a test result. An assembler takes as input the test module file, along with the contents of any library files to be included, and produces both an assembly code list file and a test code file. The assembly code list file is a computer program listing containing assembly language instructions and data.

Abstract: When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

Abstract: Multiple test cycles may be randomly generated for simultaneous execution on a design under test using a simultaneous random cycles test generator. One form of the test generator is hardware description code run on a simulator. The test generator provides multiple random cycle description generators. A random cycle description generator randomly generates a particular test cycle at runtime using constraints provided by the test generator. A random cycle description generator granted access to a serial common cycle initiator may initiate random test cycles through the common cycle initiator. The common cycle initiator may execute the randomly determined test cycle or define and arm a cycle executor of a plurality of cycle executors to execute the randomly determined test cycle. While one random test cycle is executed, another random cycle description generator is selected to initiate another random test cycle on the common cycle initiator.

Abstract: Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

Abstract: The invented method addresses two important issues concerning don't cares in formal system or circuit synthesis verification. First, it is shown how to represent explicit don't cares in linear space in a flattened hierarchy. Many circuits need this information for verification, but the classical calculation can be exponential. Second, three interpretations of verification on incompletely specified circuits are explored and it is shown how the invented method makes it easy to test each interpretation. The invented method involves transforming each cell within an original circuit that implements an incompletely specified function into set of plural cells that implement the upper and lower bound of the interval of the function. The method thus constructs networks for the endpoints of the intervals and, rather than constructing traditional miters, connects the outputs of the interval circuits with the logic appropriate for the property, e.g. equality or consistency, that is to be verified.

Abstract: A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.

Abstract: A method, apparatus and system for simulating the operation of a circuit using a computer-based simulator comprising: (a) distributing at least one signal upon to one or more simulation model subcircuit functions, which use the signal, upon a change in the signal; (b) scheduling one or more subcircuit functions that use the signal for execution according to a priority assigned to each subcircuit function; and (c) providing an output value to the simulator when no subcircuit functions are scheduled, otherwise, executing one or more subcircuit functions with the highest priority and returning to step (a) to repeat the process.

Abstract: A new design methodology which utilizes a module-based architecture is used to implement customized VLSI designs. In accordance with this invention, the module-based architecture comprises a number of Matrix Transistor Logic (MTL) modules. Each MTL module has a control input buffer section, an output stage section, and a matrix array section. The matrix array section implements logic functions using Pass Transistor Logic technology. Three variables, each of which place a different constraint on the MTL modules, are used in an automated design procedure to implement the MTL modules.

Abstract: An LSI design aiding apparatus includes an operating-part net list generation unit for generating an operating-part net list from a net list of a logical circuit, the net list including information relating to a plurality of logical elements in the logical circuit and information relating to connections involving the plurality of logical elements, and the operating-part net list describing an operating part of the logical circuit which is in operation during a predetermined logical operation, so as to perform an estimation of current consumption, synthesis of the logical circuit adapted for low power consumption, and generation of layout data adapted for low power consumption.