Abstract: A significant improvement over current methods for co-simulation of the hardware and software components of embedded digital system designs is provided. The present invention integrates the hardware and software components of a system design into a single unified simulation environment. The unified simulation environment and the various component models of the system design are created in a high level general purpose programming language. This allows inter-component communications and communications with the unified simulation environment to be carried out through the use of function calls, which significantly increases the overall simulation speed. Additionally, the unified simulation environment runs as a single process, which significantly improves debugging capabilities.

Abstract: A technique for observability based coverage of a design under test (DUT) is presented. A conventional simulation signal is augmented to include a “tag value.” In the course of a simulation, assignment statements (for which observability-based coverage is desired) “inject” tag values on their output signals. A tag value contains an identifier uniquely identifying the assignment statement that produced it. A tag value also contains a “tag history.” The tag history contains copies of the tag values for assignment statements earlier in the flow of control or in the flow of data. If a tag propagated through the DUT appears at an observable output, the circuit designer knows that the assignment statements it identifies have satisfied observability based coverage.

Abstract: A system for monitoring and controlling boundary scan chains in real time that does not require the use of test vectors or test executives. The system automatically builds virtual Devices Under Test (DUT's) from user provided Boundary Scan Description Language (BSDL) files and displays them on the computer display. The virtual devices are connected to a port on the computer and the scan button is pressed to invoke a boundary scan. The results are displayed as color coded “pins” on a computer display to indicate if the pin is at a logic high, a logic low, or is toggling. Logic values may be forced on the pin via a point-and-click graphical user interface, again bypassing the need for test vectors. Graphical indicators and controls are provided by the system to help simplify monitoring and controlling of the boundary scan chain.

Abstract: A system and method is provided to accurately model bidirectional wire I/O using hardware description language (HDL). The preferred model and method uses an HDL model that provides two parallel paths between ports of the bidirectional wire I/O. During simulation, the ports are monitored for activity. When an event is detected on either port, the model checks both ports to see if they are different values. If the ports are different values, one of the two parallel paths is enabled and the other disabled. For example, the model enables the path in which the new signal has appeared and thus passes the signal to the other port. The preferred model allows for the use of HDL elements that support full timing annotation. The preferred embodiment also removes the possibility of high impedance transition error that can result from false transitions to a high impedance state.

Abstract: All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT—FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

Abstract: Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data.

Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Abstract: A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.

Abstract: In simulating a physical circuit or system including analog and mixed signal digital-analog components, a computer models the physical circuit or system as a system of simultaneous equations. Conditional equations with associated conditions that can be true or false at different analog solution iterations result in a system of simultaneous equations that can change during the simulation. Rather than reformulating the system of simultaneous equations at each analog solution iteration, the system of simultaneous equations includes slots that are associated with conditional equations as the conditional equations become active. At a given point during the simulation, the conditions associated with the conditional equations are evaluated to determine which conditional equations are active. The values of the active conditional equations are placed in the slots in the system of simultaneous equations. System variables are associated with active conditional equations.

Abstract: Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is to generate property-specific testbenches that are targeted either at proving the correctness of a property or at finding a bug. It is based on performing property-specific analysis on iteratively less abstract models of the design in order to obtain interesting paths in the form of a Witness Graph, which is then targeted during simulation of the entire design. This testbench generation framework will form an integral part of a comprehensive verification system currently being developed.

Abstract: A test pattern sequence is generated (101), then a logic simulation of the operation of an IC under test in the case of applying each test pattern of the test pattern sequence, and a logic signal value sequence occurring in each signal line of the IC under test (102). The logic signal value sequence in each signal line is used to register in a fault list parts (a logic gate, signal line or signal propagation path) in which a fault (a delay fault or an open fault) detectable by a transient power supply current testing using the test pattern sequence is likely to occur (103).

Abstract: A method and system for simulating the execution of a software program on a simulated hardware system. An instrumented software program is divided into program segments delineated by tags and is then analyzed for data describing the program segments. The data is tabulated and indexed in a function data table according to the program segments. Hardware parameters that at least define a portion of the simulated hardware system are tabulated in a hardware configuration file. The software program is executed on a host system, and when a tag is executed, data indexed in the function data table under the program segment corresponding to the executed tag and hardware parameters tabulated in the hardware configuration file are used to calculate an estimated execution time for the program segment corresponding to the executed tag. The estimated execution time for the program segment is added to a running total for the overall execution time of the software program.

Abstract: A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

Abstract: A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.

Abstract: A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.

Abstract: A driver module is provided that generates test patterns with desired tendencies. The driver module provides these test patterns to controlling code for simulation of a hardware model. The test patterns are generated by creating and connecting subgraphs in a Markov chain. The Markov model describes a plurality of states, each having a probability of going to at least one other state. Markov models may be created to determine whether to drive an interface in the hardware model and to determine the command to drive through the interface. Once the driver module creates and connects the subgraphs of the Markov models, the driver module initiates a random walk through the Markov chains and provides the commands to the controlling code.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of controlling the simulation of a digital circuit in such a way that desired functions are annotated for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A method is described for identifying an inaccurate model of a hardware circuit. The method includes the steps of simulating the model of the circuit by applying a plurality of signals, said plurality of signals having at least one abstract data type level to provide a set of expected results, replacing the at least one abstract data type level with two or more levels having different values to thereby provide and expanded set of signals to apply to said model, resimulating the model with said expanded set and comparing the two sets of results and providing an output signal indicating if the model is inaccurate if the results contradict.

Abstract: Methods and apparatus for performing formal verification of a system defined by a set of automata are useful in facilitating computing efficiencies during the verification of an incremental system design. The various embodiments permit computing efficiencies by saving information generated during a verification of the system for use in subsequent verification runs. The saved information includes calculation results pertaining to instances or elements of the system that do not require modification for the next subsequent verification.

Abstract: A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

Abstract: A system that controls devices and integrally simulates the controlled motion of devices. The control and simulation system allows simultaneous development hardware and software in controlled device installations and increase operational ease-of-use and diagnostic capabilities. The control and three dimensional simulation system also allows client computers to remotely control the system and other devices connected to a network.

Abstract: A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a core cell having a bitline and a complementary bitline, and designing a flipped core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a core cell followed by a flipped core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the core cell is coupled with the flipped complementary bitline of the flipped core cell, and the complementary bitline of the core cell is coupled to the flipped bitline of the flipped core cell.

Abstract: One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality of wire densities, wherein each wire density is associated with one region of a plurality of regions of the component, and comparing the plurality of current densities and the plurality of wire densities.

Abstract: A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model comprises a high-level language model. Each member of the set of faults comprises a finite state machine state, a memory address, and a memory data fault. The built-in self-test circuit and the embedded memory behavior model are then simulated. The built-in self-test circuit generates input data and address patterns for the embedded memory behavior model. The embedded memory behavior model outputs memory address and data in response to the input data and address patterns. The input address and data and the memory address and data are compared in the built-in self-test circuit and a fault output is generated if not matching. The fault output and the set of faults are compared to verify the performance of the built-in self-test circuit.

Abstract: A method, system, and data structure for instrumenting a cross-hierarchical simulation event are disclosed herein. The cross-hierarchical simulation event is a function of a first simulation event residing at a first level of simulation model hierarchy and a second simulation event residing at a second level of simulation model hierarchy. In accordance with the present invention, a cross-hierarchical instrumentation entity is defined within the first level of simulation model hierarchy utilizing an instrumentation declaration comment containing data representing a cross-hierarchical instrumentation entity. A first input of said instrumentation entity is connected to the first simulation event and a second input of the instrumentation entity is connected to the second simulation event utilizing an input port mapping comment that declares the cross-hierarchical instrumentation entity to generate a cross-hierarchical simulation event.

Abstract: A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level model is compared with output of a lumped circuit model for each gate and the substrate, and signal contributions from each gate and switching event are determined based on the comparison. The system determines switching event signals for each of the plurality of gates. The signal contributions and the switching event signals are combined, and a combined lumped circuit model is derived based on a combination of lumped circuit models of the plurality of gates. The overall signal is computed based on the combined gate signal contributions and switching event signals, which are configured as an input to the combined lumped circuit model.

Abstract: With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library is expressed as a function of parameters of throughput, a bus width, instruction quantity and memory size. Also, a portion of the operation realized by using software and a portion realized by using hardware are registered. Through operation simulation conducted with each application successively replaced with each of the libraries, the performance of a semiconductor integrated circuit can be evaluated, so as to synthesize an optimal interface.

Abstract: A method is provided of transferring data from a sender process to a plurality of receiver processes in a hardware description language, which uses a language construct which effects synchronised communication between the sender process and the receiver processes.

Abstract: Simulation methods and simulators are presented which operate on a computer under software control. Said computer simulation methods and simulators are specially suited for simulating digital circuits and mixed analog digital circuits. The methods enable efficient simulation, meaning resulting in a fast simulation while still obtaining accurate results. With fast simulation is meant that the simulation can be completed in a short simulation time. Accurate means that the signals obtained or determined by simulation are good approximations of the signals that would be measured when the circuit, which representation is under simulation, is actually running in real world. Indeed the simulation methods and the related simulation apparatus or simulator exploits a representation of a circuit.

Abstract: A method of performing model to hardware correlation that simulates models based upon design criteria and manufactures devices based upon the design criteria. The method evaluates features of the devices during the manufacturing to produce in-line test parametric data, compares the models to the in-line test parametric data to obtain correlation data, and modifies the simulating according to the correlation data.

Abstract: According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.

Abstract: A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a core cell having a bitline and a complementary bitline, and a flipped core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.

Abstract: A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that describe the design elements. The functional design elements are linked with selected ones of the documentation elements in the database. A testbench is simulated with the design module, and the generated results are stored in a database and linked with the functional design elements. By linking the simulation results, documentation, and design elements, the characteristics of the design module are easily ascertained by a designer who is reusing the design module.

Abstract: A method and system are described in a logic simulator machine for overriding a value of a net during execution of a test routine. A model of a logic design to be simulated is built utilizing the logic simulator machine. The logic design includes multiple nets. One of the nets whose actual value may be overridden is selected. A multiplexer is inserted into the model. The multiplexer receives as its inputs the actual value of the selected net, a control bit, and an override value bit. An override value is input into the multiplexer using the override value bit. The multiplexer outputs a current value of the selected net. The current value is thus propagated to other nets. The override value is propagated as the current value of the net instead of the net's actual value throughout execution of the test routine when the multiplexer control bit is set.

Abstract: A computer software tool for aiding in the design of combinatorial logic and sequential state machines comprising, according to the preferred embodiment, an apparatus and methods for representing and displaying a mathematical transform between a binary output variable and a set of binary input variables. The apparatus includes a computer software program which performs a method having the steps of separating input variables of a transform into successive fields, providing field combination maps having cells representative of binary combinations of field variables, assigning field combination maps of successive fields to each preceding field cell, and assigning binary values to field cell chains formed thereby. The computer software program also enables the visual display, on the display of a computer monitor, of the combination maps and the relationship between combination maps of preceding and successive fields.

Abstract: A method and system for visualizing circuit operation. In the method device activity is obtained based on one or more of measured or simulated activity. The device activity is expressed in a representation, and the expressed activity is represented in a visual form. One suitable form of activity is the simulated version of the PICA slow motion movie. The invention may apply to other simulated design data vies as well, such as switch level simulation, current density simulation, and power density simulation.

Abstract: The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero or more signal declarations, zero or more bus declarations and one or more logic expressions. A logic expression, formulated using the declared signals and buses, is used to evaluate whether a specific verification event has occurred. The present invention further comprises a monitor where the signal of the signal declaration of the monitor is an N-Nary signal. Additionally, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver.

Abstract: A method and apparatus are provided for assembling and operating a physical system having a plurality of structural elements and structural interconnections from a remote location. The method includes the step of creating a graphical representation of the physical system at the remote location showing the elements and connections of the system to be assembled. The method further includes the steps of converting the graphical representation into an element list delineating the elements and the interconnections, transferring the element list from the remote location to an element controller and assembling and operating the system by the element controller in accordance with the element list.

Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

Abstract: A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

Abstract: A method and apparatus that utilize time-domain measurements of a nonlinear device produce or extract a behavioral model from embeddings of these measurements. The method of producing a behavioral model comprises applying an input signal to the nonlinear device, sampling the input signal to produce input data, measuring a response of the device to produce output data, creating an embedded data set, fitting a function to the embedded data set, and verifying the fitted function. The apparatus comprises a signal generator that produces an input signal that is applied to the nonlinear device, the device producing an output signal in response. The apparatus further comprises a data acquisition system that samples and digitizes the input and output signals and a signal processing computer that produces an embedded data set from the digitized signals, fits a function to the embedded data set, and verifies the fitted function.

Abstract: A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced.

Abstract: A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.

Abstract: Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e.g., the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.