Abstract: A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion tools. The technique uses sigma-delta modulation technology to allow conversion of analog and mixed signal stimuli into digital representations that can be converted for use in the target tester using existing digital pattern conversion tools.

Abstract: Methods and systems for designing integrated circuits. In one exemplary method, a first plurality of points in a first representation of a circuit are identified, and the first representation is modified to produce a second representation for which a second plurality of points are identified. The first representation is compared to the second representation at the first plurality and second plurality of points to determine whether the first representation is equivalent to the second representation. Other features and embodiments are also described.

Abstract: Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate primary inputs and outputs. When there are one or more unmatched registers between the first netlist and the second netlist, the unmatched registers are pushed to the primary inputs or outputs using retiming. At the primary inputs, a subspace generator is used to generate subspaces. The subspaces are used to identify non-equivalences between the first and second netlists. Other features and embodiments are also described.

Abstract: A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.

Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

Abstract: Integrated circuit models having associated timing and tag information therewith for use with electronic design automation to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.

Abstract: A method for a cache architecture simulation includes obtaining a first sample set for the cache architecture using a non-stationary Gaussian field model, performing a cache architecture simulation using the first sample set to produce a first set of simulation data, and fitting a first multivariate model to the first set of simulation data.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. A different logic cone is derived for each of the multiple failing output signals at output pads.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: The invented method addresses two important issues concerning don't cares in formal system or circuit synthesis verification. First, it is shown how to represent explicit don't cares in linear space in a flattened hierarchy. Many circuits need this information for verification, but the classical calculation can be exponential. Second, three interpretations of verification on incompletely specified circuits are explored and it is shown how the invented method makes it easy to test each interpretation. The invented method involves transforming each cell within an original circuit that implements an incompletely specified function into set of plural cells that implement the upper and lower bound of the interval of the function. The method thus constructs networks for the endpoints of the intervals and, rather than constructing traditional miters, connects the outputs of the interval circuits with the logic appropriate for the property, e.g. equality or consistency, that is to be verified.

Abstract: A plurality of data code files including addresses and data to be written to the addresses are prepared. Next, a simulation model of a memory macro (memory macro model) is set to write mode. Then, an address value and data value are extracted from a verification pattern at a write-in operation in the first clock cycle after the write mode has been set. A necessary data code file is selected from the plurality of data code files based on the extracted search key. Finally, data are written at once to the simulation model of the memory macro according to contents of the selected data code file.

Abstract: Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.

Abstract: The present invention utilizes a file locking emulator between an application program and an operating system. The file locking emulator comprises an application program interface and a file lock supervisor. The file locking emulator receives the file locking requests from the application program and generates file requests and file lock query commands. When the application program interface receives a file request it first checks the files lock status and then either returns an error for incompatible file requests or executes the compatible lock request along with any other compatible operation request such as a read, write or truncate file operation. Only code in the file request emulator needs to be rewritten when an application program is ported to different operating systems sharing incompatible but executable processes. In this manner tested code of the application program does not have to be rewritten.

Abstract: An apparatus and method of generating an application for a control system. A control process is defined by a physical model and a topological model. An application generator utilizes the physical and topological models to generate an application for the control system.

Abstract: A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.

Abstract: A simulation method is provided in which by using a device model of a thin film transistor in which a nonlinear resistance element or a transistor having characteristics different from an intrinsic transistor is connected to the intrinsic transistor without characteristic deterioration due to a hot carrier, and a circuit operation after hot carrier deterioration can be simulated even by a general-purpose circuit simulator. The nonlinear resistance element is connected to a drain electrode of the intrinsic transistor (conventional device model) without hot carrier deterioration, and an increase of nonlinear resistance due to hot carrier injection is simulated by the nonlinear resistance element. As the nonlinear resistance element, a transistor in which a drain and a gate are connected is used. An increase of channel resistance due to hot carrier deterioration is set by setting the channel length, channel width, and threshold value of the transistor to predetermined values.

Abstract: During designing an electronic device, a test method and a peripheral circuit are also designed using logic data for simulating the operation of the electronic device and the characteristics of a test apparatus used for testing an electronic device. By using the designed test method and logic data representing the operation of the designed peripheral circuit, simulation to judge whether or not the electronic device can be tested. According to the results of the simulation, the designs of the electronic device, the test method, and the peripheral circuit are altered. To optimize the designs of the electronic device, the test method, and the peripheral circuit, simulation is repeated.

Abstract: A method of configuring a set of programmable logic devices includes the step of partitioning a programming file into a set of programmable logic device configurations. A set of programmable logic devices are subsequently configured, in parallel, in accordance with the set of programmable logic device configurations.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or cone of logic cells which cause the desired output signal at a selected output signal transition time.

Abstract: A method used with a simulator and a controller, the controller running execution code to provide output signals which, when linked to resources, cause the resources to cycle through requested activities, the simulator receiving controller output signals and, in response thereto, generating motion pictures of resources as the resources cycle through requested activities, the simulator using data structures which model the resources to determine which motion pictures to generate, the method for generating execution code and data structures for use by the controller and the simulator, respectively, and comprising the steps of, for each resource, encapsulating resource information including resource logic in a control assembly (CA), instantiating at least one instance of at least one CA, compiling instantiated CA instance resource logic to generate execution code, gleaning simulation information from the instantiated CA instances and using the gleaned simulation information to generate a simulation data structur

Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation resources to either the emulation function or the application program. Each emulation resource can have three states: unassigned; an emulation state assigned to emulation function; or an application state assigned to the application program. An emulation resource in the unassigned state may be assigned to emulation or application by writing to a predetermined data register. Emulation resources assigned to emulation return to unassigned state upon a test logic reset. Emulation resources assigned to the application return to the unassigned state upon an integrated circuit logic reset.

Abstract: A method of simulating a memory transistor is provided. An Id-Vcg characteristic is obtained by actual measurement in Step s2, and an Id-Vfg characteristic is obtained by actual measurement in Step s4. Based on the obtained Id-Vcg and Id-Vfg characteristics, the value of a capacitance (Cfc) for use in circuit simulation of the memory transistor is determined in Step s5. In Step s14, the circuit simulation is performed using the value of the capacitance (Cfc) determined in Step s5. This allows a simulated value to reliably approach a measured value since the determined capacitance (Cfc) is based on a result of actual measurement of the characteristics of the memory transistor.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system.

Abstract: A method for checking on cyclicity of a set of definitions employs a simple, non-computational definition of constructivity and a symbolic algorithm based on the new, simple to implement, formulation for variables with arbitrary finite types. This is accomplished by extending variable type to include the “undeterminable” value ⊥ (read as “bottom”). This formulation is non-computational and easily extensible to variables with any finite type. The formulation also handles definitions of indexed variables in the same manner. The set of definitions is then checked to determine whether any of the variables assume the value is ⊥.

Abstract: A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, which have an arithmetic and logic function, reads the circuit description and analyzes signal connection topologies between the hierarchies of the circuit description from top to bottom. The method stores the data of the signal connection topologies. The method reads properties of target modules implemented by the circuit components in the circuit description. The method extracts a property part having a signal communicating between the target modules. The method extracts an output operation property, defining output operation of an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target modules. The method compares the output operation properties with the expecting operation properties.

Abstract: Method and apparatus for detecting and analyzing effects of noise in a digital circuit that arises from a coupling of signals produced by switching of a first gate and a second gate in a timed relationship. Where each of a first gate and a second gate can switch within a selected switching time interval, the gate switching effects are combined and the second gate output signal is analyzed with reference to the first gate input signal. Otherwise, the gate switching effects are not combined. When the second gate output signal satisfies at least one of three criteria, this condition is interpreted as indicating that the second gate permits propagation of a noise pulse produced at the first gate.

Abstract: Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state.

Abstract: A system having a high efficiency of operation to determine a design rule and thus requiring lesser time needed in determining the design rule, is provided by automating the process of determining the design rule. The system comprises an automatic L/S pattern generation part automatically generating a L/S pattern defined by a line width and space width, an optical simulation part performing an optical simulation based on the L/S pattern and a finish prediction part in which the dimension (finished size) of a pattern formed on a resist is predicted based on the result of the optical simulation. Also included is a L/S matrix database construction part in which a L/S matrix is made based on the finish prediction result, and also constructs the data used in making the L/S matrix, as a database, and a design rule generation part generating a design rule from the L/S matrix.

Abstract: The present invention provides a formal equivalence verification method and system to determine the compatibility, or nonsimilarity, of two or more circuit designs. The method and system can check the corresponding verification nodes or candidates for cut points while accounting for input vectors including environmental conditions. The method and system may produce an answer for the user to indicate, for example, compatibility or disimilarity.

Abstract: The operating-point differentiated test results are obtained by running a code sequence on the device at a first operating point to generate predicted results and then running the same code sequence on the device at a second operating point defined by changing an electrical parameter of the first operating point to generate actual results. Any differences that might exist between the predicted and actual results are due to the changed operating point of the device.

Abstract: For each predetermined operational unit of a semiconductor device for which a logic simulation model is to be generated, several types of operational descriptions (MRS operating sections, bank selecting operating sections, and the like) having different functions are stored in advance as a group of operational description libraries in a hard disk. Then, specifying information which specifies operational descriptions that will be applied to the logic simulation model are inputted. The specified operational descriptions are then read out of the hard disk. Then a model body section which is the core of the logic simulation model is generated based on the read operational description. Thus, a method, an apparatus and a program for generating a logic simulation model, and a recording medium for recording the program, which can greatly reduce the procedures required for generating and maintaining the logic simulation model, are provided.

Abstract: In one embodiment, the invention is a method. The method includes extracting parameters of a set of domino logic circuits. The method also includes simulating each domino logic circuit of the set of domino logic circuits. Also, the method includes reporting results of the simulation.

Abstract: A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state.

Abstract: A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

Abstract: A method to automate techniques for using delay correlation effects to optimize the design of digital circuits, including a graphical method of data-entry and an optimized calculation scheme. It is used in conjunction with, or is part of, a computer program which performs timing analysis of digital circuits. The method calculates the time difference between two user-input timing paths in a circuit which include delay ranges for each gate in the paths along with correlation factors between any pair of gates. The method checks the user-input to determine an optimal calculation procedure. If none exists, it resorts to a calculation based on a sequential search of many possible timing states.

Abstract: An integrated support tool set that allows a programmer to design an efficient pipelined FPGA.

Abstract: It is intended to provide an effective value impedance simulation method and apparatus in which even when an external circuit is opened or short-circuited, no infinite current or voltage occurs, no instability occurs in a numerical analysis, and the probability that a physical apparatus is broken is low. An instantaneous value/effective value conversion section connects a resistor and an externally controllable current source in parallel, measures an instantaneous value current i that flows through the parallel connection of the resistor and the current source, and converts the measured instantaneous value current i into an effective value current I. Another instantaneous value/effective value conversion section measures an instantaneous value voltage v that is applied to the parallel connection of the resistor and the current source, and converts the measured instantaneous value voltage v into an effective value voltage V.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Abstract: The present invention is a method and apparatus to verify a design which has an input space and a predicate. The input space is decomposed into a plurality of decompositions. The input space includes a plurality of node variables. The plurality of decompositions includes parametric variables. The decompositions are parameterized into vectors of parametric functions to satisfy the predicate.

Abstract: Simulating a logic design comprised of combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements and associating computer code that simulates portions of the logic design with a graphic element that represents the combinatorial logic and with a graphic element that represents the state logic.

Abstract: Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.

Abstract: Providing instrumentation data relating to a logic design element generally includes using a logic design element in a logic design, performing a simulation of the logic design that includes simulating the logic design element, and having the logic design element automatically collect the instrumentation data during the simulation, where the instrumentation data relate to the logic design element. A query may be received to display the instrumentation data relating to the logic design element and the instrumentation data relating to the logic design element may be displayed in response to the query.

Abstract: The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio.

Abstract: A system and method which reduce power consumption of a domino circuit. An initial phase assignment for outputs of the domino circuit is generated. A final phase assignment that reduces power consumption of the domino circuit is determined. The final phase assignment is selected from at least one additional phase assignment. The power consumption of domino circuits can be reduced by utilizing the methods and systems disclosed.

Abstract: The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

Abstract: A modeling method and a simulation method enable a circuit board to undergo modeling without deterioration of simulation precision while describing with no matrix shape. A circuit simulator analyzes power/ground noise of a circuit board with single current change source. A process regards the circuit board as an aggregate of thin doughnut boards of concentric circle shape with the current change source as the center, subsequently, approximating the aggregate of the doughnut boards to be an aggregate of rectangular boards with respective circumferences of the doughnut boards as widths and respective cut-lengths of the same as lengths, then forming respective transmission line models taking respective rectangular boards of the aggregate of the rectangular boards as the transmission line, thus connecting respective transmission line models in series to make it a simulation model of the circuit board.