Timing Patents (Class 703/19)
  • Patent number: 10768211
    Abstract: Systems and methods are provided for compensating for parasitics in current measurements utilizing series current sense resistors. In one or more embodiments, the techniques include connecting a probe to a terminal of a circuit and a waveform measuring device. A waveform measuring device then acquires, through the probe, a voltage waveform. A virtual probe netlist is generated, where the netlist is descriptive of a series resistance and associated parasitics. A virtual probe processor converts, based on the virtual probe netlist, the voltage waveform to a current waveform representative of a current in the circuit.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 8, 2020
    Assignee: Oracle International Corporation
    Inventors: Peter J. Pupalaikis, Lawrence W. Jacobs, Istvan Novak
  • Patent number: 10726189
    Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Norihiro Kamae, Minoru Yamashita, Biju Manuel
  • Patent number: 10642512
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10641822
    Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 5, 2020
    Assignee: ARM Limited
    Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
  • Patent number: 10552560
    Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 4, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Lance S. P. Brooks, Darrell A. Teegarden
  • Patent number: 10534889
    Abstract: A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 14, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: William Pinello, Arthur Nieuwoudt, Mathieu Drut, Beifang Qiu
  • Patent number: 10489282
    Abstract: Examples disclosed herein relate to application testing. The examples may enable identifying a set of tests for testing an application and identifying a set of attributes associated with a particular test of the set of tests. The set of attributes may comprise an average execution duration of the particular test, a last execution time of the particular test, and a last execution status of the particular test. The examples may further enable determining attribute scores associated with individual attributes of the set of attributes and obtaining user-defined weights associated with the individual attributes. The examples may further enable determining a test score associated with the particular test based on the attribute scores and the user-defined weights associated with the individual attributes. The set of tests may be sorted based on the test score associated with the particular test. The sorted set of tests may be executed.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 26, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: David Peer, Clement Arnaud Gaston Claude, Fan Chen, Eyal Fingold
  • Patent number: 10452803
    Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 22, 2019
    Assignee: ARM Limited
    Inventor: Karen Lee Delk
  • Patent number: 10417141
    Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 17, 2019
    Assignee: Arm Limited
    Inventors: Andrea Pellegrini, Kshitij Sudan, Ali Saidi, Wendy Arnott Elsasser
  • Patent number: 10409941
    Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: September 10, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Mayukh Bhattacharya, Chih-Ping Antony Fan, Huiping Huang, Vinay Nulkar, Amelia Huimin Shen
  • Patent number: 10402532
    Abstract: Various techniques implement an electronic design with electrical analyzes with compensation circuit components. A power pin of a power net may be identified in an electronic design. The electronic design may be reduced into a reduced electronic design at least by applying one or more circuit reduction techniques to at least a portion of the electronic design. At least one load device of a plurality of load devices in the reduced electronic design may be transformed into a transformed load device. One or more design closure tasks may be performed on the electronic design using at least the reduced electronic design and the transformed load device.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yujia Li, Xiaohai Wu, An-Chang Deng
  • Patent number: 10394987
    Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
  • Patent number: 10380301
    Abstract: The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed point is reached. The method may also include identifying a non-X node and providing a path of X-diffusion at a property output.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pradeep Goyal, Mudit Sharma
  • Patent number: 10383093
    Abstract: The present document relates to a method for allocating resources for multi-user or multi-station (STA) data transmission in a wireless LAN system, and an apparatus therefor. To this end, an AP generates a frame including a signaling field and a data field, wherein the signaling field includes a first signaling field (SIG A field) comprising common control information for a plurality of STAs and a second signaling field (SIG B field) comprising user specific control information for each of the plurality of STAs, the second signaling field also comprising data transmission resource allocation information for each of the plurality of STAs. The AP transmits the thus generated frame to the plurality of STAs.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 13, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Jeongki Kim, Wookbong Lee, Kiseon Ryu, Jinsoo Choi, Hangyu Cho
  • Patent number: 10366330
    Abstract: A design verification problem includes a design description and a property to be verified. Feature data is identified from the design verification problem and a result is predicted for the design verification problem based on the feature data. A plurality of verification engines is then orchestrated based on the prediction. Supervised machine learning may be used for the result prediction. Feature data and verification results from a plurality of training test cases are used to train a classifier to create a prediction model. The prediction model uses the feature data of the design verification problem to make a result prediction for the design verification model.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 30, 2019
    Assignee: SYNOPSYS, INC.
    Inventor: Jinqing Yu
  • Patent number: 10353789
    Abstract: This application discloses a computing system to identify multiple views of cells in a circuit design for selective utilization during analog fault simulation of the circuit design. The views of the cells can include two or more of macromodel design views, schematic design views, or extracted design views that includes parasitic elements extracted from a physical layout of the circuit design. The computing system can prompt generation of multiple netlists, each netlist generated based on a different combination of the identified views of the cells in the circuit design, or a list of macromodels with pin accurate subcircuit wrappers, parse and organize the cells in each netlist or the list of macromodels, identify one of the cells to inject with a defect, and selectively simulate portions from a plurality of the netlists based, at least in part, on the identified one of the cells to inject with the defect.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 16, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Tina Najibi, Stephen Kenneth Sunter, Mark Hanson
  • Patent number: 10339238
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa
  • Patent number: 10331826
    Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 25, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
  • Patent number: 10318684
    Abstract: Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Zuo Dai, Aiqun Cao
  • Patent number: 10268787
    Abstract: A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Jiun Dai, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10235490
    Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 19, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Mallon, Gilles S. C. Lamant, Kenneth Ferguson, Monika Bijoy
  • Patent number: 10223493
    Abstract: Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the analysis of the entire design. In a critical slack based merging method, a maximal arrival time associated with a circuit node may be compared to the remaining arrival times associated with the circuit node. Arrival times less than the maximal arrival time by an amount greater than a threshold amount may be deemed non-critical arrival times and may be removed from the tag for the circuit node.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventor: Athanasius Spyrou
  • Patent number: 10216864
    Abstract: A computing device may be used to create a model that includes a block. The block may represent a function corresponding to a simulation and capable of operating in a fault operational mode. The computing device may also, or alternatively, associate a fault scenario, corresponding to the model, with the fault operational mode of the block. Additionally, or alternatively, the computing device may simulate the fault scenario based on the block diagram model.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: February 26, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Joel Berg, Krishna Tamminana, Jagadish Gattu
  • Patent number: 10210294
    Abstract: A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 19, 2019
    Assignee: XILINX, INC.
    Inventor: Kyle Corbett
  • Patent number: 10210296
    Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
  • Patent number: 10203995
    Abstract: Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: February 12, 2019
    Assignee: Excalibur IP, LLC
    Inventors: Jay Hobson, Derek Wang
  • Patent number: 10191833
    Abstract: A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 29, 2019
    Assignee: VMWARE, INC.
    Inventors: Bo Chen, Hao Chen
  • Patent number: 10073938
    Abstract: Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Raj K. Gajavelly, Sujeet Kumar, Pradeep K. Nalla
  • Patent number: 10067183
    Abstract: Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Raghu G. Gaurav, Mary P. Kusko, Hari K. Rajeev
  • Patent number: 9965581
    Abstract: A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 8, 2018
    Assignee: XILINX, INC.
    Inventors: Sabyasachi Das, Aaron Ng, Ruibing Lu, Niyati Shah, Zhiyong Wang
  • Patent number: 9940417
    Abstract: Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John S. Bialas, Jr., Siva Pr. Boosa, Stephen P. Glancy, Yelena M. Tsyrkina
  • Patent number: 9928325
    Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hikoyuki Kawata, Masaki Tosaka, Kumiko Teramae
  • Patent number: 9836566
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nitin Srimal
  • Patent number: 9823298
    Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: November 21, 2017
    Assignee: ARM Limited
    Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
  • Patent number: 9817931
    Abstract: Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: November 14, 2017
    Assignee: The MathWorks, Inc.
    Inventors: Yongfeng Gu, Girish Venkataramani, Rama Kokku
  • Patent number: 9805155
    Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chien-Pang Lu, Yu-Tung Chang
  • Patent number: 9673862
    Abstract: A measurement instrument and associated method: receive at a measurement instrument at least one victim signal from a device under test (DUT), the victim signal including crosstalk interference from one or more aggressor signals which are not received by the measurement instrument; extract from the victim signal an ideal data pattern for the received victim signal, where the ideal data pattern does not include intersymbol interference (ISI), a noise component, or crosstalk interference to the victim signal; ascertain from the received victim signal and the ideal data pattern the ISI for the victim signal; produce a difference signal as a difference between: (1) the received victim signal; and (2) a sum of the ideal data pattern and the ISI; and ascertain from the difference signal a sum of the noise component and the crosstalk interference from one or more aggressor signals which are not received by the measurement instrument.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 6, 2017
    Assignee: Keysight Technologies, Inc.
    Inventors: David L. Gines, Steven Draving, Min Jie Chong
  • Patent number: 9645740
    Abstract: Delay commands are injected into sequential input/output (I/O) requests and the effects of the injected delay commands are measured for determining whether a storage system handling the sequential input/output (IO) requests is causing a bottleneck, while the processing of sequential I/O requests is delayed for a time period when injecting the delay command.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Fischer-Toubol, Omer Haklay, Nir Milstein, Ori Shalev
  • Patent number: 9582626
    Abstract: Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 28, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Eddy Pramono, Jijun Chen, Nikolay Rubanov
  • Patent number: 9543859
    Abstract: Systems, methods, and devices for use with active/reactive power control in power conditioning systems. To provide quick active/reactive power control by way of a grid-connected inverter, an estimator estimates the P and Q coefficients based on an instantaneous power from the grid-connected inverter. The estimator receives grid current and voltage and estimates of the P and Q coefficients are used with reference P and Q values to determine whether active or reactive power needs to be injected to the grid. The P coefficient is a DC offset of the instantaneous power of the grid and the Q coefficient is the coefficient of a sine component of the instantaneous power.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: January 10, 2017
    Inventors: Suzan Eren, Majid Pahlevaninezhad, Praveen Jain, Alireza Bakhshai
  • Patent number: 9497019
    Abstract: An Optical Line Termination (OLT) is connected to an Optical Network Unit (ONU) over an Optical Distribution Network (ODN), wherein the OLT transmits multiple time domains to the ONU over the ODN for synchronizing client equipment connected to the ONU with different time domains. The multiple time domains are transported in one or more OMCI messages, and each OMCI message comprises a single Managed Entity.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 15, 2016
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Niclas Nors
  • Patent number: 9436796
    Abstract: A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 6, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Stephen Dixon
  • Patent number: 9418484
    Abstract: A learning system with augmented reality is provided. The learning system includes a cloud server recording an operation history of a learner and providing feedback messages, and a mobile device having an image-capturing module capturing an image of a substantial object. Also, the learning system comprises an object database storing a simulated object corresponding to the substantial object, an identification module identifying the image and generating image information, and a processing module which receives and analyzes the image information, obtains the simulated object from the object database according to analyzing results, and displays the simulated object on a display interface of the mobile device. The learning system allows learner to operate simulated object operation instructions on the display interface or directly operate the substantial object to control a display status of the simulated object, and the operation history of learner is transmitted to the cloud server.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 16, 2016
    Assignee: National Taiwan Normal University
    Inventors: Mei-Hung Chiu, Wei-Tian Tang, Chin-Cheng Chou
  • Patent number: 9400860
    Abstract: Technology is disclosed for designing a prototype including a plurality of programmable chips for modelling a logic design comprising a hierarchy of logic modules. An example method includes: creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design, by flattening the modules that cannot be preserved according to design constraints; partitioning the new hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimizing: inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; and the number of crossings of programmable chips of a critical combinatorial path; and establishing a routing of the signals between programmable chips using the physical resources available.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 26, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Zied Marrakchi, Christophe Alexandre
  • Patent number: 9280614
    Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst
  • Patent number: 9268885
    Abstract: A method can include selecting integrated circuit (IC) device fabrication process source variations; generating relationships between each process source variance and a device metric variance; and calculating at least one IC device metric value from the process source variations and corresponding relationships between each process source variance and a device metric variance.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 23, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: Jing Wang
  • Patent number: 9230050
    Abstract: A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to a raster scan image of the extracted and annotated electrical property values superimposed at their corresponding physical locations onto a physical layout image of the integrated circuit, preferably color-coded to further spotlight potential defects. The visual images are compared to as specified layout design parameters and to as manufactured parameters.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: January 5, 2016
    Assignee: The United States of America, as represented by the Secretary of the Air Force
    Inventor: Mary Y. Lanzerotti
  • Patent number: 9191197
    Abstract: This invention makes the number of cycles required for AES encryption or decryption by hardware smaller than before by reducing the difference among the summation of the signal processing time for each sub-block transformations in each clock cycle period. To do this, an encryption/decryption circuit includes a first AddRoundKey Transformation module, a second AddRoundKey Transformation module, a ShiftRows Transformation module, a SubBytes Transformation module, a MixColumns Transformation module, and a data holding unit, wherein in a cycle of encryption, the first AddRoundKey Transformation module and the second AddRoundKey Transformation module are executed using different Round Keys.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: November 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirohisa Hotta, Akihiko Yushiya
  • Patent number: 9177090
    Abstract: Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 3, 2015
    Assignee: Atoptech, Inc.
    Inventor: Ping-San Tzeng
  • Patent number: 9165105
    Abstract: A method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for said each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for a timing constraint violation during the STA of the IC design according to the lookup table and re-optimizing the identified risky cell(s) is to reduce risk for the timing constraint violation of the IC design.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Kai Hsu, Wen-Hao Chen