Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.

Abstract: A method for clock modeling in a simulation tool is described. An internal time (I) may be defined that governs the simulator tool's clock period. An external time (E) may be defined. The internal time may have a smaller resolution than the external time. A calibration period (C) may be defined for the clock. The calibration period may be smaller than 0.5E and greater than I. The largest inaccuracy of any clock edge may be monitored, and the clock may be calibrated if the largest inaccuracy is greater than (C?1).

Abstract: The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV.

Abstract: A method of forecasting the electrical production of a photovoltaic device comprising photovoltaic modules (1), comprising a first part of estimating the lighting that will be received in the plane of the photovoltaic modules (1) and a second part of estimating the electrical production of the photovoltaic device, characterized in that it comprises the following first step: (E1)—determination of whether a period concerned is sunny or cloudy, and characterized in that it comprises the following second step (E2) of implementing at least one of the following two steps: (E2)—correction of the second part of the method of forecasting the electrical production based on the measurement of the true electrical production of the photovoltaic modules if the period concerned is sunny; and/or correction of the first part of the method of forecasting the electrical production based on the measurement of the true electrical production of the photovoltaic modules if the period concerned is cloudy.

Abstract: To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

Abstract: Local clock modeling for a discrete event simulator is described. A local clock generator provides realistic clock characteristics in terms of clock precision and clock drift and clock mapping utilities provide API for other modules and/or protocols in the discrete event simulator to schedule events on local clocks instead of global clock of the simulator.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.

Abstract: A simulation system is provided. A simulator is configured to execute simulation of a simulation object at a processing speed. A user interface module is configured to generate at least one of a first operation screen for inputting simulation conditions on the simulation executed by the simulator and an output screen for representing a result of the simulation executed by the simulator, and to display the at least one of the first operation screen and the output screen on a display unit. An adjustor is configured to adjust an updating speed of the at least one of the first operation screen and the output screen which are displayed on the display unit by the user interface module to be different from the processing speed.

Abstract: Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: A method and computer product is provided to generate a signal model for use in analyzing a model system including imposing an explicit time assumption for each time instant of the system model. The time assumptions are defined so that any two assumptions contradict each other, thereby separating all inferences into the respective times. A non-monotonic rule is applied to instantiate component models of the model system. Results are defined as not depending on the existence of a previous time instant and, a simplified signal model is generated, wherein the signal model represents the evolution of a value in the model system over time.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: Systems and methods are provided for concurrently emulating multiple channel impairments. The systems and methods may include storing a plurality of channel impairment profiles, where each channel impairment profile corresponds to a respective channel impairment type; receiving a selection of two or more of the plurality of channel profiles; generating a composite impairment profile by combining the selected two or more channel profiles, the composite profile specifying time-variant impairments, the composite profile reflecting a combination of the respective impairment types of the selected channel profiles; and applying the time-variant impairments specified by the composite profile to an input real-time data stream to generate an impaired real-time data stream, where a timing of the application of the time-variant impairments is based at least in part upon timing data from a real-time clock.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: In an embodiment, a technique for identifying a timer in a graphical block diagram environment. According to the technique, one or more variables associated with an executable model in a graphical diagram environment are identified. One or more characteristics associated with the identified one or more variables are identified and the timer is identified based on the one or more characteristics.

Abstract: A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing.

Abstract: A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

Abstract: A method for building a magnetic bead mathematical model includes defining component elements of the model of the magnetic bead, building the model of the magnetic bead, obtaining a characteristic curve of an impedance of a magnetic bead in a standard magnetic bead specification of the magnetic bead, ascertaining parameters of the component elements, simulating the model of the magnetic bead, and comparing the characteristic curve with the characteristic curve in the standard magnetic bead specification, to further optimize the mode of the magnetic bead.

Abstract: An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.

Abstract: A method and system for generating a patient specific anatomical heart model is disclosed. A sequence of volumetric image data, such as computed tomography (CT), echocardiography, or magnetic resonance (MR) image data of a patient's cardiac region is received. A multi-component patient specific 4D geometric model of the heart and aorta estimated from the sequence of volumetric cardiac imaging data. A patient specific 4D computational model based on one or more of personalized geometry, material properties, fluid boundary conditions, and flow velocity measurements in the 4D geometric model is generated. Patient specific material properties of the aortic wall are estimated using the 4D geometrical model and the 4D computational model. Fluid Structure Interaction (FSI) simulations are performed using the 4D computational model and estimated material properties of the aortic wall, and patient specific clinical parameters are extracted based on the FSI simulations.

Abstract: A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max). The aggressor net delay range at least partially overlaps the victim net delay range. Without increasing the value of Vmax (critical path timing), the first circuit victim net delay range is shrunk, thereby minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.

Abstract: A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

Abstract: A method for designing a transformer using three secondary winding phase shift angles and a minimized core cross-sections. The method includes receiving an indication of an acceptable level of total harmonic distortion (THD) for the transformer, identifying a desired number of secondary windings per output phase of the transformer, simulating performance of various models for the transformer various potential phase shift angles, wherein each of the various models includes a set of phase shift angles for the secondary windings of the transformer. The method further includes identifying, based on the simulation, a transformer model that both has no more than three unique phase shift angles in the set and exhibits a primary side THD that is within the acceptable level, identifying an optimized core cross-sections, and reporting the identified transformer model having the three unique phase shift angle and the optimized core cross-sections.

Abstract: In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.

Abstract: A method for evaluating a device during circuit simulation includes receiving a first request including a first input value; and mapping the first input value to a first space in a table. The table is configured to store one or more table entries. A table entry includes an input value and a stored value. The stored value is obtained as a function of the input value from an analytical device model used to characterize the device during circuit simulation.

Abstract: A system and method for obtaining information about an electronic device includes the steps of providing a criterion for a property of the electronic device depending on at least one device parameter, and determining a relationship between variations of the at least one device parameter and variations of the property.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Abstract: A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and second regions of the target device. A circuit design is placed and routed. With a programmed processor, the timing delay of the first timing specification is increased for one or more elements implementing the circuit design in the first region to produce a second timing specification, and a second timing yield of target device is determined from the second timing specification. In response to the second timing yield being larger than a target timing yield, the programmed processor decreases the timing delay of the second timing specification for one or more elements in the second region to compensate for a difference between the second timing yield and the target timing yield to produce a design-specific timing specification.

Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.

Abstract: Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.

Abstract: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop analysis is performed for the laid out circuit so that a voltage drop list is produced based on a result of the voltage drop analysis and timing analysis is performed using the voltage drop list, and, in a later timing verification process, the voltage drop list is updated based on the changing instruction list and the timing analysis is performed using the updated voltage drop list.

Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.

Abstract: A memory modeling method is provided. According to the memory modeling method, a memory model is provided. The memory model includes an array unit, and the array unit includes an array declaration module and a calculation module. A virtual array is defined in a storage device by the array declaration module. The virtual array is configured to simulate a real memory. Further, according to the memory modeling method, an access instruction is received, and an access operation corresponding to the access instruction is performed to the virtual array, wherein the access operation is performed with a transaction level modeling method. Then, an access time or a delay time of the access operation according to the access instruction is estimated by the calculation module.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.

Abstract: Methods, apparatuses, systems, and computer-readable mediums for modeling output delay of a clocked storage element(s) are disclosed. An output delay model is employed that includes variations in the output delays for the clocked storage element over an operating range of the clocked storage element, including during transitions from transparent operation to non-transparent operation, and vice versa. Errors in the model output delay are reduced or avoided as a result. In one embodiment, the model output delay is determined for the clocked storage element as a function of the differential timing between the arrival time of a clock signal and input data to the clocked storage element. The differential timing allows determination of a model output delay from a plurality of model output delays representing a model output delay curve for the clocked storage element. Time borrowing can also be modeled automatically without the need for a second output delay model.

Abstract: Exemplary embodiments report delay incurred in a model. Exemplary embodiments identify an incurred delay that is related to a graphical affordance in the model and generate a visual indicator associated with the graphical affordance in the model. The visual indicator is related to the incurred delay. Exemplary embodiments render the visual indicator with an output device to depict the incurred delay that is related to the graphical affordance in the model.

Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Abstract: Apparatus for presentation of functional coverage, including one or more processors and a memory, wherein the memory stores software instructions including instructions for representing a set of attributes of a design under test as a multi-dimensional cross-product space, comprising events corresponding to combinations of values of the attributes to be tested, the events comprising legal and illegal events, instructions for running at least one test on the design, instructions for identifying, responsively to the at least one test, a first group of the legal events that were covered by the at least one test and a second group of the legal events that remain non-covered after the at least one test, instructions for grouping one or more of the illegal events with at least one of the first and second groups so as to generate a simplified model of the functional coverage of the events in the cross-product space and instructions for presenting the simplified model of the functional coverage on an output device.

Abstract: Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data.