Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: A method and apparatus are provided to model, analyze, and build linear time invariant systems with delays. The method and apparatus model a linear time invariant system as a linear fractional transformation of matrices of a delay free linear time invariant model with a bank of pure delays. The method and apparatus of the present invention can further accommodate input delays and output delays associated with the linear time invariant system with delays.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to: receive design parameters indicative of a plurality of power supply loads to be powered; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: A performance evaluation device includes: a control timing model unit for outputting a timing for inputting a control signal input/output between plural function blocks contained in a simulation model corresponding to a hardware; a control signal transfer period calculation unit for calculating a transfer period of the control signal between the plural function blocks in accordance with the timing for inputting the control signal; a data timing model unit for outputting a timing for inputting a data signal corresponding to the control signal, which is input/output between the plural function blocks; and a data signal transfer period calculation unit for calculating a transfer period of the data signal between the plural function blocks in accordance with the timing for inputting the data signal.

Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.

Abstract: Method, system, and computer readable medium are disclosed for analyzing electrical properties of a circuit. The method may comprise: providing a network model including at least one network parameter, the network parameter being defined over a frequency range; converting the network parameter into an intermediate network parameter having first and second portions; identifying first and second frequencies defining a frequency sub-range; replacing the first portion of the intermediate network parameter with a DC value when a frequency associated with the intermediate network parameter is lower than the first frequency; replacing the first portion of the intermediate network parameter with a transitional value when the frequency associated with the intermediate network parameter is within the frequency sub-range; and converting the intermediate network parameter with the replaced first portion into an updated network parameter.

Abstract: An extension to a simulator (801) that allows the user to specify real numbers, voltages, and currents (808) on ports of an electrical net is presented. The computer using the analog wire functionality routines (805), the routines for determining nets (804), the net manager (803), and the pin manager (802) resolves unspecified values on said electrical nets. The user may specify at least one value on said port and may specify whether said port is driven. The extension includes additional math functions (1901).

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.

Abstract: A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing.

Abstract: A pulse width of a simulated external system clock is set by determining a least common multiple of the frequency of selected internal clock signals relative to the frequency of the external system clock. The pulse width can be further adjusted based on the frequency of simulated external clocks. By setting the pulse width of the simulated external system clock based on the least common multiple value, the time required to complete the simulation can be reduced while ensuring proper operation of the simulated clock signals during the simulation.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: A method of determining the surface topology of a reflector for convergence of a beam incident thereupon.

Abstract: Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.

Abstract: A computer implemented method includes providing information related to wind speed and direction prediction to a wind turbine energy prediction module, providing wind energy production prediction information to a resource allocation engine, and combining the wind energy production prediction information with information about non-renewable energy resources to provide an output identifying energy production resources to use for optimal load servicing.

Abstract: A method and apparatus for determining the propagation delay of a selected net in a circuit design is described. In one exemplary embodiment, a selected net is received, where the selected net includes a plurality of characteristics that represent the physical and/or parasitic parameters of the net. A net is a set of one or more wires that connects a set of circuit junctions between a pair of endpoints of that net. In addition, a simulation is performed on the selected net using the plurality of characteristics. The circuit design system computes the propagation delay for the selected net based on the simulation and makes available the propagation delay of that net. The propagation delay for a net is the delay for a signal traveling between the endpoints of the net.

Abstract: A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp.

Abstract: In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.

Abstract: The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV.

Abstract: A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

Abstract: A method of generating a representation of an electronic circuit across a plurality of design entry tools includes extracting a first partial circuit including a first plurality of first electronic components from a first partition, extracting a second partial circuit including a second plurality of second electronic components from a second partition, generating a simulation block in the first design entry tool including an interface between the first and second partitions, exporting a first netlist representing the interconnection of the first electronic components in the first partial circuit, populating the simulation block in the second design entry tool to include a second netlist representing the interconnection of the second electronic components in the second partial circuit and the interface between the first and second partitions, and exporting the second netlist to stitch the extracted first and second partial circuits using the interface between the first and second partitions.

Abstract: A system and method for measurement of the performance of a network by simulation, wherein time divergence is addressed by using discrete event simulation time to control and synchronize time advance or time slow down on virtual machines for large-scale hybrid network emulation, particularly where the loss of fidelity could otherwise be substantial. A dynamic time control and synchronization mechanism is implemented in a hypervisor clock control module on each test bed machine, which enables tight control of virtual machine time using time information from the simulation. A simulator state introspection and control module, running alongside the simulator, enables extraction of time information from the simulation and control of simulation time, which is supplied to the virtual machines. This is accomplished with a small footprint and low overhead.

Abstract: Accurate circuit and system timing analysis is a critical tool for designing and analyzing complex modern semiconductor chips. While the accuracy and detail of dynamic electrical simulation may be desirable in theory, such analysis is not feasible due to extreme computational complexity and open-ended simulation times. Improved circuit modeling and timing analysis tools that can provide both accuracy and computational efficiency are required. Table look-up (TLU) and other techniques provide computationally efficient timing analysis but may be undertaken at the expense of simulation accuracy. Instead, the use of current waveform moments representing the frequency domain equivalents of signals can provide the required simulation accuracy and computational efficiency.

Abstract: A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance

Abstract: A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.

Abstract: Disclosed in this specification is a method for identifying at least one aptamer that can bind to a bio-molecular target. The aptamer is designed in silico based on the structure of the target molecule. The process includes the steps of determining a first seed residue and growing an oligomer, one residue at a time, while maximizing the entropy of target-oligomer complex or minimizing the binding energy after the addition of each oligomer.

Abstract: A method and tools for providing precise timing analysis scalable to industrial case studies with large numbers of tasks and messages are provided, including the capability to model and analyze task and message response times; ECU usage; bus usage; end-to-end latency of task/message chains; and timing synchronization problems in task/message graphs. System tasks and messages are modeled in a formalism known as calendar automaton. Models are written in a modeling language such as Promela and instrumented with code specific to the analysis specification. Models and instrumentation are automatically generated from the system description and analysis specification. The system model is subjected to exhaustive state space exploration by a compatible model checker, such as SPIN. During exploration, the instrumented code produces results for different timing analyses.

Abstract: Methods and systems are provided for modeling a multiprocessor system in a graphical modeling environment. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements. Code may be generated to simulate each node and communication channel in the modeled multiprocessor system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: A computer implemented method for modelizing a nuclear reactor core, includes the steps of: partitioning the core in cubes to constitute nodes of a grid for computer implemented calculation, calculating neutron flux by using an iterative solving procedure of at least one eigensystem, the components of an iterant of the eigensystem corresponding either to a neutron flux, to a neutron outcurrent or to a neutron incurrent, for a respective cube to be calculated. The eigensystem iterative solving procedure includes a substep of conditioning the eigensystem into a spare eigensystem wherein the components of an iterant of the spare eigensystem correspond only either to neutron incurrents coming into the cubes or to neutron outcurrents coming from the cubes.

Abstract: A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: A traffic generator is disclosed which generates a first type of traffic in accordance with a given distribution, and generates a second type of traffic that includes at least one traffic burst. The traffic burst is generated based at least in part on an amount of the first type of traffic generated over one or more time intervals. For example, in an illustrative embodiment, generation of the second type of traffic involves accumulating traffic over one or more of the time intervals for which the first type of traffic is generated, and generating the traffic burst based at least in part on the accumulated traffic.

Abstract: A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent ins

Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

Abstract: Methods, systems, and machine-readable storage medium for logic synthesis that adjust a timing model of a circuit are provided. A first memory element from multiple memory elements of the circuit may be determined, where the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal. A combinational element within the first portion of the circuit may be determined. The combinational element may include at least one input or output coupled with a second memory element. The second memory element may be controlled by at least one second control signal. The second control signal may be incompatible with the first control signal. A first timing element may be inserted into the circuit at a location connecting the first timing element with the combinational element. A synthesis optimization may be performed utilizing the at least one first timing element.

Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.

Abstract: Embodiments of the present invention provide a method, system and computer program product for duration estimation of simulating a process model embodied in a directed graph. In an embodiment of the invention, a method for estimating a duration of simulation for a process model embodied in a directed graph can include loading a directed graph for traversal in a simulation engine, identifying nodes in the directed graph, estimating a duration of simulation by the simulation engine for individual ones of the nodes, summing a duration of simulation for the individual ones of the nodes to produce an estimate of a duration of traversal of the directed graph, and presenting the estimate in association with the traversal of the directed graph by the simulation engine.

Abstract: A method for clock modeling in a simulation tool is described. An internal time (I) may be defined that governs the simulator tool's clock period. An external time (E) may be defined. The internal time may have a smaller resolution than the external time. A calibration period (C) may be defined for the clock. The calibration period may be smaller than 0.5E and greater than I. The largest inaccuracy of any clock edge may be monitored, and the clock may be calibrated if the largest inaccuracy is greater than (C?1).

Abstract: The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV.

Abstract: A method of forecasting the electrical production of a photovoltaic device comprising photovoltaic modules (1), comprising a first part of estimating the lighting that will be received in the plane of the photovoltaic modules (1) and a second part of estimating the electrical production of the photovoltaic device, characterized in that it comprises the following first step: (E1)—determination of whether a period concerned is sunny or cloudy, and characterized in that it comprises the following second step (E2) of implementing at least one of the following two steps: (E2)—correction of the second part of the method of forecasting the electrical production based on the measurement of the true electrical production of the photovoltaic modules if the period concerned is sunny; and/or correction of the first part of the method of forecasting the electrical production based on the measurement of the true electrical production of the photovoltaic modules if the period concerned is cloudy.

Abstract: To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

Abstract: Local clock modeling for a discrete event simulator is described. A local clock generator provides realistic clock characteristics in terms of clock precision and clock drift and clock mapping utilities provide API for other modules and/or protocols in the discrete event simulator to schedule events on local clocks instead of global clock of the simulator.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

Abstract: A complex two-dimensional layout of a photomask or other three-dimensional object is systematically decomposed into a finite number of elementary two-dimensional objects with the ability to cause one-dimensional changes in light transmission properties. An algorithmic implementation of this can take the form of creation of a look-up table that stores all the scattering information of all two-dimensional objects needed for the synthesis of the electromagnetic scattered field from the original three-dimensional object. The domain is decomposed into edges, where pre-calculated electromagnetic field from the diffraction of isolated edges is recycled in the synthesis of the near diffracted field from arbitrary two-dimensional diffracting geometries. The invention has particular applicability in die-to-database inspection where an actual image of a mask is compared with a synthesized image that takes imaging artifacts of comers, edges and proximity into account.