Abstract: Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the analysis of the entire design. In a critical slack based merging method, a maximal arrival time associated with a circuit node may be compared to the remaining arrival times associated with the circuit node. Arrival times less than the maximal arrival time by an amount greater than a threshold amount may be deemed non-critical arrival times and may be removed from the tag for the circuit node.

Abstract: A computing device may be used to create a model that includes a block. The block may represent a function corresponding to a simulation and capable of operating in a fault operational mode. The computing device may also, or alternatively, associate a fault scenario, corresponding to the model, with the fault operational mode of the block. Additionally, or alternatively, the computing device may simulate the fault scenario based on the block diagram model.

Abstract: A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example.

Abstract: A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.

Abstract: Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.

Abstract: Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.

Abstract: A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.

Abstract: Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected.

Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.

Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.

Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Abstract: Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.

Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.

Abstract: A measurement instrument and associated method: receive at a measurement instrument at least one victim signal from a device under test (DUT), the victim signal including crosstalk interference from one or more aggressor signals which are not received by the measurement instrument; extract from the victim signal an ideal data pattern for the received victim signal, where the ideal data pattern does not include intersymbol interference (ISI), a noise component, or crosstalk interference to the victim signal; ascertain from the received victim signal and the ideal data pattern the ISI for the victim signal; produce a difference signal as a difference between: (1) the received victim signal; and (2) a sum of the ideal data pattern and the ISI; and ascertain from the difference signal a sum of the noise component and the crosstalk interference from one or more aggressor signals which are not received by the measurement instrument.

Abstract: Delay commands are injected into sequential input/output (I/O) requests and the effects of the injected delay commands are measured for determining whether a storage system handling the sequential input/output (IO) requests is causing a bottleneck, while the processing of sequential I/O requests is delayed for a time period when injecting the delay command.

Abstract: Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.

Abstract: Systems, methods, and devices for use with active/reactive power control in power conditioning systems. To provide quick active/reactive power control by way of a grid-connected inverter, an estimator estimates the P and Q coefficients based on an instantaneous power from the grid-connected inverter. The estimator receives grid current and voltage and estimates of the P and Q coefficients are used with reference P and Q values to determine whether active or reactive power needs to be injected to the grid. The P coefficient is a DC offset of the instantaneous power of the grid and the Q coefficient is the coefficient of a sine component of the instantaneous power.

Abstract: An Optical Line Termination (OLT) is connected to an Optical Network Unit (ONU) over an Optical Distribution Network (ODN), wherein the OLT transmits multiple time domains to the ONU over the ODN for synchronizing client equipment connected to the ONU with different time domains. The multiple time domains are transported in one or more OMCI messages, and each OMCI message comprises a single Managed Entity.

Abstract: A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.

Abstract: A learning system with augmented reality is provided. The learning system includes a cloud server recording an operation history of a learner and providing feedback messages, and a mobile device having an image-capturing module capturing an image of a substantial object. Also, the learning system comprises an object database storing a simulated object corresponding to the substantial object, an identification module identifying the image and generating image information, and a processing module which receives and analyzes the image information, obtains the simulated object from the object database according to analyzing results, and displays the simulated object on a display interface of the mobile device. The learning system allows learner to operate simulated object operation instructions on the display interface or directly operate the substantial object to control a display status of the simulated object, and the operation history of learner is transmitted to the cloud server.

Abstract: Technology is disclosed for designing a prototype including a plurality of programmable chips for modelling a logic design comprising a hierarchy of logic modules. An example method includes: creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design, by flattening the modules that cannot be preserved according to design constraints; partitioning the new hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimizing: inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; and the number of crossings of programmable chips of a critical combinatorial path; and establishing a routing of the signals between programmable chips using the physical resources available.

Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

Abstract: A method can include selecting integrated circuit (IC) device fabrication process source variations; generating relationships between each process source variance and a device metric variance; and calculating at least one IC device metric value from the process source variations and corresponding relationships between each process source variance and a device metric variance.

Abstract: A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to a raster scan image of the extracted and annotated electrical property values superimposed at their corresponding physical locations onto a physical layout image of the integrated circuit, preferably color-coded to further spotlight potential defects. The visual images are compared to as specified layout design parameters and to as manufactured parameters.

Abstract: This invention makes the number of cycles required for AES encryption or decryption by hardware smaller than before by reducing the difference among the summation of the signal processing time for each sub-block transformations in each clock cycle period. To do this, an encryption/decryption circuit includes a first AddRoundKey Transformation module, a second AddRoundKey Transformation module, a ShiftRows Transformation module, a SubBytes Transformation module, a MixColumns Transformation module, and a data holding unit, wherein in a cycle of encryption, the first AddRoundKey Transformation module and the second AddRoundKey Transformation module are executed using different Round Keys.

Abstract: Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.

Abstract: A method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for said each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for a timing constraint violation during the STA of the IC design according to the lookup table and re-optimizing the identified risky cell(s) is to reduce risk for the timing constraint violation of the IC design.

Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.

Abstract: Methods and numerical tools for designing and optimizing LED systems are provided to achieve a desired luminous performance and to increase reliability and operating lifetime. In addition, methods for designing LED illumination systems are also disclosed to determine an optimum operating power for a desired output luminous flux, given the condition of the rated power of the LED and the heatsink. By the invention, LED illumination systems can be designed with a suitable choice of LED and/or heatsink.

Abstract: A method includes extracting multiple-patterning group assignment information of one or more layout patterns from a layout design. The layout design corresponds to a circuit design, and the one or more layout patterns corresponding to a node of the circuit design. Whether the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node is determined by a hardware processor.

Abstract: A position detection and simulation platform includes software configurable logic and programmable inputs and outputs to support software configuration only changes for use with a variety of position feedback devices including synchros, resolvers, linear variable differential transformers, and rotary variable differential transformers. Power to the software configurable outputs is dynamically controlled so that the power supply voltage presented to the outputs satisfies a minimum threshold above the amplitude of the output signal. Dynamic control is based on at least one of a digital representation of a signal to be output, an analog version of the signal to be output, or the signal being output.

Abstract: The application relates to a method for determining the cut quality of a laser cutting process, said quality being assessed on the basis of the formation of solidification ridges along the cut face and/or burr formation on the lower edge of the cut face. In said method, a virtual laser cutting machine in a simulation program can be virtually operated with a set of values P0 from a parameter space P.

Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.

Abstract: A laser device, having an optical cavity containing a gain medium, a total reflectance reflector positioned within the optical cavity, and a partial reflectance reflector positioned within the optical cavity in a juxtaposed relationship to the total reflectance reflector. The topology of the reflectors are defined by a convergent reflector topology function that converges light emitted within the optical cavity to a laser beam that exits the optical cavity through the partial reflectance reflector by a series of reflections between the total reflectance reflector and the partial reflectance reflector. The laser beam emitted from the optical cavity has a predefined pattern for a given convergent reflector topology.

Abstract: Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation.

Abstract: A circuit simulation apparatus acquires wiring connection information indicating connection data in an electric circuit, selects a component constituting the circuit based on the wiring connection information, performs a setting of replacing the selected component with each resistor having different resistance values, generates at least one of netlists using the acquired wiring connection information and at least one of the set resistance values, calculates a value of an equivalent power source and a value of an internal resistance thereof for a part of the circuit using the acquired wiring connection information and at least one of the generated netlists, and calculates a resistance value of the selected component and a power consumption for the resistance value using the value of the equivalent power source and the value of the internal resistance.

Abstract: Systems and methods for event simulation with energy analysis. A method includes receiving a plurality of environment objects, and receiving energy attributes corresponding to one or more of the environment objects. The method includes simulating the operation of the environment objects and, during the simulation, calculating values for the energy attributes reflecting the energy use for the respective energy attributes. The method includes displaying the calculated values for the energy attributes.

Abstract: Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation.

Abstract: In connection with a machining program used in machining a workpiece by means of a machine tool controlled by a numerical controller, interpolation data, a command position point sequence, and a servo position point sequence for each processing period are determined by simulation by designating speed data for giving a machining speed and precision data for giving a machining precision. A predicted machining time for workpiece machining is determined based on the determined interpolation data, and a predicted machining error for workpiece machining is determined based on the determined command and servo position point sequences. Further, the precision data and the speed data are determined for the shortest predicted machining time within a preset machining error tolerance, based on a plurality of predicted machining times and a plurality of predicted machining errors.

Abstract: A computing device may be used to create a model that includes a block. The block may represent a function corresponding to a simulation. Measurement points may be inserted into the model. The model may be used to create a simulation, and the measurement points may be used to measure operational characteristics corresponding to the block.

Abstract: A method for designing a system on a target device includes performing timing analysis at an intermediate node on a data path from a source to a destination to determine whether rise and fall skew of components on the data path could result in data not being sampled at the destination.

Abstract: Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation.

Abstract: A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.

Abstract: A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.

Abstract: Methods, apparatuses, systems, and computer-readable mediums for modeling output delay of a clocked storage element(s) are disclosed. An output delay model is employed that includes variations in the output delays for the clocked storage element over an operating range of the clocked storage element, including during transitions from transparent operation to non-transparent operation, and vice versa. Errors in the model output delay are reduced or avoided as a result. In one embodiment, the model output delay is determined for the clocked storage element as a function of the differential timing between the arrival time of a clock signal and input data to the clocked storage element. The differential timing allows determination of a model output delay from a plurality of model output delays representing a model output delay curve for the clocked storage element. Time borrowing can also be modeled automatically without the need for a second output delay model.

Abstract: In an embodiment, a technique for identifying a timer in a graphical block diagram environment. According to the technique, one or more variables associated with an executable model in a graphical diagram environment are identified. One or more characteristics associated with the identified one or more variables are identified and the timer is identified based on the one or more characteristics.

Abstract: The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV.