Abstract: A method and system for particle simulation are provided in which the number of particles is held as close as possible below a prescribed particle limit. When adding new particles to the simulation results in approaches the particle limit, new particles which contribute most to the visual quality of the simulation are added first, followed by deleting or merging existing particles which contribute least before adding the remaining new particles. Visual quality is also optimized by splitting particles into two or more new particles until the target particle count is reached. The criteria for performing insertions, deletions, splitting, or merging are governed by the results of predefined fitness functions by which the visual effect of each operation is estimated.

Abstract: A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: A mechanism for evaluating hybrid expressions which allows access to more than one modeling domain is discussed. The present invention allows an evaluation of a portion of a hybrid expression in a first modeling domain. Following the evaluation of the portion of the hybrid expression specific to the first modeling domain, at least a portion of the remainder of the hybrid expression is provided to a second modeling domain for further evaluation.

Abstract: Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the model. The delay of each component of the model may be determined based on intrinsic information of the component. If the intrinsic information of the component does not provide information on the delay of the component, the component may be simulated to determine the delay of the components. The model may be automatically compensated for the delay. The delay is reported prior to the execution of the model, and compensated for without executing the model.

Abstract: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Abstract: Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.

Abstract: The present invention comprises apparatus and systems for measuring, monitoring, tracking and simulating enterprise communications and processes. A central message repository or database is constructed, comprised of monitoring messages sent from process messaging systems. The database may then be accessed or queried as desired. A simulation tool assists in reviewing present and proposed processes and sub-processes before modifying existent systems or creating new systems.

Abstract: Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.

Abstract: A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency may occur when a substrate current in a high voltage device is calculated, for example using BSIM3-based modeling. According to embodiments, a substrate current for a third region may be modeled by an expression with a ternary operator, and the modeled substrate current may be added to a substrate current obtained through BSIM3-based modeling.

Abstract: An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least one path comprising logical user defined delay segments and a timing point may be associated with both a common point and no delay. An original clock signal may propagate along the logical path without incurring delay until arriving back at the common point, along with the original signal. All other clocks may be ignored or prevented from propagating long the path. Multiple replicated copies may be accomplished without requiring additional hardware.

Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Abstract: A simulation apparatus according to an embodiment performs an electromagnetic field circuit coupling analysis on a first substrate and a second substrate electrically coupled via a circuit element having a finite delay time. A first coupling analysis unit carries out a time domain electromagnetic field analysis and also a circuit analysis on a circuit element at a first analytical domain including the first substrate. The second coupling analysis unit carries out a time domain electromagnetic field analysis and also a circuit analysis on a circuit element at a second analytical domain including the second substrate.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Abstract: A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: A system that enables controlling motion over a network comprises an interface that receives motion control data that includes a time stamp from the network. Additionally, the system includes a motion control component that utilizes the received motion control data to update properties associated with the motion control component based at least in part on the time stamp. The system can also include a clock that is synchronized with disparate clocks associated with disparate motion control components located on the network.

Abstract: A method for determining a worst-case transition is disclosed. The method includes determining a plurality of output slews for the plurality of input signals based on a timing model of a gate and selecting a worst delay input signal from the plurality of input signals based on the output slews.

Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.

Abstract: A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation identifier configured to identify at least some timing violations in a circuit based on a timing analysis, (2) an unsensitizable path identifier configured to identify at least some unsensitizable paths in the circuit and (3) a repair list generator coupled to the timing violation identifier and the unsensitizable path identifier and configured to generate a repair list based on both the at least some timing violations and the at least some unsensitizable paths.

Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

Abstract: Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.

Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Abstract: Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay.

Abstract: Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic elements and the nets of the logic design are generated. The partial routing leaves some of the nets unsuccessfully routed. An initial area associated with each of the logic elements is expanded for the logic elements that are connected to the unsuccessfully routed nets. Positions for the logic elements are determined from a linear system that reduces a total length of the nets connecting the logic elements and inhibits overlap of the areas of the logic elements. A second placement of the logic elements is generated from the positions. A complete routing of all of the nets is generated for the second placement. A specification of the second placement and the complete routing is output.

Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Abstract: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Abstract: The claimed subject matter provides systems and/or methods that facilitate utilizing a motion control timing model to coordinate operations associated with controlling motion within an industrial automation environment. For example, a cycle timing component can implement timing set forth by a timing model (e.g., that can be selected, preset, . . . ). Pursuant to an illustration, the cycle timing component can utilize the timing model to coordinate transmitting data, receiving data, performing calculations associated with data (e.g., to generate command(s)), capturing data, applying received commands, and so forth.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.

Abstract: A delay analysis device composed of a storage device and a data processing device analyzes a chip fabricating a semiconductor integrated circuit. Delay calculation is performed via an RC simulation with reference to a layout-implemented macro net list, macro layout data, and a cell timing library, thus producing macro delay information. An initial stage of a macro is annotated by the global clock path delay information including the edge information so as to produce a global clock delay-annotated macro net list, which is then converted into a macro delay-annotated net list. Based on the macro delay-annotated net list and timing constraint, the delay analysis device calculates delay times of signal paths and clock paths as well as clock skews with a high precision. It checks whether or not the relationship between the delay times of signal paths and clock paths meets the timing constraint, thus producing delay analysis information.

Abstract: In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip and selecting at least one path that maximizes the process coverage metric.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.

Abstract: The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Abstract: Provided is a technology for providing an efficient embedding method in virtualizing a wireless test-bed network. In a virtual network embedding method in a wireless test-bed network, at least one packing point is generated in a two-dimensional strip comprised of time and frequency bandwidth, and the best virtual network slice according to the packing point is disposed. To dispose the virtual network slice, a set of packing points on the strip is collected, the suitability of the network slice according to each packing point is determined, and the network slice is disposed such that a left bottom point of the network slice is disposed at a suitable packing point. Accordingly, the length of a TDM super frame in the virtual test-bed network can be minimized.

Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: A timing-control method of a hardware-simulating program can be applied to a software platform for facilitating control program development. The hardware-simulating program can be recorded in any suitable recording medium and defines therein a plurality of simulating elements which are automatically synchronized at intervals by setting specified time points as aligning points. The specified time points are set with adjustable intervals. By adjusting an interval between adjacent specified time points, the simulating speed between the adjacent specified time points can be changed to comply with practical requirements.

Abstract: A transient simulation system, methods and program product that implement an adaptive piecewise constant (PWC) model are disclosed. The invention evaluates an error criteria to determine a maximum allowable change in one of a current and a voltage; and simulates the transient conditions by implementing an adaptive step in the PWC model according to the maximum allowable change. The invention allows dynamic or static adaptation of a PWC model according to an error criteria.

Abstract: A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay generator inserter produces a delay-insertable version of the circuit by embedding a delay generator into each found CDC path. When activated, those delay generators give a signal delay to the corresponding CDC paths. A simulator simulates the behavior of the delay-insertable circuit by using a specified simulation pattern while deactivating the embedded delay generators. A delay pattern generator creates a delay pattern from simulation results, which activates or deactivates delay generators individually so as to produce signal delays that could affect output signals of the circuit. A verifier verifies the circuit by applying the delay pattern to each delay generator in the circuit.

Abstract: The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.