Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers. A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node. The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC. The PC can then be enumerated as the connected device by other PCs on the bus. The PC can emulate or morph itself into any desired device or even multiple devices at the same time. The invention also allows a PC to create devices that don't yet exist on the bus. The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Abstract: A method of initiating re-enumeration of a USB device without manual intervention is provided. The method involves a sequence emulating detachment and re-attachment of a device to the host while the device remains attached to the host. As the device remains attached to the host throughout the sequence, the host OS is manipulated to receive a plurality of preset device states in order for it to perceive a device change and to eventually initiate device enumeration. The sequence, which involves a series of command exchanges between the device and the host, may be initiated by a software application residing in the host upon an event requiring device enumeration.

Abstract: The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Abstract: PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: A system and method for emulating SCSI reservations using network file access protocols is provided. The system and method enable applications or operating systems on a networked computer designed to utilize SCSI reservations on only locally attached storage to also access networked data storage. The emulation occurs transparently to higher levels of operating systems or applications so that the applications or operating systems which are designed to only access locally attached storage may be enabled to access networked storage.

Abstract: A method and system is provided for emulating individual JTAG devices in a multiple device boundary scan chain. The method includes coupling an emulator to the scan chain, and obtaining the topology of the scan chain. One device within the scan chain is then selected, and at least one other device within the scan chain is placed into bypass mode. Emulation instructions are sent to the scan chain, so that the emulation instructions bypass the at least one other device and are executed by the one device.

Abstract: Method and computer program product for recommending cost effective upgrades for a computer system. At least one performance parameter is determined for an existing computer system. Up to date performance specifications for available upgrade components are obtained. A variety of potential systems are modeled utilizing at least one upgrade component, and at least one component from the existing system to create upgrade scenarios. At least one performance parameter is predicted for each upgrade scenario. The performance parameters for the upgrade scenarios are compared to the performance parameters of the existing computer system. The cost-effectiveness is determined for each upgrade scenario, and upgrade recommendations are made when the cost-effectiveness meets or exceeds a target value.

Abstract: A method and system for testing a computer is presented. The temperature of the computer is controlled by one or more on-board fans inside the computer's enclosure. Voltages are controlled at the Voltage Regulator Module (VRM) level. A test program is then run under varying temperature and VRM voltages, and the results of the test program are logged. The present invention can be used either at the manufacturer's location or the customer's site, either under local or remote control.

Abstract: A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.

Abstract: A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterising the memory abort is written to a fault status register 28 (memory-abort register). The data characterising the memory abort includes data identifying a register number associated with the memory access which gave rise to the memory abort. This register identifying data is used to emulate the action of the memory access instruction without having to read the program instruction lead to the memory abort. This is useful in providing virtualisation support for a virtual data processing apparatus 2.

Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers. A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node. The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC. The PC can then be enumerated as the connected device by other PCs on the bus. The PC can emulate any desired device or even multiple devices at the same time. The invention also allows a PC to create devices that don't yet exist on the bus. The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC.

Abstract: The present invention includes a repeater and a server for controlling access, from a terminal of an outside network, to the server of an inside network. The repeater and the server permit a packet transmission from the terminal to the server under limited conditions. When the server acknowledges a connection for the permitted packet, transmission conditions for packets to be sent to the server are loosened. Subsequently, packet transmission between the terminal and the server is controlled under the loosened transmission conditions. As for encrypted packets, the server decodes the encrypted packets and notifies the repeater of relevant information.

Abstract: Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource.

Abstract: A first virtual machine (VM) in a processing system may emulate a first server blade, and a second VM in the processing system may emulate a second server blade. The emulated server blades may be referred to as virtual server blades. A virtual machine monitor (VMM) in the processing system may provide a communication channel to at least one of the virtual server blades. Other embodiments are described and claimed.

Abstract: Several embodiments of the present invention provide a means for reducing overhead and, thus, improving operating efficiency in virtualized computing systems. Certain of these embodiments are specifically directed to providing a bypass mechanism for jumping directly from a first stack in the guest operating system to a second stack in the host operating system for a virtual machine environment. More specifically, certain embodiments of the present invention are directed to a system for and method of eliminating redundancy in execution of certain virtual machine commands and executing host environment equivalents by using bypass mechanisms, thereby bypassing redundant software layers within the guest and host stacks. For some of these embodiments, the bypass mechanism operates at a high-level component of the stack or, alternatively, the bypass mechanism operates at a low-level component of the stack.

Abstract: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one embodiment, a flow of instructions requested by a host processor from a memory device is monitored. The flow of instructions is routed to an application-specific component in response to identifying code embedded in the flow of instructions targeted for execution by the component. While the instruction flow is routed to the component, a sequence of instructions is directed to the host processor that maintains instruction execution flow in the host processor, e.g., no-op instructions. When the end of the application-specific code is detected, the instruction flow is re-routed to the host processor for execution.

Abstract: A method for storage virtualization in user space. The method includes providing a first emulation module running in the OS kernel and providing a second emulation module in the user space of the computer, which may emulate a media changer or other SCSI or other storage device. The method continues with a kernel-resident driver receiving a packet of data at a port of the computer that is linked to a data communications network (such as a SAN). The packet of data may include command data for a particular data storage device (e.g., a SCSI command for a SCSI device). The method includes operating the first emulation module to communicate with the driver and to then pass through the packet of data to the second emulation module, allowing the second emulation module to run in user space but efficiently receive data from the kernel-resident driver via the first emulation module.

Abstract: A two-level transformation scheme to enable a practical fast mesh-free method is disclosed. The first level transformation transforms the original chosen mesh-free shape function to a first transformed mesh-free shape function that preserves Kronecker delta properties. The first transformed mesh-free function allows the essential boundary conditions to be imposed directly. The second-level transformation scheme employs a low pass filter function served as a regularization process that filters out the higher-order terms in the monomial mesh-free approximation obtained from the first-level transformation scheme with desired consistency and completeness conditions. This integration scheme requires only a low-order integration rule comparing to the high order integration rule used in the traditional mesh-free methods. The present invention simplifies the boundary condition treatments and avoids the usage of high-order integration rule and therefore is more practical than the traditional mesh-free methods.

Abstract: A system for simulating interdependencies between a plurality of infrastructure models includes a first infrastructure data model that models a first infrastructure, a second infrastructure data model that models a second infrastructure, a simulation engine including a society of software agents and adapted to automatically produce, in response to a first change in the infrastructure data model, a second change in the infrastructure data model, and a user interface permitting a user to interact with the simulation engine. The system is adapted to simulate interdependencies between different critical infrastructure models as well as interdependencies between an infrastructure of one infrastructure category and an infrastructure of a different infrastructure category. Infrastructure categories include behavioral infrastructures, relational infrastructures, and physical infrastructures.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate the proprietary hardware systems of powerful older computers on platforms built using commodity processors. The systems being emulated are often large mainframe computers with large numbers of disks, communications systems and other attached hardware. Because of the size and expense, and also because databases involved must reside in only one location, it is difficult to replicate these systems for testing, development, debug or for providing alternative options to customers. A method for providing a single emulated computer system which provides for multiple views or options in control of the emulator is disclosed in which the options are dependent and selected based on job or user basis. The mechanism continues to provide for high performance and a single copy of the operating system with multiple processes, jobs and threads being emulated under user controlled parameters.

Abstract: The invention is an intellectual network storage device that uses a network to store and retrieve data, and that connects to an existing storage controller of a host computer. The device is transparent to the operating system of the host computer, and thus does not require additional software, such as a device driver, to operate. The device includes a device board, which is connected to an existing storage controller of a host computer via any suitable interface, a set of hardware or software acting as a remote storage server, and a connection that carries signals between the device board and the remote storage server.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: A system for developing the preceding logic to be implemented in a built-in microcomputer that is used while being incorporated in an electronic control unit. The system includes: a motherboard having a first CPU, a first memory, and a first interface via which the motherboard communicates with the outside, interconnected over a first internal bus; a core board having a second CPU, a second memory, quasi microcomputer peripheral devices, which simulate by software the peripheral devices of a microcomputer, and a second interface via which the core board communicates with the outside, interconnected over a second internal bus; and a PCI bus that links the motherboard and the core board. The development system is substituted for the built-in microcomputer in order to implement the preceding logic.

Abstract: A technique for emulation of a data storage system. The invention allows the level of services to be provided by a data storage system to be specified in terms of the level of services provided by another storage system. In one aspect, a performance characterization of a data storage device to be emulated is obtained (e.g., by experimental techniques). A specification of a workload is also obtained that includes a specification of a plurality of data stores for the workload. The data stores are assigned to an emulation data storage device according to the performance characterization and according to the specification of the workload such that sufficient resources of the emulation data storage device are allocated to the workload to meet the performance characterization of the data storage device to be emulated. The emulation data storage device is then operated under the workload. Quality-of-service (QoS) control may be performed so as to provide a degree of performance isolation among the workloads.

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

Abstract: An information processing apparatus includes: a display control means for controlling display of a GUI for operating a first apparatus including buttons operated when opening and closing a tray; and a processing means for performing processing by receiving an instruction from the first apparatus or for transmitting the instruction to the first apparatus, wherein the GUI includes graphics of a second apparatus obtained by copying out the first apparatus, and the second apparatus includes graphics corresponding to the tray and the button, when the button in the second apparatus is operated, the display control means controls graphics in which the tray is opened or closed in the second apparatus, and when the button provided in the first apparatus is operated, the processing means instructs the display control means to control graphics in which the tray is opened or closed in the second apparatus.

Abstract: A solid-state floppy disk drive is disclosed. In one embodiment, a solid-state floppy disk drive may include a non-volatile memory and a connector for coupling the solid-state floppy disk drive to a computer system. The non-volatile memory may store instructions and data which may allow the solid-state floppy disk drive to emulate a mechanical floppy disk drive having a bootable floppy disk inserted into it. The computer system may be booted using the solid-state floppy disk drive.

Abstract: A method and apparatus to improve the read/write performance of a hard drive is presented. A device having solid state, non-volatile (NV) memory is added in-line to the conventional hard drive and acts as a read/write cache. Data specified by the operating system is stored in the NV memory. The operating system provides a list of data to be put in NV memory. The data includes data to be pinned in NV memory and data that is dynamic. Pinned data persists in NV memory until the operating system commands it to be flushed. Dynamic data can be flushed by the hard drive controller. Data sent by an application for storage is temporarily stored in NV memory in data blocks until the operating system commits it to the disk.

Abstract: The present invention provides a method for avoiding demand forecast errors in a network topology model having a plurality of nodes, by monitoring and controlling the quantity of a selected port type at a node. The method comprises determining the actual quantity of a selected port type at a node, setting a forecast of the quantity of the port required, setting a forecast period for the ports, wherein the forecast period is a function of the time required to change the quantity of the ports, and setting a threshold value to generate alerts, wherein the threshold value is a function of the forecast period; monitoring the node for a forecast change, if a forecast change is found then computing the difference between the actual quantity and the forecast quantity, wherein if the difference is greater than the threshold value, then generating an alert and forwarding the alert to a user.

Abstract: A plurality of local and remote computers share a plurality of local manipulating devices, and the connection agreements of the computers and the manipulating devices are different. First electrical signals from these manipulating devices are received, and each of the first electrical signals complies with the connection agreement of its source manipulating device. Each first electrical signal is then converted to a standard packet. The paths of these standard packets are routed between the manipulating devices and the computers. Afterwards, each standard packet is converted to a second electrical signal which complies with the connection agreement of its destination computer.

Abstract: This invention relates to a method for replaying, from a log file, events in a process belonging to a software application. This method in particular relates to internal events within a process belonging to an application executed in a multi-computer environment. This method comprises the following steps: reading (1) or receiving event data (KL) by a replay agent (PRE); from the event data, transmission (2) by the replay agent to a communication agent of message data addressed to said target process capable of initiating said event for this target process; transmission (3, 6) of said message data to the target process and initiation of said event.

Abstract: A method and system for accessing audiovisual data in a computer, which has a hard disk, a hard disk controller and a device driver. The hard disk is divided into a partition region and a non-partition region. The partition region has an audiovisual table to record a location of the audiovisual data stored in the non-partition region. The non-partition region is emulated as an emulated compact disk drive. When the device driver determines to access the emulated compact disk drive, it performs a converting procedure to convert an access instruction to the compact disk drive into an access instruction to the non-partition region, and sets a command register of the hard disk controller in accordance with the instruction converted and the audiovisual table, thereby accessing the non-partition region.

Abstract: The generic device emulator provides an operational emulation of the behavior of any desired device within a device connectivity or other communications protocol as specified in a description of the respective device. This facilitates development and implementation of devices within a device connectivity architecture based on the protocol, since the user has only to define the description of the device. The generic device emulator provides default behaviors for a set of capabilities defined in the description for the device, which can be over-ridden or augmented by user-provided implementation of specific behavior for a capability. The generic device emulator also permits the user to inject defect behaviors, such as to introduce defects in the device's implementation of the protocol.

Abstract: A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to a peripheral bus fabric. A second bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to the peripheral bus fabric. The configurable host bridge operably couples to the virtual peripheral bus, supports a host mode of operation in which it serves as a host bridge, and supports a device mode of operation in which it operates as a device.

Abstract: A method to communicate provide server management information that emulates a floppy disk drive (FDD) with a management processor. This management processor operably couples to a multi-function integrated circuit having a FDD controller. Monitoring hardware and sensors operably couple to the management processor and write server management information to data files within the emulated FDD. Programs that utilize the server management information may then read this server management information.

Abstract: Embodiments of the invention relate to a data processing system and method for supporting dynamically assigning devices within a virtualisation environment.

Abstract: The present invention discloses dynamically adding virtual devices to a virtual computing environment. The system described in the invention includes a virtualized computing system with a manifest, which further includes device lists and an external device directory, which provides users of the virtualized computing system with a directory for adding software plug-ins that contain specifications needed to add virtual devices to the virtual computing environment. Certain embodiments are specifically directed to providing a method of adding and configuring virtual devices. Certain embodiments are specifically directed to providing a method of operating a virtualized computing system wherein the host operating system and the virtual devices progress through a series of states, such as: initializing, powering up, loading a stored state, operating in normal state, saving state for future restoration, powering down, and tearing down and turning off.

Abstract: Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of a plurality of buffers is sent. The synchronous request is responded to with the data from at least one buffer of the plurality of buffers.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: An apparatus for transcoding encoded content, the encoded content being encoded using a first coding algorithm, with a first interface for communicating with a content sink, the first interface being adapted for receiving a request for content being encoded using a second coding algorithm and for providing a transcoded content being encoded using the second coding algorithm. The apparatus further has a second interface for communicating with the content source, being adapted for providing a request for the encoded content being encoded using the first coding algorithm and for receiving the encoded content being encoded using the first coding algorithm. The apparatus further has a processing unit being adapted for processing the encoded content being encoded using the first coding algorithm to provide the transcoded content being encoded using the second coding algorithm.

Abstract: A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Abstract: Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Abstract: The present invention is directed to an extensible console emulator for Hyperion Performance Suite interaction. An emulator system in accordance with an embodiment of the present invention includes: a Hyperion Performance Suite (HPS) console emulator for receiving commands from a source and for performing actions based on the commands; and an HPS Software Development Kit (SDK) for receiving output from the HPS console emulator and for interacting with the HPS; wherein the HPS console emulator provides an interface that allows a user to interact with the HPS via the HPS SDK.

Abstract: A tape operation relating to EOF identification in an open process for a file is emulated, whereby the tape operation in the open process is simplified. Consequently, open-process, close-process performance, and process performance of a system accessing to a magnetic tape unit can be improved. In a method of this invention, a position of a head relative to a magnetic tape is fixed at a predetermined position in the open process for a file recorded on the magnetic tape, and when a command is received from a command issuing apparatus, emulation in which a tape operation according the command is virtually carried out in the magnetic tape unit without making said magnetic tape unit carry out a real tape operation, is executed.

Abstract: An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.

Abstract: Various embodiments of the present invention are directed to bimodal virtual device approaches (that is, “bimodal devices”). In certain embodiments, the bimodal device is a virtual device that is primarily based on a real piece of hardware to provide a broad degree of compatibility with software running in the guest environment (similar to the hardware device virtualization approach). However, to overcome the problem of poor performance that plague hardware virtual devices, these embodiments also provide an idealized “high-performance mode” that is not found in the original hardware-based device. Software drivers (and other software) developed for interacting with the original hardware device and which are unaware of (and unable to use) the high-performance mode will continue to use the “legacy mode” (hardware virtualization), while enhanced versions of guest software will be able to recognize and utilize the high-performance mode (idealized virtualization).

Abstract: In a back-up storage system, an apparatus and methods for mounting a data volume corresponding to a back-up data set to a host computer. In one example, a method includes mounting a data volume on a host computer, the data volume comprising at least one data file, the data file corresponding to a most recently backed-up version of the at least one data file stored on a backup storage system, and storing, on the backup storage system, data corresponding to a second version of the at least one data file that is more recent than the most recently backed-up version of the at least one data file stored on the backup storage system while preserving the most recently backed-up version of the at least one data file.

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.