Abstract: A configurable network switch is disclosed. The configurable network switch may include a plurality of network switch chips operatively connected to a plurality of connectors via a programmable crosspoint chip. The programmable crosspoint chip may be configured to operate in one or more network operating modes. In a first network operating mode, the programmable crosspoint chip may be configured to operate at 40 Gigabit Ethernet speeds, whereas in the second network operating mode, the programmable crosspoint chip may be configured to operate at 10 Gigabit Ethernet speeds. The configurable network switch may also include an input interface, such as an I2C interface, that allows an operator of the network switch to select the one or more network operating modes of the configurable network switch.

Abstract: A method and non-transitory computer readable medium for discovering network subnets are disclosed. For example, the method sets a host portion of a network address to a fixed value for a particular network, sends a discovery message to a subnet of a plurality of subnets having the fixed value of the host portion for the particular network, discovers the subnet if a response to the discovery message is received from a device and repeats the sending and the discovering until all of the plurality of subnets are checked, where the sending and the discovering are applied only to the fixed value of the host portion for each of the plurality of subnets.

Abstract: A data processing system facilitates virtual machine migration with direct physical access control. The illustrative data processing system comprises a software-programmable trap control associated with hardware registers of a computer that selectively vectors execution control of a virtual machine (VM) between a host and a guest. The data processing system further comprises a logic which is configured for execution on the computer that programs the trap control to enable the virtual machine to directly access the hardware registers when the virtual machine is not migrated and to revoke direct access of the hardware registers in preparation for virtual machine migration.

Abstract: A system comprises a guest graphics subsystem with a combined virtual graphics device that combines underlying emulated virtual graphics device and virtual function of a physical graphics device to support virtual machine migration. The VMM in the system may expose to the guest a single combined virtual PCIe graphics device that combines access to the virtual graphics device and the virtual function, and switches between the virtual graphics device and the virtual function for graphics acceleration without triggering a PnP event in the guest OS. In response to the switch, the guest graphics stack and applications may redraw their windows to provide a consistent user experience.

Abstract: A disclosed interface between an emulator and a network that is readily scalable. In one aspect, a scalable solution is achieved through a hardware interface board positioned between the network and the emulator to allow proper transfer there between. A computer is separated from and coupled to the hardware interface board and provides the necessary control signals. Because it is done in hardware separated from the computer, the interface board is readily scalable through the simple addition of network chip sets. In another aspect, the interface board can be placed in two modes of operation, a live test mode and a direct test mode. In yet another aspect, packet formats may be changed on the interface board so that it appears to the emulator as if the network is operating at a different data transfer speed than is actually the case.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: In an example embodiment, a device provides a connection to an endpoint coupled with a first network to a virtual desktop client coupled with a second network. The device obtains data from the virtual desktop client which client which includes at least one link to data available from an external server, such as streaming media. The device obtains the data from the external server and provides the data with data obtained from the virtual desktop client to the endpoint.

Abstract: Aspects of the present disclosure relate to methods of managing and delivering digital media content data. In certain embodiments, a management device in communication to a computing device via a universal serial bus (USB) connector is provided. The management device has a processor, a volatile memory and a non-volatile memory. The non-volatile memory includes a first partition storing a firmware and a second partition. When executed at the processor, the firmware emulates an emulated bootable storage device for the computing device at the USB connector. In response to an access instruction from the computing device to access data stored at an emulated address of the emulated bootable storage device, the management device converts the emulated address to a physical address of the second partition, and accesses the data at the physical address. The data includes digital media content data and a control module configured to play the content data.

Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.

Abstract: Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control of one of the primary firmware or secondary firmware. The selected one of said primary firmware and secondary firmware may be used to certify a hardware driver for either the current generation (primary firmware) or a future generation (secondary firmware).

Abstract: A means for extending a PCI System of a host computer via software-centric virtualization. A Root Complex is virtualized at the host computer, and physically separated with a portion located remotely at an Endpoint, such as at a Remote Bus Adapter. One aspect of the invention avoids the need for a Host Bus Adapter. The invention utilizes 1 Gbps-10 Gbps or greater connectivity via the host's existing standard LAN adapter along with unique software to form the virtualization solution. The invention works within a host's PCI Express topology, extending the topology by adding an entire virtual I/O hierarchy via virtualization. The invention enables I/O virtualization in those implementations where a specialized host bus may not be desirable or feasible. Some examples of this may be a laptop computer, an embedded design, a cost-sensitive design, or a blade host where expansion slots are not available or accessible.

Abstract: An integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric is disclosed. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic.

Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

Abstract: A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

Abstract: A print control device includes: a creation unit that creates print data; an output unit that outputs the print data created by the creation unit to a printing device through a designated port; a determination unit that determines whether or not the print data is to be output to a non-connected port that is a port not connected to the printing device; and a display unit which, when the determination unit determines that the print data has been output to the non-connected port, displays at least one of a first operation screen that is an operation screen for instructing port switching and a second operation screen that is an operation screen for instructing deletion of the print data.

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract: The invention is an intellectual network storage device that uses a network to store and retrieve data, and that connects to an existing storage controller of a host computer. The device is transparent to the operating system of the host computer, and thus does not require additional software, such as a device driver, to operate. The device includes a device board, which is connected to an existing storage controller of a host computer via any suitable interface, a set of hardware or software acting as a remote storage server, and a connection that carries signals between the device board and the remote storage server.

Abstract: A simulation environment for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for recovering data from a signal generator using a native communication channel and an emulated communication channel coupled in parallel to the native communication channel.

Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers. A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node. The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC. The PC can then be enumerated as the connected device by other PCs on the bus. The PC can emulate or morph itself into any desired device or even multiple devices at the same time. The invention also allows a PC to create devices that don't yet exist on the bus. The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC.

Abstract: In a normal operation, a physical unit simulator is allowed to speculatively perform high-speed continuous execution. Only when an actual input comes in, a speculative input and the actual input are compared with each other. Thereafter, in response to inconsistency between the inputs, the physical unit simulator is returned to a point closest to the point of the actual input and is allowed to execute a variable step module to reach the point of the actual input. Upon arrival at the point of the actual input, the simulator is shifted back to the high-speed continuous execution from there. Thus, a processing speed of the simulator can be significantly improved.

Abstract: Techniques for reducing virtual machine input/output emulation overhead and decreasing the attack surface of a virtual machine architecture are disclosed.

Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.

Abstract: To provide an emulator capable of targeting a device capable of accepting connection of an expansion device for expanding a controller connection port to a plurality of controller connection ports. The emulator, targeting a device having at least one controller connection port and capable of accepting connection of an expansion device for expanding the controller connection port to a plurality of controller connection ports so as to accept connection of a plurality of controllers, emulates operation of the targeted device. The emulator assigns port identification information to each of controllers connected via wire or radio, the port identification information indicating to which of a controller connection port of the targeted device and the controller connection ports of the expansion device connected to the device the controller is assumed to be connected. The assigned port identification information is provided to a process for receiving an operation carried out on the controller.

Abstract: A video game controller charging system for charging at least one video game controller is provided. The system includes a controller adapter including a battery unit, at least one first induction coil, and at least one first magnet, and is adapted to be received by the at least one video game controller; and a base including a power input, at least one second induction coil, and at least one structure on the base for providing physical support to the controller while the controller is being charged, the at least one structure including at least one second magnet. The base is configured to inductively charge the battery unit through inductive coupling between the at least one first induction coil and the at least one second induction coil when the controller is held in place on the structure by magnetic attraction between the magnets.

Abstract: A method may include creating an Extensible Markup Language (XML) instruction file based on screen shots of a host system, providing the XML instruction file to a screen scraper program, executing screen scraping operations based on the XML instruction file, and outputting a user interface file based on the screen scraping operations that corresponds to extracted data output from the host system.

Abstract: Techniques and mechanisms provide design information in a scalable representation. A design includes multiple master components and slave components. The master components and slave components include ports allowing interconnection. Techniques and mechanisms are described for selectively providing a subset of the interconnections between the master components and the slave components.

Abstract: Users with headsets may share an electronic device such as a portable computer or handheld device. The electronic device may have a connector such as an audio jack for receiving mating audio plugs on headsets. During normal operation with a single user, audio signals may be conveyed through the audio jack to the headset of the single user. When more than one user wishes to share the electronic device, an adapter accessory may be inserted into the audio jack of the electronic device. The headset of each user may be plugged into mating audio jacks in the adapter accessory. Circuitry in the adapter accessory may receive and process user input from each of the users. User input may be used to make local audio adjustments in the adapter accessory. User input may also be provided from the adapter accessory to the electronic device for processing.

Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers. A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node. The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC. The PC can then be enumerated as the connected device by other PCs on the bus. The PC can emulate or morph itself into any desired device or even multiple devices at the same time. The invention also allows a PC to create devices that don't yet exist on the bus. The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC.

Abstract: Provided is a microcomputer simulator capable of quickly dealing with change of a target microcomputer to thereby enable a speedy development of software. The microcomputer simulator is a microcomputer simulator for simulating a microcomputer including therein a CPU and a peripheral circuit of the CPU, and includes a mother board including a CPU for executing application software to be processed by the CPU provided in the microcomputer, and an IO board for executing, at an FPGA thereof, processing of the peripheral circuit provided in the microcomputer and IO processing executed by the CPU provided in the microcomputer. The FPGA includes a common memory portion so that the microcomputer simulator updates data stored in the common memory portion through a communication bus provided between the mother board 10 and the IO board, and causes data to be exchanged between the CPU provided in the mother board and the FPGA.

Abstract: A concurrent grouping operation for execution on a multiple core processor is provided. The grouping operation is provided with a sequence or set of elements. In one phase, each worker receives a partition of a sequence of elements to be grouped. The elements of each partition are arranged into a data structure, which includes one or more keys where each key corresponds to a value list of one or more of the received elements associated with that key. In another phase, the data structures created by each worker are merged so that the keys and corresponding elements for the entire sequence of elements exist in one data structure. Recursive merging can be completed in a constant time, which is not proportional to the length of the sequence.

Abstract: With N_Port ID Virtualization (NPIV), a managed system can he configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fibre channel adapter. An NPIV client recovery component of a virtualization management component, such as a Power Hypervisor (pHYP), provides the emulation mapping between server and client virtual fibre channel adapters. The pHYP also provides a mechanism that prevents client partition crashes when the NPIV server (e.g., a VIOS logical partition) goes down. When the NPIV server is rebooted or powers down, the pHYP handles the client LPARs to avoid a crash by removing processing resources from the client logical partition. Thereby, the client logical partition is prevented from attempting to access a root volume group in physical storage via the NPIV server. The pHYP allocates processor resources to the client LPAR when the NPIV server is again available for I/O processing.

Abstract: An interface device for an emulator is disclosed. The interface device includes a connection unit, a transmission unit, and an interface unit. The connection unit receives data, to be used to emulate a logic, from a host computer, and transmits result data, output from the logic, to the host computer. The transmission unit receives the data from the connection unit and stores (writes) the data in the first area of a register array. If the result data is stored in the second area of the register array, the transmission unit reads the result data and transmits the result data to the connection unit. The interface unit includes at least one register array, outputs a clock, set using the data stored in the first area, to the logic, and stores the result data, output from the logic, in the second area.

Abstract: System and method for operating a motor using a single general purpose input/output (GPIO) pin of a controller. In one embodiment, a control circuit may include a first terminal coupled to a GPIO pin of a controller. The first terminal can be configured to receive, and output, at least one or more signals. The control circuit may include a plurality of elements coupled to the first terminal, and motor driver circuit output terminal, such that the control circuit may be configured to output one more control signals to the motor driver circuit output terminal for control the motor driver circuit. Motor driver control signals may be based, at least in part, on one or more signals received from the first terminal.

Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.

Abstract: A computer-readable medium encoded with an instruction check program for making a computer to check a status of execution of an instruction by an I/O simulator that performs an operation simulation according to a structure of an I/O area of a microcomputer, the instruction check program when executed by a computer causes the computer to perform a method including obtaining specification information of the microcomputer describing an input and an output condition of a hardware resource in the I/O area, detecting a simulation of a reference instruction to the hardware resource executed by the I/O simulator, determining correctness of the reference instruction by comparing a content of the simulation of the reference instruction detected by the detecting with the input and output condition of the hardware resource included in the obtained specification information, and outputting an error signal when it is determined that the reference instruction is incorrect.

Abstract: A system on a chip comprises a plurality of circuit blocks, a programmable processor and a communication circuit. Design information includes connection data including an identification of the direct mutual connection and first and second circuit blocks coupled by the direct mutual connection. An additional register is added to the system on a chip coupled to the direct mutual connection. Verification programs are used includescomprising instructions for the processor to access registers in the second one of the circuit blocks, to use the connection data, or information derived therefrom to select the first one of the circuit blocks, and to issue the standardized call to the interface program of the selected further one of the circuit blocks.

Abstract: An analyzer for analyzing a specimen includes a central control unit that instructs systems of the analyzer of a process operation; and a primary control unit that time-divisionally outputs an instruction by the central control unit. The analyzer also includes a plurality of secondary control units; a communication connection unit; and a plurality of connecting units. The secondary control units are connected to the systems, respectively, and control an operation of the systems according to the instruction by the central control unit. Each of the secondary control units has positional information set in advance. The communication connection unit connects the primary control unit and the secondary control units. The connecting units are provided on a fixed arrangement position, have arrangement positional information indicating the arrangement position, and are connected to the secondary control units, respectively.

Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.

Abstract: Emulating HDMI-CEC devices, sub networks, or messages, including selecting the properties of an HDMI-CEC device to be emulated from at least two devices representing different functionalities, and initiating spoofed CEC messages. One of the methods includes selecting an initiator CEC logical address to emulate, and initiating a CEC message comprising the selected CEC logical address that is not unregistered logical address and does not represent a functionality of the device that actually initiated the CEC message.

Abstract: An embodiment of the present invention is a technique to process an input/output (I/O) transaction. An emulated device driver in a guest partition interacts with a virtual machine (VM) manager in processing an input/output (I/O) transaction on behalf of an application via an operating system (OS). The I/O transaction is between the application and a device. A device emulator in a service partition communicatively coupled to the emulated device driver interacts with the VM manager in processing the I/O transaction on behalf of a device specific driver via the OS. The device specific driver interfaces to the device.

Abstract: Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).

Abstract: A power testing apparatus for a USB interface includes first and second USB interfaces, and a simulation apparatus. The simulation apparatus includes a first voltage regulator, first and second resistors, and a load resistor. The first USB interface is configured to connect to a circuit board. The second USB interface is configured to connect to a USB device. The first voltage regulator includes input, output, and adjusting terminals. The first resistor is connected between the output terminal and the adjusting terminal. The second resistor is connected between the adjusting terminal and ground. The load resistor is connected to the output terminal and ground. Signal pins of the first USB interface are connected to signal pins of the second USB interface. A voltage pin of the first USB interface is connected to a voltage pin of the second USB interface and the input terminal.

Abstract: A data backup system is provided for backing up data files from a data source and for securing those data files against accidental modification or deletion. The system comprises storage and a data protection component that includes an application programming interface defining a command set. The system can also comprise a backup application that is configured to use the commands of the command set. The data protection component allows applications that use the commands of the command set, such as the backup application, to access the storage of the system. The data protection component prevents operating systems and applications that do not use the commands of the command set from accessing the storage. The data protection function of the data protection component can optionally be disabled to allow open access to the storage.

Abstract: A system and method for connecting a running logic circuit simulation to a network running at a higher speed that includes a computer for receiving data packets from the network and storing the received data packets in a first buffer. The computer next transmits the received data packets to an electronic circuit in the logic circuit simulation at a slower speed. The computer also receives data packets from the electronic device under simulation, and stores the data packets received from the electronic device under simulation in a second buffer. The computer then transmits the data packets received from the electronic device under simulation to the network at a higher speed.

Abstract: With N_Port ID Virtualization (NPIV), a managed system can be configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fibre channel adapter. An NPIV client recovery component of a virtualization management component, such as a Power Hypervisor (pHYP), provides the emulation mapping between server and client virtual fibre channel adapters. The pHYP also provides a mechanism that prevents client partition crashes when the NPIV server (e.g., a VIOS logical partition) goes down. When the NPIV server is rebooted or powers down, the pHYP handles the client LPARs to avoid a crash by removing processing resources from the client logical partition. Thereby, the client logical partition is prevented from attempting to access a root volume group in physical storage via the NPIV server. The pHYP allocates processor resources to the client LPAR when the NPIV server is again available for UO processing.

Abstract: An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. A simulator comprises: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section.

Abstract: A simulation method and system. The method includes receiving by a simulation engine in a device driver, input simulation parameters data associated with a simulation process. The simulation engine calculates a simulated scaled down process time period for a device associated with the device driver. The simulation engine simulates the device. The simulation engine calculates an overall runtime period for the device. The overall runtime period is calculated based on the simulated scaled down process time period. The simulation engine transmits the overall runtime period to a simulator software application for generating an operating schedule for operating the device.