Abstract: A system, method and software product emulate and profile an application to play on a mobile device. Characteristics defining performance of the mobile device are defined. The mobile device is emulated using a model based upon the characteristics. The application is played and monitored within the model to determine resource utilization of the application for the mobile device.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation.

Abstract: A method and apparatus for configuration templates for different use cases for a system. An embodiment of a method includes receiving an abstract configuration for a system. The received abstract configuration includes a configuration setting. The configuration setting is modified with a template, with the template being designed for a particular use of the system.

Abstract: Emulating legacy hardware using IEEE 754 compliant hardware is disclosed herein. In some aspects, the emulation includes locating an instruction that includes NaN (not a number) as at least one of an operand or a resultant. The emulation adjusts the resultant of the instruction, via additional code, to produce a final resultant of non-compliant (legacy) hardware. Legacy software, which was written in anticipation of processing by legacy hardware, may then be processed using compliant hardware.

Abstract: Architecture that provides the capability to receive types associate with external data and services and then integrate (or blend) these types into other applications such as office suite applications and collaboration applications. The result is the user is given a complete view of a given business problem and allows the user to complete tasks and plans in a single context. The architecture creates new defined types and blends these new defined types with the host native types of the particular host application (e.g., office application, collaboration application, etc.) so the user can operate from within a single context. Formal and pre-existent business applications, as well as external data sources are seamlessly proxied into the everyday productivity tools and/or collaboration environment to enable the user complete work as a single work stream within a known user experience with expected behaviors.

Abstract: Analyzing system malfunction data and associated direct and indirect effects in a collaborative tool to determine relationships between the effects and the system malfunction information. System malfunction cases and other data are received and stored. A user may view and/or modify the system malfunction data. The data may be presented in a relational structure. Each system malfunction case is linked to one or more direct effects, and each direct effect is linked to one or more indirect effects.

Abstract: A network testing environment includes a control server and a testing cluster composed of one or more load generating devices. The load generating devices output network communications in a non-deterministic manner to model real-world network users and test a network system. The load generating devices operate in accordance with probabilistic state machines distributed by the control server. The probabilistic state machines model patterns of interaction between users and the network system.

Abstract: Flexible network policies might be enforced by (a) obtaining a flow of network packets, (b) determining a content characteristic by characterizing content of the flow using bit-stream level statistics, (c) determining content-independent flow characteristics, port-independent flow characteristics, and/or application header-independent flow characteristics, and (d) enforcing a policy on the flow using both (1) the determined content characteristic and the (2) determined content-independent flow characteristics, port-independent flow characteristics, and/or application header-independent flow characteristics.

Abstract: A processor based system including a processor and a storage subsystem communicatively coupled with the processor, an operating system stored in the storage subsystem to schedule instructions for execution, including a driver in which are included a virtual machine monitor and an emulator for an emulated processor; and a virtualization subsystem of the processor based system to generate an event for the virtual machine monitor.

Abstract: A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.

Abstract: A method for emulating a system call includes making the system call by a first process in a first operating system (OS) for interacting with a second process, wherein the first OS is emulated in a second OS, spawning an agent process, wherein the agent process is a child process of the first process, implementing a functionality of the system call using a general mechanism in the second OS between the agent process and the second process, passing a result associated with the system call from the second process to the agent process using the general mechanism, and relaying the result from the agent process to the first process using a system call in the second OS, wherein the result is stored by the first process.

Abstract: Provided are a method, system, and article of manufacture, wherein instructions stored in an option ROM are copied to the system memory of a computer, wherein the option ROM corresponds to a device that is coupled to the computer. A virtual machine is generated, wherein the virtual machine executes the instructions copied to the system memory to boot the device before any operating system is loaded.

Abstract: A video display terminal capable of operating with a graphical user interface such as Windows provides windowing functionality to permit use of popular applications programs resident on a server, without requiring more than application data to be transmitted from the server, and keyboard and mouse information to be transmitted from the terminal to the server. The terminal includes processing means, not fully compatible with personal computer BIOS or disk operating systems and incapable of executing windowing applications locally, adapted to receive windowing information supplied by programs executing on a remotely located application server. The terminal also includes a display for the windowing information supplied by programs executing on the remotely located application server. The invention provides FTP and SNMP capabilities along with a number of user interface enhancements, DHCP and SNMP enhancements. File information is transferred to and from the terminal using a communications protocol.

Abstract: The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Abstract: Techniques for simulation of multi top-level graphical-containers (e.g., frames) in an object-oriented computing environment are disclosed. A Multi Top-level Graphical-Container Simulator (MTGS) can be provided to simulate multi top-level graphical container support for applications that expect to use a plurality of top-level graphical containers (e.g., frames, windows). A MTGS may be implemented as a layer between a GUI-based application and an operating system and/or hardware/device with limited or virtually no graphical support capability. The Multi Top-level Graphical Simulator (MTGS) can effectively isolate the operating systems and/or hardware/device from the GUI-based application, and yet hide this simulation from the operating system and/or hardware/device. MTGS may be implemented in a platform independent programming language (e.g., Java™ programming language using a set of Java™ classes which have been provided in the Java™ Swing development toolkit.

Abstract: Systems and methods are provided for annotating software with performance information. The computer code is compiled into assembler code, the assembler code is translated into a simulation model, expressed in assembler-level source code. The simulation model is annotated with information for calculating various performance parameters of the software, such as timing information, or resource usage information. The simulation model is then re-compiled and executed on a simulator, optionally including a hardware simulation model, and the performance information is computed from the simulation.

Abstract: Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource.

Abstract: A first virtual machine (VM) in a processing system may emulate a first server blade, and a second VM in the processing system may emulate a second server blade. The emulated server blades may be referred to as virtual server blades. A virtual machine monitor (VMM) in the processing system may provide a communication channel to at least one of the virtual server blades. Other embodiments are described and claimed.

Abstract: Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

Abstract: The memory access capabilities of a host processor are used to facilitate the movement of instructions and data to an application-specific component having direct access to memory. Although the component executes code absent direct host processor control, the code may be uniquely tailored to the component's architecture. According to one embodiment, a flow of instructions requested by a host processor from a memory device is monitored. The flow of instructions is routed to an application-specific component in response to identifying code embedded in the flow of instructions targeted for execution by the component. While the instruction flow is routed to the component, a sequence of instructions is directed to the host processor that maintains instruction execution flow in the host processor, e.g., no-op instructions. When the end of the application-specific code is detected, the instruction flow is re-routed to the host processor for execution.

Abstract: Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data.

Abstract: Multiple versions of a runtime system, such as a software emulation application that emulates a legacy hardware architecture, are allowed to co-exist in the memory of a new hardware architecture. The operating system software of the new hardware architecture reads configuration data from a database or table to decide which version of the runtime system is desirable for an application program or game that is being loaded or is currently running, and, if a match is found, only that runtime system is invoked. To reduce storage footprint, the different versions of the runtime system may be stored using “differential patching” techniques. In this configuration, the operating system will always launch the same basic runtime system binary, but it will select a different differential patch to apply at run-time based on the title as determined during the database lookup.

Abstract: Reference architecture instructions are translated into target architecture operations. In some embodiments, an execution unit of a processor executes a function determined from a collection of operations, the function specifying functionality based on instructions, the collection selected from operations translated from the instructions. In further embodiments, the function is specified as a fused operation. Sequences of operations are optimized by fusing collections of operations; fused operations specify a same observable function as respective collections, but advantageously enable more efficient processing. In some embodiments, a collection comprises multiple register operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, fusing operations requires setting only final architectural state, such as final flag state; intermediate architectural state is used implicitly in a fused operation.

Abstract: Software managing long names in an application programming interface receives a request to perform a requested operation on one or more fields, the application comprising a first operation operable to perform the requested operation on at least one field type. The software determines whether the field type of any of the fields is incompatible with the first operation. If the field types of the one or more fields are compatible with the first operation, then the software performs the requested operation on the one or more fields using the first operation. If the software determines that the field type of at least one of the fields is incompatible with the first operation, then it converts the request into a call for a second operation operable to perform the requested operation on the one or more fields and performs the requested operation using the second operation.

Abstract: A software development technique is provided using target system virtualization software simulating behaviour of a target system. A target device driver running on a host system issues memory access commands to the target system virtualization software rather than to a memory interface unit of the host system. The memory interface unit may be an SRAM (Static Random Access Memory) interface. The target system may be an EGPRS (Enhanced General Packet Radio Service) modem.

Abstract: Methods and apparatus are disclosed to self-initialize a processor. An example method disclosed herein detects a processor reset, receives initialization instructions from a core zone, establishes a core zone boundary, executes received initialization instructions, and publishes a data structure, the data structure comprising state information. Other embodiments are described and claimed.

Abstract: A two-level transformation scheme to enable a practical fast mesh-free method is disclosed. The first level transformation transforms the original chosen mesh-free shape function to a first transformed mesh-free shape function that preserves Kronecker delta properties. The first transformed mesh-free function allows the essential boundary conditions to be imposed directly. The second-level transformation scheme employs a low pass filter function served as a regularization process that filters out the higher-order terms in the monomial mesh-free approximation obtained from the first-level transformation scheme with desired consistency and completeness conditions. This integration scheme requires only a low-order integration rule comparing to the high order integration rule used in the traditional mesh-free methods. The present invention simplifies the boundary condition treatments and avoids the usage of high-order integration rule and therefore is more practical than the traditional mesh-free methods.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

Abstract: Node-to-node communication pipelines may include code modules that are configured and assembled across a protocol according to dynamically input module-specific parameters. The parameters may be input to a service into which the modules are registered, and one or more appropriate pipelines may be dynamically assembled.

Abstract: The invention describes a test bed, a method and a computer program product for testing an application installed on a wireless communication device. The wireless communication device communicates with a server over a network through the test bed. Further, the test bed is connected to the server and receives various testing parameters from a user. Furthermore, the test bed establishes a wireless connection between the test bed and the wireless communication device. Thereafter, the test bed emulates various network conditions, based on the testing parameters, and subsequently communicates the emulated network conditions to the wireless communication device. The application installed on the wireless communication device experiences the emulated network conditions. The user then tests the application in the emulated network conditions.

Abstract: A method is provided to automatically allocate resources of an integrated circuit (IC) to form multipliers in a given design to optimize the use of IC resources. Information about the multipliers in the design is extracted to place the multipliers into a priority order. The priority allows primitives in the IC, like DSP blocks LUTs or MUXCYs to be economically allocated to the multipliers. The ordering criteria can include: (1) a user defined criteria, (2) the number of primitives required to implement a multiplier, or (3) a size of the multiplier operands. This invention further optimally allocates LUTs and MUXCYs when DSP48 blocks are exhausted. The steps for generating a multiplier include: constructing a partial product matrix and minimizing the adders used in the multiplier by minimizing the size of support for the partial products. Either LUTs or MUXCYs are selected depending on the size of support determined.

Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.

Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

Abstract: A simulating method for loading different operation systems by means of externally connected simulation and a simulation device thereof. The simulating method and the simulation device are achieved by means of hardware. The simulation device can be externally inserted to a personal computer, enabling the personal computer to simulate different operation systems without being incautiously damaged by a user.

Abstract: A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

Abstract: Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of a plurality of buffers is sent. The synchronous request is responded to with the data from at least one buffer of the plurality of buffers.

Abstract: A host operating system can take ownership of a device. The host can project the presence of a device proxy (VDP) into a guest operating system. The VDP provides a set of device functions corresponding to the particular device class. Interactions with the VDP in the guest are forwarded to a Virtual Service Provider (VSP) in the host. The VSP maps a set of device class functions onto physical devices through a hardware abstraction and emulation layer. Functions supported directly by a physical device can be delivered to the device by the hardware abstraction layer (HAL). Functions not directly supported can be implemented through the hardware emulation layer (HEL). A uniform and robust set of functions may be made available in the guest regardless of hardware changes in the host, migration to a new host, or use of the device by other competing operating systems.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: An apparatus for transcoding encoded content, the encoded content being encoded using a first coding algorithm, with a first interface for communicating with a content sink, the first interface being adapted for receiving a request for content being encoded using a second coding algorithm and for providing a transcoded content being encoded using the second coding algorithm. The apparatus further has a second interface for communicating with the content source, being adapted for providing a request for the encoded content being encoded using the first coding algorithm and for receiving the encoded content being encoded using the first coding algorithm. The apparatus further has a processing unit being adapted for processing the encoded content being encoded using the first coding algorithm to provide the transcoded content being encoded using the second coding algorithm.

Abstract: A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Abstract: Systems and methods provide for emulating a host architecture in guest firmware. One aspect of the systems and methods comprises determining whether an emulated instruction would cause a transition into a legacy mode. A current execution context is converted into a legacy mode context, and the firmware emulator proceeds to a group of legacy mode instructions in a native mode for the processor. The firmware emulator detects an end instruction and converts the legacy context back to the guest firmware context.

Abstract: The present invention is directed to an extensible console emulator for Hyperion Performance Suite interaction. An emulator system in accordance with an embodiment of the present invention includes: a Hyperion Performance Suite (HPS) console emulator for receiving commands from a source and for performing actions based on the commands; and an HPS Software Development Kit (SDK) for receiving output from the HPS console emulator and for interacting with the HPS; wherein the HPS console emulator provides an interface that allows a user to interact with the HPS via the HPS SDK.

Abstract: The present invention relates to a method and apparatus for running an application (APPL) of a mobile device (MB) on an external device (PC). The mobile device comprises an application (APPLI) for running on an operating system (OS_H) of the mobile device, and an emulator (E_M) for emulating the operating system (OS_M) of the mobile device. The method comprises establishing (1, 2) a communication link between the mobile device and the external device (PC); triggering (3) the emulator (E_M) to run on an operating system (OS_H) of the external device (PC); and running the application (APPL) of the mobile device on the emulator (E_M).

Abstract: An information processing system includes a preparation machine with an installed image; an execution machine on which the installed image is virtually installed; and a virtualizer for virtualizing the installed image on the execution machine to produce a virtually installed image by using a hierarchy of selective virtualizers, wherein the virtualizing is selective such that not all operations of the executing software of the installed image at any particular level are virtualized.

Abstract: Systems, methods, and devices are provided for embodiments of the present invention to describe a technique that provides an operation region and associated operation region handler to define a virtual device for extending the functionality of an existing operating system.

Abstract: A flexible printing subsystem is enabled with a printer filter pipeline. A configurable and arbitrary number of printer filters forming a printer filter pipeline are applied to files that are to be printed. In a described implementation, the printer filter pipeline may implement enhancement features and conversion functions as determined by the individual printer filters forming the printer filter pipeline. The printer filter pipeline is established in accordance with a printer filter configuration file. The printer filter configuration file stipulates a printer filter order and includes a printer filter entry associated with each printer filter to be part of the printer filter pipeline. Each printer filter entry identifies the associated printer filter by name and enumerates the interfaces thereof. Printer filters may be adjacently linked in a printer filter pipeline when their mating interfaces match.

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract: A method and apparatus described herein are for providing a simplified option Read Only Memory (ROM) that is compatible in multiple firmware and platform architectures. Instead of providing multiple option ROM images for every variation of platform architecture and firmware architecture, a single code image is provided along with an interpreter stub. If the default code type of the code image is supported by a platform, then the option ROM is directly launched from the single code image without launching the interpreter stub. However, if a device including the option ROM is inserted in a different variation of platform or firmware architecture that does not support the single code image code type, then the interpreter is launched, which in turn interprets, translates, and/or launches the single code image.