Abstract: The present invention relates to an apparatus for carrying out a harness design in a short time while taking a physical characteristic of a harness at the design and development of equipment incorporating the harness. The apparatus comprises a component information preserving unit for preserving three-dimensional model data on a component other than the harness in an apparatus which is an object of design, a harness information setting unit for setting information on the harness as harness information, a characteristic information setting unit, a three-dimensional model constructing unit for constructing a three-dimensional model of each of the harness and the component on the basis of the harness information set in the harness information setting unit, the three-dimensional model data on the component in the component information preserving unit and the characteristic information set in the characteristic information setting unit, and a display control unit.

Abstract: An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circuits that can be based on any signal generated by the device under test during run time, including signals that were optimized out of the design during the compilation process. The dynamic netlists can be loaded and used in the emulator without having to recompile the entire design, which could take many hours. This enables a user to quickly and efficiently debug circuit designs.

Abstract: Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.

Abstract: A network testing environment includes a control server and a testing cluster composed of one or more load generating devices. The load generating devices output network communications in a non-deterministic manner to model real-world network users and test a network system. The load generating devices operate in accordance with probabilistic state machines distributed by the control server. The probabilistic state machines model patterns of interaction between users and the network system.

Abstract: Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are queried as to the capabilities of the engines. A co-simulation engine is selected based on the capabilities, and an instance of the engine is created. The selected co-simulation engine is configured, input logic vectors are provided to the selected HDL co-simulation engine, and the co-simulation engine is executed accordingly.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract: A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.

Abstract: Embodiments of the present invention are directed to a networked software and service dispensing vending machine (also referred to as a “software ATM”) for dispensing software and providing services to a portable computer system. Software stored on the software ATM is offered for sale and, once payment is received, downloaded into a portable computer system. A communications interface on the software ATM allows communications with the portable computer system. The software can be displayed on the software ATM prior to being purchased. Once payment is received for the software, it is downloaded into the portable computer system using the communications interface. A network connection on the software ATM provides communications with a network server.

Abstract: An electronic apparatus for testing equipment for serial busses employs a generic bus model that breaks down a serial bus into separate layers that are managed by separate processors. The processors have parameters that can be programmed for communicating via one type of serial bus, or can be reprogrammed for communicating via another type of serial bus.

Abstract: A method and apparatus for emulation of IOS in a feasible and efficient manner are provided. The method includes defining a data structure to hold a data set; opening a socket connection to the device; sending instructions to return the command data for an index value; storing the returned command data in the data structure; incrementing the index value, repeating the sending, the storing and the incrementing till the index value exceeds the depth of command data to be captured; and writing the command data captured in the data structure to a file. The depth of command data to be captured or stored can be defined by specifying an index value in the data structure.

Abstract: The claimed method and system collects an alert link for display at a client device. The alert link may be associated with a trigger placed on a parameter associated with a legacy application. The alert link may be used to retrieve security and configuration data for the associated legacy application to dynamically activate an interface to the legacy application and configure the legacy application to a target state that enables a user to easily retrieve necessary data.

Abstract: A system, method and article of manufacture are provided for performing a comparative analysis of vendors of network-related products or services. The present invention includes first determining a current network framework. Thereafter, a graphical depiction of the current network framework is displayed along with a plurality of components thereof. Next, a comparative analysis of at least two vendors of network-related products or services is presented. This is accomplished with indicia coding that highlights various aspects of the vendors.

Abstract: A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.

Abstract: A method for changing operation of a device, comprising: sending target device descriptors to the device's device emulator, which processes and stores the descriptors as the current descriptors in memory, and the device emulator responding to a query from a host simulating operation of the target device. Using the method, the host recognizes the device as a different, target device, such as printers, MFPs, peripherals, digital cameras, etc. Device emulation enables installation and other testing of a new and yet unavailable target device under development. The methods also include USB device enumeration, making a print job containing extended PJL commands and sending it using a generic device driver, emulator firmware analyzing and storing the descriptors in registers, sending a line reset command to simulate device detachment and reattachment, and meeting timing requirements of USB detached and attached states.

Abstract: Disclosed is a device arranged to process messages for communications, comprising a virtual machine means including a message processor means which is arranged to process messages communicated to and/or to be communicated from the device, and message processor instruction means, arranged to provide directions for operation of the message processor means. Also disclosed is a method for operating a device arranged to process messages for communications and a method of programming a device arranged to process messages for communications.

Abstract: In a first general aspect, a method of adapting an interactive electronic form is described. The method includes extracting, from an interactive electronic form, source code that defines at least one function of the interactive electronic form. The interactive electronic form has a format that is supported by a reader application. The method also includes parsing the source code to identify components of the interactive electronic form, generating an executable application using the identified components that when executed provides the at least one function of the interactive electronic form, and forwarding the executable application for execution on a device that does not have the reader application.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Abstract: Method and apparatus for modeling a business process to facilitate evaluation of driving metrics. A decision tool can be provided to help manage a business process. Model files are created based on data pertaining to a plurality interrelated metrics. Each of the plurality of model files is optimized. The results of the optimization for the various metrics can be combined into a summary, which describes a hierarchy of selected driving metrics in such a way as to facilitate an understanding how to fine-tune various metrics to meet goals. An embodiment of the invention can take the form of a stand-alone computing system running a spreadsheet program, a stand-alone computer system running a dedicated application, or a computer system interconnected with a data warehouse to acquire current data regarding the interrelated metrics.

Abstract: A system and method for authorizing access to a controlled entity by a user. A set of user privileges is provided for user; and a content manager intersects an access control list (ACL) and the set of user privileges to authorize access. Binding level control indicia selectively binds an access control list (ACL) to the controlled entity at item type, item, mixed, or library binding level. An item type comprises one or more component items with each component item having one or more item views which together form an item type view. A content manager is responsive to the binding level to perform ACL checking for authorizing access to the controlled entity by the user.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: A simulation environment includes a number of simulation domains. Particular simulation domains in a simulation environment are selectively activated and deactivated such that performance and resolution for a circuit design being simulated are dynamically controlled.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract: An apparatus and method for searching a database of web site functional characteristics to identify web sites that are compatible with designated functions are provided. With the apparatus and method, a database of functional characteristics is compiled and a search interface is provided. The database may be compiled in an automatic, manual, or semiautomatic manner by, for example, retrieving web site content with various functions of a web browser disabled and analyzing the resultant output through the web browser. With the search interface, a user may enter designations of the functional characteristics that the user is either interested in having or not having in the resultant list of web sites. Based on the user's designation of functional characteristics, the search engine associated with the search interface searches the database of web sites and identifies the web site entries in the database that are compatible with the designated functional characteristics.

Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.

Abstract: A removable magnetic storage device uses an optical drive interface to appear to the operating system as an optical drive. Thus, a removable magnetic drive appears to the operating system as a large optical device similar to DVD/CD, and receives similar functionality. By appearing as an optical device, the removable magnetic storage device can use many features not currently available to magnetic storage devices, such as autorun, multiple volume sets, larger capacity, and efficient space allocation.

Abstract: A data processing system is arranged to execute multiple program threads, with each program thread comprising program thread instructions. An interpreter is operable, during execution of each program thread, to employ a table pointer to reference a table to determine for a current program thread instruction a sequence of native instructions to be executed by the processor core to effect execution of that current program thread instruction. A consistency module is provided which is responsive to occurrence of a predetermined event to cause the table pointer to be manipulated, such that for a predetermined number of the program threads, the interpreter will be operable to associate a subsequent program thread instruction with a predetermined routine to be executed by the processor core, the predetermined routine being operable to cause the state of the corresponding program thread to be made available for subsequent reference.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A system, for example, includes software executing within an emulation environment provided by a computing system. The emulation software emulates an instruction processor having an interface to receive inter-processor messages. During emulation the emulated instruction processor calculates an actual count of the inter-processor messages received during emulation. A compiler executing on the computing system compiles test software to output an instruction stream for execution by the emulated instruction processor. The compiler calculates an expected count of inter-processor messages that the emulated instruction processor is expected to receive during emulation.

Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor. The behavior of the given DSP fixed-point processor is then modeled in a C++ environment using the library of classes.

Abstract: A method for monitoring and emulating privileged instructions of a program that is being executed at a privilege level in a virtual machine is disclosed. A privilege level associated with a received instruction is determined. The instruction privilege level is compared to the program execution privilege level. If the instruction privilege level is valid with respect to the program execution privilege level, the instruction is executed. If the instruction privilege level is invalid with respect to the program execution privilege level: the instruction result is emulated; the number of times the instruction has been received from the program is checked; and if the instruction has been received more than a specified number of times, the instruction is overwritten with one or more instructions with a valid privilege level with respect to the program execution privilege level.

Abstract: A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.

Abstract: A system and method for modeling the configuration of a network device is described. Such a system could include, for example, a CLI-to-XML converter connected to a schema storage device or a CLI-to-XML converter in combination with document object model (DOM) generator. Other embodiments could include a CLI-to-XML converter, a schema hash system, and a DOM generator.

Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.

Abstract: A method and apparatus for managing the configuration of a computing arrangement having a host operating system and an emulator operating system includes establishing host operating system interfaces to computing arrangement components. The computing arrangement is scanned, using the host operating system interfaces, to determine configuration information about computing arrangement components reserved for use by the emulator operating system. At least a portion of the scanned configuration information is communicated to the emulator operating system.

Abstract: A method for obtaining real-time debug information, e.g., state information and trace information, from an FPGA acting as a virtual microcontroller that is attached to a microcontroller under test. The two devices, the microcontroller and the FPGA execute the same instructions in lock-step with the FPGA acting as an emulator. The FPGA emulates the actual microcontroller and relieves the actual microcontroller from having debug logic installed thereon. FPGA and microcontroller, are coupled using a four pin interface. The FPGA is directly coupled to the PC for both programming and control. The system is implemented such that the microcontroller forwards information regarding I/O reads, interrupt vector information and watchdog information to the FPGA in time before the execution of the next instruction. Thus, the FPGA has an exact copy of the state information of the microcontroller.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: The various embodiments of the invention relate to analyzing operations of an emulated input-output processor. Instructions native to the first type of instruction processor are emulated on a second-type instruction processor. The instruction processor emulator executes an operating system that includes instructions native to the first type of instruction processor. The operating system includes instructions that write input/output (IO) requests to the memory arrangement in response to IO functions invoked by a program. An IOP emulator that is executable on the second-type processor emulates IOP processing of IO requests from the memory arrangement. The IOP emulator maintains in the memory arrangement a first set of data structures used in processing the IO requests. State data currently contained in the data structures is stored on a retentive storage device, and in response to user input controls, the state data is read from retentive storage and displayed.

Abstract: A watchdog timer control using a gatekeeper in an In-Circuit Emulation system. The In-Circuit Emulation system has a microcontroller operating in lock-step synchronization with a virtual microcontroller. When a watchdog event occurs, the gatekeeper, forming a part of the virtual microcontroller, crowbars the reset line of the virtual microcontroller as well as the real microcontroller. This freezes the state of the virtual microcontroller so that debug operations can be carried out. The gatekeeper operates with its own gatekeeper clock independent of the microcontroller clock. When a watchdog event occurs, the gatekeeper clock is rerouted to the virtual microcontroller to facilitate debug operations of the virtual microcontroller.

Abstract: Data necessary for diagnosing the condition of software of a virtual living thing or the condition of a hardware keeping the virtual living thing are acquired from the hardware or a storage medium storing the software, and are analyzed, and the condition of the virtual living thing is diagnosed on the basis of the analysis result. Besides, data necessary for diagnosing the hardware or the software of a robot apparatus are acquired from the robot apparatus or the storage medium storing the software, and are analyzed, and the condition of the robot apparatus is diagnosed on the basis of the analysis result.

Abstract: In a system for function settings of operating components in a piece of electronic equipment, a microcomputer circuit (4) of a radio receiver outputs function control signals to a radio receiver circuit (2), based on operating input signals. An input-output port correspondence setting program is downloaded from an external personal computer (8) to the microcomputer circuit (4), this program displaying a correspondence guide screen on a display of the external personal computer (8) and generating control function assignment data between groups of operating components (31a, 31b), (32a to 32c), and (33a to 33c and 34a to 34c) having the same type and characteristics. This data is transferred to the microcomputer circuit (4), so that the microcomputer circuit (4) sets the relationships of correspondence between the input and output ports (4d) and (4e), based on the input-output port correspondence setting program.

Abstract: A method and apparatus for merging design intent of multiple designers with respect to a digital model of an object are described. In one embodiment, the method includes receiving data concerning a change to the digital model performed by a fist designer. The method further includes analyzing the data concerning the change performed by the first designer and data concerning a digital model version created by a second designer, and integrating the change performed by the first designer into the digital model version created by the second designer.

Abstract: An analytical virtual machine (AVM) analyzes computer code using a software processor including a register that stores behavior flags indicative of behaviors identified by virtually executing the code within the virtual machine. The AVM includes a sequencer that stores the sequence in which behavior flags are set in the behavior flags register. The AVM analyzes machine performance by emulating execution of the code being analyzed on a fully virtual machine and records the observed behavior. When emulation and analysis are complete, the AVM returns the behavior flags register and sequencer to the real machine and terminates.

Abstract: A print architecture, including a print manager interposed between an application and a set of installed filters that complete features associated with submitted print jobs, includes an integrated data tree that stores a composite of the features and printer personalities supported by the print system including the installed filters. Properties/behaviors of components of the print architecture, including installed print filters and job tickets, are specified in accordance with an XML-based print schema. A print manager interface facilitates parsing and incorporating feature completion capabilities supported by the installed filters. A capabilities interface presents the features supported by the filters, organized in the form of feature descriptors.

Abstract: A data storage system for storing data for a host processor includes physical data storage devices each having data storage attributes and an outboard storage manager. The outboard storage manager is operable with the physical data storage devices for presenting to the host processor a virtual data storage image having a desired data storage attribute for a particular data storage application by organizing the physical data storage devices in an arrangement suitable for providing the desired data storage attribute irrespective of the data storage attributes of the physical data storage devices such that the combined physical data storage device arrangement emulates the virtual data storage image. The outboard storage manager is operable to transfer data between the host processor and the organized physical data storage device arrangement via the virtual data storage image.

Abstract: A real time functional replicator (10) of a specific integrated circuit comprised of a processing unit and peripherals in order to perform specific digital and/or analog functions controlled by specific software, this specific integrated circuit being designed to be incorporated into a specified application board.