Abstract: A method for a virtual sensor system corresponding to a target physical sensor is provided. The method may include selecting a plurality of measured parameters provided by a set of physical sensors based on operational characteristics of the virtual sensor system. The method may also include establishing a virtual sensor process model indicative of interrelationships between one or more sensing parameter and the plurality of measured parameters. Further the method may include obtaining a set of values corresponding to the plurality of measured parameters; calculating a value of the sensing parameter based upon the set of values corresponding to the plurality of measured parameters and the virtual sensor process model; and providing the value of the sensing parameter to a control system.

Abstract: An apparatus for creating a protocol stack has at least one protocol layer with at least one standardized interface and an instance for the administration of the protocol stack. The protocol stack is created by making available the protocol layer(s), randomly compiling the protocol stack from the protocol layer(s), and making available an instance for the administration of the protocol stack using a graphical user interface.

Abstract: A microcomputer chip includes a plurality of first electrode pads arranged in a chip circumferential section; a plurality of second electrode pads arranged inside from the plurality of first electrode pads; and an emulation circuit connected with the plurality of second electrode pads to interface with an external unit in emulation. The plurality of second electrode pads may be arranged on an area where a functional circuit is formed.

Abstract: Disclosed is a host terminal emulator installed in a client computer to detect a coordinate at which a non-protecting attribute is set from coordinates in CUI screen data when it is received from a host computer, to generate GUI screen data in which GUI parts corresponding to the non-protecting attribute are set at respective coordinates following the detected coordinate, to correct the GUI screen data so as to transform the GUI parts in response to the coordinate at which the non-protecting attribute is set, and to display a screen based on the corrected GUI screen data on a monitor.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: An embodiment of the invention is a technique for enabling an emulator that emulates an e-mode program to utilize stored data items whose values are stored in native data format in native memory. The emulator fetches an item referenced by the e-mode program. The referenced item comprises a tag field and a data field. The emulator determines whether the tag field of the referenced item indicates that the referenced item is an external reference word (ERW). If the tag field of the referenced item indicates that the referenced item is an ERW, the emulator decodes the ERW to obtain a data type and a pointer. The pointer corresponds to a location of a stored data item in native memory.

Abstract: An embodiment of the invention is a technique for enabling an emulator that emulates an e-mode program to utilize stored data items whose values are stored in native data format in native memory. The emulator fetches an item referenced by the e-mode program. The referenced item comprises a tag field and a data field. The emulator determines whether the tag field of the referenced item indicates that the referenced item is an external reference word (ERW). If the tag field of the referenced item indicates that the referenced item is an ERW, the emulator decodes the ERW to obtain a data type and a pointer. The pointer corresponds to a location of a stored data item in native memory.

Abstract: A method and apparatus for receiving persistent data into a running system. Metadata comprising a description of the known and/or unknown data model structure of the persistent data is used to establish a storage format and location for the persistent data, during runtime of the system. New transforms are created for data structures unknown to a running system.

Abstract: A technique is provided for exchanging data between software components in interface devices, monitoring devices, control devices, and so forth. Device elements are stored in the devices that are capable of communicating signals to one other, with each device element including a predetermined functionality. A connection is established between the device elements that facilitates event-based transfer of signals. A first of the device elements transfers data resulting from its functionality acting upon the received signals or the received signals themselves to a second device element. The transfer happens upon a receipt of the signals by the first device element. Each of the device elements made and act upon the signals in accordance with this respective functionality. The technique may used to cause interface elements to mirror one another.

Abstract: The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e.g., FPGA chips on slot module boards) for modeling at least a portion of one or more user design. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communicate with each other.

Abstract: A hard disk drive (HDD) emulator comprises a dynamic random access memory, a controller that refreshes content of the dynamic random access memory, and an input/output port coupled to the controller. The input/output port provides a hard disk drive interface. An operating system of a computing system in which the HDD emulator is installed uses the dynamic random access memory as a swap storage space.

Abstract: The invention relates to methods and systems for reconnecting a client and providing user authentication across a reliable and persistent communication session. A first protocol that encapsulates a plurality of secondary protocols is used to communicate over a network. A first protocol service, using the first protocol, provides session persistence and a reliable connection between a client and a host service. When there is a disruption in the network connection between a client and a host service, the connection is reestablished and the user's session with the host service is maintained through the connection being reestablished.

Abstract: An administrative computer sends keyboard commands over a network to control a remote computer. If the keyboard at the administrative and remote computers are different in key layout or language, a remote console software application permits the administrative computer to emulate the keyboard of the remote computer. The remote console application includes a graphical user interface through which the administrator can select the particular key layout and language to emulate for compatibility with the keyboard at the remote computer. The remote console application converts the key code for the key that was pressed at the administrative keyboard into a USB usage code that corresponds to a key on the remote keyboard. This usage code is encapsulated in an Ethernet packet and transmitted over the network to the remote computer. This Ethernet packet is decoded at the remote location and coupled to the remote computer over a USB bus.

Abstract: A product design support system comprises a product design support server (1), a product design support database (2) where parts information, parts image information, circuit information and circuit image information are stored, a communication network (3) and a designer terminal (4) connected via the communication network (3). The product design support server (1) allows a designer to specify a predetermined circuit from circuits stored in the product design support database (2). When the predetermined circuit is specified, the product design support server (1) transmits at least one of circuit information or circuit image information of the specified circuit to the designer terminal (4) via the communication network (3) to provide the designer with the transmitted information.

Abstract: Environment asset inventories of computing environment assets are arranged into computing environments, and at least one collector interface is disposed between the environments to detect movement of an asset and to produce asset movement reports. Upon receipt of a movement report, one or more backup copies of a environment asset inventory are accessed, and compared a modified environment asset inventory. A history of each asset in each inventory is maintained. A history report regarding the life of an asset from first introduction into an environment throughout movements between environments is produced, including any applicable patches and upgrades configured into an environment. A discrepancy report is generated including assets, locations, status, and a revision level indicators.

Abstract: A new and unique server having server core, storage interface I/O function, local area network interface I/O function that comprises remote graphic controller manageable emulated function (RMEF). The RMEF comprises circuitry capable of emulating a standard graphic controller to the server core so as to enable the core to generate video frames and circuitry capable of remotely delivering the video frames to remote management console application and other I/O interface functions. The functions can be implemented on a single chip.

Abstract: A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.

Abstract: The invention models software as a physical device with causality. It develops interaction between software and user in a software dynamic system that connects software or modeled software with a software controller. The software is modeled with its input/output behavior on a discrete sampling domain and is controlled by the controller in a modeling software dynamic system while its behavior is observed real-time to identify its model. The modeled software is controlled by the same controller in a simulation software dynamic system, which can be augmented programmatically. Augmentations integrated with the controller construct a software amplifier coupling the modeled software and user interactively and automatically. The modeled software represents domain knowledge simulated in the augmented system as software intelligence. A software-2 including the modeled software, the software controller, and augmentations is created.

Abstract: A method, apparatus and program product are provided for increasing the usable memory capacity of a logic simulation hardware emulator. The present invention performs an additional logic synthesis operation during model build to transform an original logical array within a logic model into a transformed logical array, such that a row within the transformed logical array includes a plurality of merged logical array rows from the original logical array. The invention further modifies read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: A virtual computer system includes multiple timer emulators for emulating multiple virtual timers in a virtual machine (VM). A time coordinator keeps track of an apparent time that is provided to the multiple timer emulators for presentation to the VM through the virtual timers. In particular, the time coordinator ensures that timer events generated by the multiple timer emulators are presented to the VM in an appropriate sequence and with substantially appropriate relative apparent times. Also, when guest software reads a count from a virtual timer, the time coordinator ensures that the apparent time presented to the guest software is substantially consistent with the apparent times represented by preceding and succeeding timer events. When the apparent time falls behind the real time of the physical computer system, the time coordinator speeds up the apparent time until it catches up to the real time.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for recovering data from a signal generator using a native communication channel and an emulated communication channel coupled in parallel to the native communication channel.

Abstract: A portable distributed application framework that uses a definition file describing a structure of data and commands to be used by the framework to interface with an application. A proxy, responsive to a definition file, creates and receives messages based on the definition file. The created messages contain data and commands used to control the application while the received messages contain data from the application. A control, responsive to the definition file, relays messages between the proxy and the application. A housing, responsive to the definition file and the messages from the proxy, provides the application with configuration information and receives data from the application.

Abstract: In one embodiment, a distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot pull command designating the first node. The first node does not participate in the simulation responsive to the hot pull command. In another embodiment, A distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot plug command designating the first node. The first node does not participate in the simulation prior to the hot plug command. Additionally, the first node begins participation in the simulation responsive to the hot plug command.

Abstract: A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.

Abstract: A system and method for developing an application is disclosed. The application is for use with point of sale equipment having a device. The application is capable of utilizing the device when the application is executed on the point of sale equipment. The method and system include providing an emulation module corresponding to the device. The method and system further includes ensuring that the application will utilize the emulation module when the application is executed on the development system. Thus, when the application is executed on the system, the emulation module and the application emulate the interaction between the application and the device that occurs when the application is executed on the point of sale equipment.

Abstract: A method is provided in a server, having a first operating system (Windows) and a second operating system (MCP), to allow both environments to share the same resilient and redundant benefits provided by the Fibre Channel storage systems with multi-path capabilities and to ensure that MCP formatted disk units in a virtualized environment in the first operating system will only receive and accept MCP formatted data from the second.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A method of separating a function of the business logic of an application from a user interface of the application where the business logic and user interface of the application are intermingled is provided. The method includes providing a wrapper interface for the application. The method also includes providing a function of the business logic of the application separated from the user interface of the application through the wrapper interface.

Abstract: A method allows communication within a network. The method includes the steps of: transmitting data packet as a broadcast signal (107) from a first application node (105) of a first subnetwork (101) to a first gateway node (103) of the first subnetwork (101); transmitting the data packet as a point-to-point signal (108) from the first gateway node (103) to a second gateway node (104) of a second subnetwork (102); and transmitting the data packet as a broadcast signal (109) from the second gateway node (104) of the second subnetwork (102) to at least one application node (106) of the second subnetwork (102).

Abstract: Method and system for testing an Application Specific Integrated Circuit is provided. The system includes, a simulator that interfaces with a host computer emulation module; and a virtual interface driver (“VID”) that interfaces with the host computer emulation module and a bus interface module, wherein the VID maps plural stimulus to the simulator via the bus interface module. The method includes, loading a bus functional module in an ASIC simulator; determining configuration of devices supported by a host emulation system; and mapping configuration information to the host emulation system, wherein a virtual interface driver maps the configuration information to the host emulation system.

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads a selected image associated with a desired input/output technology prior to runtime. The selected image identifies an appropriate output driver supply voltage, and any auxiliary voltages are controlled as functions of the output driver supply voltage to limit voltage inconsistencies. Defaulting each voltage to its least dangerous state when unprogrammed, the target interface system subsequently monitors the voltages, disabling the input/output connections if a problem is detected. The target interface system likewise detects when a selected system component is absent, unpowered, and/or wrongly powered and provides contention detection.

Abstract: The present invention enhances the Direct Access Stimulus (DAS) interface presently employed within a logic simulation hardware emulator to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator. The present invention accomplishes this by introducing a set of special logic within the logic model to provide an alternate source for selected signals, identifies the special logic so that it is subsequently connected directly to the DAS card interface, and adds information to a symbol table so that this special logic can be identified as signal accessible through the DAS card interface. At runtime, when the user control program accesses facilities that have been connected to the DAS card interface, a set of special routines automatically reference the symbol table information to access the special logic that is connected to the DAS card interface.

Abstract: A computer-readable medium stores a program which, when executed by a computer, causes the computer to execute functions including an extraction operation of extracting a sequence of character strings that are arranged in order of transitions and indicate meanings of transition conditions of transition branches that are taken to reach each transition state starting from an initial state from a finite state machine model of a hardware module which is a check subject; a generation operation of generating message information which means transitions that are taken to reach each transition state starting from the initial state by burying the sequence of character strings extracted by the extraction operation at a burying position for a partial character string which is part of a character string indicating each state of the finite state machine model; and an output operation of outputting the message information generated by the generation operation.

Abstract: A method is provided for developing an architecture model for a system-of-systems (SoS) that includes n system levels L1 . . . Ln, each of which includes at least one component of the SoS. For at least i>1, each system level Li includes at least one component of level Li-1. The method includes developing an architecture model for at least one level of the SoS. For at least i>1, the level Li-1 architecture model can be developed by developing a functional architecture model for level Li-1, and thereafter transforming the level Li-1 functional architecture model into a physical architecture model for level Li-1. The functional architecture model includes a functional and a logical structure for level Li-1. And as such, the functional architecture model is developed based upon a concurrent functional and logical decomposition of a functional architecture model developed for level Li.

Abstract: Provided are an apparatus and method for modeling and analyzing a network simulation for a salable simulation framework (SSF)-based network simulation package. A system logic set is generated and a network simulation modeling suitable for a predetermined network application is formed according to the system logic set. The network simulation modeling is transmitted to a predetermined network simulation package that performs simulation. Statistical information is generated based on the result according to the system logic set. Complicated network simulation modeling errors can be minimized, and remodeling of the network simulation modeling can be reduced.

Abstract: A method for flexibly defining communication constructs includes providing at least one communication element type for at least one layer of a generalized communication model, such as a bus model. Each communication element type has a user-definable structure that is adaptable for representing a corresponding protocol layer of a target communication medium. Users can define specific communication element types to substantially represent the target protocol. Users can also define the communication element types to depart from the target protocol in precisely defined ways.

Abstract: Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

Abstract: A vehicle control apparatus comprises: a computer operable to execute a control program, a first memory storing the control program, and a second memory storing the produced data. The control program includes: a platform program for inputting data from a hardware device and storing inputted data as first data in a first section of the second memory, an application program for processing for a vehicle control in accordance with an AP interface, and a coupling processing program. The coupling processing program performs mediation in the processing using the application program by converting the first data provided from the processing using the platform program to second data in accordance with the PF interface so that the second data is adapted to the AP interface. The application program executes vehicle control by using the second data. The platform program performs an operation at different predetermined intervals than the coupling program.

Abstract: A channel emulating device includes a first choosing module, a first signal integrating module, a first parameter adjusting module, a second choosing module, a second signal integrating module, a second parameter adjusting module and a third choosing module. The first signal integrating module generates at least one first integrated signal in accordance with a first input signal and at least one second input signal. The first and the second parameter adjusting modules respectively generate at least one first parameter signal and at least one second parameter signal. The second signal integrating module generates a plurality of second integrated signals in accordance with the first parameter signal and the second parameter signal. One of the second integrated signals acts as a first output signal.

Abstract: A system, and a corresponding method, provides time synchronized playback and control of dissimilar data in a simulation architecture. The system includes a master site including a controller, and agents, implemented by the controller, where the controller directs the agents to control simulation data logging and playback; simulation sites, including: one or more simulation computers, where simulation events occur, a computer, where the agents control the simulation site to record the simulation data, and a local log that stores the simulation data as events, where the agents control the test computer to replay the events; a time reference system including a master site time stamp, local time stamp pair for each of the simulation sites, each of the local time stamps related to a master time stamp, and one or more time normalization factors. The time normalization factors relate times recorded for each of the events to an earliest recorded event and to a time of initiation of a replay command.

Abstract: A virtual machine is instantiated on an M-core processor, and an N-core application is instantiated on the virtual machine such that the virtual machine emulates an N-core processor to the N-core application. Thus, the virtual machine hides difference between the N cores expected by the application and the M cores available from the processor.

Abstract: Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

Abstract: The present invention pertains to the field of electronic design automation (EDA). More particularly, this invention relates to using coherent state among multiple simulation models within an EDA simulation environment. Two related inventions are described. One invention selectively activates certain simulation domains in an electronic design automation (EDA) simulation environment at various times during the simulation of a circuit design and maintains timing synchronization among the various domains. The other invention makes state information accessible to simulation models in an EDA simulation environment without the necessity of simulating data transfers in the simulated circuit design. In various embodiments, the inventions increase efficiency and versatility of a simulation environment.

Abstract: A method provides a demonstration capability for a plurality of network coupled users by which many users can watch a primary user interact with an application. The method includes providing an application to a primary user from an application server over a network and translating output from the application into a broadcast protocol. The broadcast protocol is then translated into a browser protocol transmitted over a network for rendering by browsers at a plurality of network attached computers.

Abstract: The present invention provides a solution that unifies independent data sources into a single data source by hiding one of the data sources in metadata. The non-hidden source, which can reference the hidden source, can be processed by a primary XML processing agent. This agent can initially ignore syntax and semantics of content associated with the hidden source, which is contained within the metadata. A secondary XML processing agent can transform the hidden source into a readable form, which is consumable by the primary processing agent. The primary XML processing agent can receive this readable form as a content stream. The primary XML processing agent can be unaware that the content stream originates from the unified source, which permits the unified source to represent multiple sources while preserving “rules” that typically prohibit multiple data types to be included in a single source.

Abstract: Hardware access is provided for an operating system by allocating a portion of firmware address space of a data processing arrangement for use as a virtualized data interface that emulates a first hardware device. The virtualized data interface is presented to the operating system. The operating system accesses the virtualized data interface using a standardized kernel component of the operating system adapted to interface with the first hardware device. Data is exchanged between the virtualized interface and a second hardware device based on accesses of the virtualized data interface by the operating system via the standardized kernel component.

Abstract: A hardware and software co-simulation method for non-blocking cache access mechanism verification is provided. The method is applied for cache access mechanism verification. First, at least one way buffer is added into the software modeling, then the hardware and software modeling are simulated. Wherein, the hardware modeling issues a trigger event for reading request when one ‘outstanding miss’ occurs. At this moment, the software modeling stores the data of the address to be accessed into a way buffer. When the hardware modeling obtains the data from the main memory, it issues a trigger event for reading completion, and causes for writing the data from the way buffer into the data memory of the software modeling. The verification result of the software simulation is compared with the verification result of the hardware simulation.

Abstract: An electronic device (120) includes: an input connector (121), including at least three address pins and plural data pins; a function chip (123), including address pins and data pins corresponding to those of the input connector, and directly connected to the input connector by the data pins thereof; an adder disposed between the input connector and the function chip, and including at least three input pins and at least three output pins, the input pins being connected to the address pins of the input connector of the electronic device in one-to-one correspondence, the output pins being connected to the address pins of the function chip; and an output connector (124), including at least three address pins and plural data pins, the address pins being connected to the output pins of the adder in one-to-one correspondence, the data pins being respectively connected to the data pins of the input connector.