Of Electrical Device Or System Patents (Class 703/4)
  • Patent number: 6324493
    Abstract: A so-called multipole decomposition is employed for modeling the charge and current distributions and the interactions of those distributions in metalization sub units arising from electrical signals in those metalization sub units. Specifically, a variable interaction range meshing, i.e., multipole, decomposition process is advantageously employed to model the charge and current distributions of metalization sub units. These distributions are then employed to obtain electrical characteristics of an overall physical metalization structure to be fabricated. In an embodiment of this invention, representative sections of metalization sub units are selected such as straight sections of infinitesimal length, right angle bends and intersections, and solved for the local short range charge and current interactions that determine their local distributions in those sub units.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: November 27, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Nathan R. Belk
  • Patent number: 6314390
    Abstract: A method of determining a set of parameters for modeling an active semiconductor device in which current flow through a channel or other area is regulated by voltage applied to the device terminals, for example, MOSFETs. The method comprises first providing a plurality of measured values for current as a function of voltage for a plurality of active semiconductor devices of differing geometries. There is then determined an initial population of vectors comprising individual values representing a plurality of desired active semiconductor device model parameters. Fitness is then evaluated for each of the vectors by comparing calculated values for current as a function of voltage from the population to the plurality of measured values for current as a function of voltage of the vectors, converting any current differences to voltage errors and adding any such voltage errors together to arrive at a fitness value for each vector.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Calvin J. Bittner, James P. Hoffmann, Josef S. Watts
  • Patent number: 6304834
    Abstract: A semiconductor device simulator having a grid generator, a quasi-Fermi potential setting unit, a bias setting unit, a coefficient matrix and residual vector setting unit and a matrix calculator is disclosed. A grid generator defines a finite number of grid points inside and around a semiconductor device, and generates a plurality of grids. A quasi-Fermi potential setting unit sets said linear quasi-Fermi potentials, which is linearly changing, at each section inside the generated grid. A bias setting unit defines the terminal bias to be applied to predetermined electrode regions. A coefficient matrix and residual vector setting unit obtains carrier concentration inside each grid from the quasi-Fermi potential, and sets coefficient matrix/residual vector for the basic equations. A matrix calculator calculates this coefficient matrix, and accordingly obtains the solution for the Poisson's equation and the carrier continuity equations to obtain the device behavior.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: October 16, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Enda
  • Patent number: 6301552
    Abstract: A radar target simulator outputs multiple video and timing signals for a selected radar type from a single computer bus card slot. Several targets including cluster targets may be simulated at conveniently selectable signal-to-noise ratios. Multiple radar types may be simulated concurrently using additional bus card slots in a single desktop computer.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: October 9, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Aldan D. Gomez, Weldon J. Dahlke, David B. Schmiedeberg, Dwight R. Wilcox, Peter N. Pham
  • Patent number: 6289295
    Abstract: An integrated circuit device (10) comprising a conductor (11) for receiving a scan data signal. The integrated circuit device further comprises a plurality of storage circuit devices (SC1 through SC4), and each of those storage circuits has a data input and a data output. A first (SC1) of the plurality of storage circuit devices is coupled to receive the scan data signal at its data input. Moreover, each of the plurality of storage circuit devices other than the first of the plurality of storage circuit devices is coupled to receive at its data input a scan data bit as output from another one of the plurality of storage circuit devices as part of the scan data signal, thereby forming a clocked scan path through the integrated circuit device. The integrated circuit device further comprises a scannable multiplexer circuit (14) having an output (24) coupled to a data input of one (e.g., SC1) of the plurality of storage circuits.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: September 11, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Anthony M. Hill
  • Patent number: 6285957
    Abstract: An apparatus and method are provided to calculate the strength of an electromagnetic field radiated from an electric device according to a moment method, wherein the moment method is based on integral equations derived from electromagnetic equations. The apparatus and method include a setting unit to interactively set a name of a two-wire cable arranged in the electric device and coordinates of the two-wire cable at a cable inlet, a cable outlet, and way points in the electric device, the way points being prepared as and when required to bend the two-wire cable between the cable inlet and the cable outlet. Further, the apparatus and method include library unit corresponding to cable names, respectively, and storing attributes of a corresponding cable comprising of the name, type, characteristic impedance, and structural data of the two-wire cable.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: September 4, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshirou Tanaka, Shinichi Ohtsu, Makoto Mukai
  • Patent number: 6247010
    Abstract: A system according to the present invention searches for information related to entered text and presents searched information to a user with a minimum interruption to user's document formulating work. An input analyzing module 11 analyzes text entered by the user and extracts a search key. A related information searching module 12 searches a related information storage device 3 for information on the search key. A storage module 16 stores therein the search results collected for a plurality of past search keys including the latest search key and the positional information on each search key within a document. A controlling module 13 searches the storage module 16 for the search key corresponding to the position of a cursor. The controlling module issues an instruction to change a search button to a first display format if there is no related information, or an instruction to change the search button to a second display format if there is related information.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: June 12, 2001
    Assignee: NEC Corporation
    Inventors: Shinichi Doi, Shinichiro Kamei, Shinko Tamura
  • Patent number: 6246973
    Abstract: The objective is to accurately determine the effective value of channel width in accordance with the design value of channel width when the channel width is scaled down, thereby accurately modeling the electrical characteristic of a MOSFET. An error &Dgr;W1 based on the length of the region extending from the field oxide film to the gate oxide film, an error &Dgr;W2 based on the “effect of stress” that occurs when the design value W of channel width is scaled down, and an error &Dgr;W3 based on the “effect of lithography” that occurs when the design value L of channel length is scaled down, are predetermined with respect to various values of W and L, and the effective value We of channel width is determined according to an equation: We=W−&Dgr;W1+&Dgr;W2+&Dgr;W3. The resulting effective value We is used to model the electrical characteristic of the device.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: June 12, 2001
    Assignee: Motorola, Inc.
    Inventor: Satoshi Sekine
  • Patent number: 6236956
    Abstract: The Model Editor (106) makes simulation modeling easier and more intuitive by extracting essential information and presenting it to the user, and by providing tools to investigate simulation and model robustness, in an interactive, graphical environment. The Model Editor (106) includes a Newton step manager as an interactive, graphical tool. During simulation of a model, the Newton step manager captures matrix norms. Any indications of Newton limiting are also captured. The matrix norms are plotted as a function of iteration count, and the iterations at which Newton limiting were encountered are identified. Newton step manager can also be run automatically using a functional dependency analysis.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: May 22, 2001
    Assignee: Avant! Corporation
    Inventors: H. Alan Mantooth, Douglas K. Cooper, Martin Vlach
  • Patent number: 6219629
    Abstract: A simulator apparatus for a combined simulation of electromagnetic wave analysis and circuit analysis, which is configured to produce stable solutions with a smaller amount of processing loads. An electromagnetic wave analyzer calculates magnetic field at a simulation time tem01 and then electric field at another simulation time tem02 thereby performing a transient analysis of electromagnetic waves. A circuit analyzer solves the given circuit equation at still another simulation time tcs that is incremented by a variable time step size &Dgr;tcs determined in accordance with the circumstances. A current source data transfer unit compares tem01 and tcs, and if their difference falls below a time difference threshold &lgr;1, it calculates current source data for the equivalent circuit, based on the magnetic field obtained by the electromagnetic wave analyzer. The current source data transfer unit then transfers the resultant current source data to the circuit analyzer.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventor: Takefumi Namiki
  • Patent number: 6219631
    Abstract: A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: April 17, 2001
    Assignee: Ingenuus Corporation
    Inventors: Soo-Young Oh, Won-Young Jung
  • Patent number: 6216100
    Abstract: A method for the simulation of responses of a nonlinear amplifier provides for measuring characteristics of nonlinearity of amplitude and of amplitude/phase-shift conversion of the amplifier, each measurement being made at an amplitude that is constant in input. The method further includes measuring the characteristics at different frequencies, developing the characteristics in sequences of direct transfer functions, computing frequency correctors for the direct transfer functions, measuring characteristics of distortion of amplitude modulation, each measurement being performed by modulating the input amplitude, computing modulation transfer functions reproducing the distortion amplitudes at output according to the input modulation amplitudes and correcting the direct transfer functions when the input amplitude is modulated in order to simulate the envelope memory effect. There is a direct application of the invention to the field of the simulation of high efficiency microwave amplification.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: April 10, 2001
    Assignee: France Telecom SA
    Inventors: Vahid Meghdadi, Jean-Pierre Cances, François-René Chevallier, Jean-Michel Dumas
  • Patent number: 6199032
    Abstract: A computer software program simulates a communication network using network characteristic information provided by communication network designers. When a network designer selects a particular location within the network, the software consults the network characteristic information to predict a signal attribute of a simulated signal received at the selected location. The predicted attribute is used to modify a template signal to produce a simulated output signal, and the simulated output signal is presented for consideration by the network designers.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: March 6, 2001
    Assignee: EDX Engineering, Inc.
    Inventor: Harry R. Anderson
  • Patent number: 6185517
    Abstract: An electromagnetic field intensity computing apparatus for computing electromagnetic field intensity of an electric circuit device in a moment method obtains according to the electric current distribution an electric current of a ground layer and models a transmission line, ground layer, dielectric portion, etc. to be analyzed. When a plate to be analyzed is divided into a plurality of patches, the regularity in given structure data is automatically extracted to compute the mutual impedance among a portion of patches and apply the computation result to other portions. When elements to be analyzed meet the conditions that the electric length of the elements is short and the elements are distant from each other, the mutual impedance can be computed in an approximation obtained under various conditions. Furthermore, approximating a portion near a pigtail portion of a coaxial cable using a polygon allows a vertical electric current to be properly connected to each unit.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Shinichi Ohtsu, Makoto Mukai
  • Patent number: 6175815
    Abstract: A method for efficiently storing quantities used by the Fast Multipole Method (FMM) to perform field calculations is disclosed. This method takes advantage of the level structure used by the FMM. The disclosed method selects a particular level and, for each group in that level, calculates interactions with all far groups. The disclosed method does not repeat calculations for interaction of a similar distance for the same level. Rather, it references calculations previously made for the similar interaction, thereby eliminating the calculation and storage of information that is the same as information previously calculated and stored.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: January 16, 2001
    Assignee: Hughes Electronics Corporation
    Inventor: Mark A. Stalzer
  • Patent number: 6167363
    Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: December 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Warren G. Stapleton
  • Patent number: 6163762
    Abstract: Conformal meshing is a technique for selecting basis functions such that an accurate representation of the actual current distribution is realized with only a few subsections. This invention relates to conformal meshing, which allows a circuit to be analyzed with an error corresponding to a very small cell size while maintaining the speed normally seen when using a large cell size. Conformal meshing in accordance with this invention bends the subsection to fit the edge of the metal. The current distribution in the subsection is also modified by the introduction of strings, as will be described in more detail later, to accurately represent the high edge current caused by the edge effect. This represents a considerable improvement over existing meshing techniques.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: December 19, 2000
    Assignee: Sonnet Software, Inc.
    Inventor: James C. Rautio
  • Patent number: 6144929
    Abstract: A method of simulating an impact ionization phenomenon of a semiconductor device, by which an electric characteristic concerning the impact ionization phenomenon of the semiconductor device is obtained by setting a mesh in a space and by solving a Poisson equation, an electron current continuity equation and a hole current continuity equation which are discretized by what is called a control volume method. Further, regarding a current density defined on a mesh edge connecting adjacent mesh points, different values are used as an evaluation value of the current density at an upstream side, at which a carrier is cased to drift, and an evaluation value of the current density at a downstream side, respectively.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: November 7, 2000
    Assignee: NEC Corporation
    Inventor: Shigetaka Kumashiro
  • Patent number: 6141632
    Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: George E. Smith, III, Fariborz Assaderaghi, Paul D. Muench, Lawrence F. Wagner, Jr., Timothy L. Walters
  • Patent number: 6138267
    Abstract: A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: October 24, 2000
    Assignee: NEC Corporation
    Inventor: Syuzo Murai
  • Patent number: 6106563
    Abstract: A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure (410). These network parameters are processed to obtain model parameters that characterize each pure mode response (422, 424, 426, 428, 432, 434, 436, 438). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values (440, 450).
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: August 22, 2000
    Assignee: Motorola, Inc.
    Inventors: Robert E.. Stengel, David E. Bockelman, Lei Zhao
  • Patent number: 6086618
    Abstract: A method for developing system resource usage "cost" equations, creating models based upon such cost equations, and estimating total system resource usage and computer program product incorporating such cost equations. A server application is analyzed and certain transactions are defined therein that occur in response to interaction with a client application that in many instances originates from user behavior. System resources are also identified and resource usage measurements are determined for each transaction. One way of determining the resource usage measurements is by creating a load of a particular transaction on an "instrumented" server application and measuring the resources used in connection with the transaction. Cost equations for each type of system resource can then be constructed taking a component from each transaction that uses a particular system resource so that the cost equations are defined in terms of transactions.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: July 11, 2000
    Assignee: Microsoft Corporation
    Inventors: Hilal Al-Hilali, Perry Clarke, David Edward Guimbellot, David Andrew Howell
  • Patent number: 6083266
    Abstract: A simulation apparatus for simulating the current flowing through elements of an electronic apparatus using the moment method based on reaction matching and able to achieve high speed simulation processing, comprising a segmenting means for segmenting the electronic apparatus to be analyzed into elements, a calculating means for calculating a mutual impedance between segmented elements of the electronic apparatus, assuming that a triangle function current flows through the monopoles, by using an approximation equation of the mutual impedance between monopoles, expressed by a polynomial of the power of k, derived by exp(-jkr) which is approximated by multiplication of exp(-jkr.sub.0) and a Taylor expansion of exp[-jk(r-r.sub.0)] (where j is an imaginary number, k is a wave number, r is the distance between monopoles, and r.sub.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: July 4, 2000
    Assignee: Fujitsu Limited
    Inventors: Shinichi Ohtsu, Makoto Mukai