Abstract: One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.

Abstract: The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.

Abstract: Methods and apparatus are provided for predicting the number of iterations needed for a computed Transversal Waveform Relaxation solution to achieve a given level of accuracy. In this manner, a Transversal Waveform Relaxation algorithm is disclosed that provides full automation. According to one aspect of the invention, a circuit is analyzed having transmission lines. One or more transmission line parameters of the circuit are obtained, as well as the intrinsic behavior, E(?), and strength of coupling, N(?), of each of the transmission lines. In addition, a relative error bound is obtained for the circuit based on the intrinsic behavior, E(?), and strength of coupling, N(?), of the transmission lines and a predefined error threshold. The process then iterates until the relative error bound satisfies the error threshold.

Abstract: A system and method for modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. More particularly, a system and method of modeling device across chip variations and device mismatch. The method includes modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. The method includes providing a system of N similar statistical variables, wherein each stochastic variable has a same standard deviation. The method further includes partially correlating each and every pair of stochastic variables among N variables, wherein a degree of partial correlation is a same for all pairs of variables. A statistical model is constructed to represent a system of N stochastic variables in which only N independent stochastic model parameters are used. A one-to-one mapping relation exists between N model parameters and the N variables.

Abstract: An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock pin of the PS/2 interface. The LEDs coupled to the micro controller unit simulate functions of a keyboard. A related method for testing the PS/2 interface is also provided.

Abstract: A simulating circuit for simulating a toggle magnetic tunneling junction (MTJ) element includes at least a synthetic Anti-Ferromagnetic free layer, a tunnel barrier layer, and a synthetic Anti-Ferromagnetic pinned layer. The simulating circuit is configured with a converting circuit, a status circuit, a storage circuit, a voltage computing circuit and a feature simulating circuit. The convert circuit converts the magnetic filed generated from a write in current to an equivalent voltage. The status circuit indicates the flipping status of the magnetic moment of the free layer. The storage circuit is used for representing data stored in the toggle magnetic tunneling junction element. The arrangement of the magnetic moment of the two Anti-Ferromagnetic adjacent to the tunnel barrier layer is represented by the voltage computing circuit. The voltage-current characteristic is represented by the feature simulating circuit.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A technique is disclosed for generating markup information to be displayed on a client computer system. The client system includes memory configured to store at least one update file which comprises keyword information relating to keywords suitable for markup. In one implementation, the update file is generated at a remote server system and downloaded to the client system. When a new document (e.g. a web page) is displayed on the client system to an end user, selected context associated from the document is analyzed for selected keywords. In a specific implementation, the selected keyword information is provided by an entity other than the end user. Using the selected keyword information, specific context in the document is selected to be marked up. According to a specific embodiment, the selection of the document context to be marked up may be performed at the client system.

Abstract: A non-linear transient analysis module and method for phase locked loop (PLL) is disclosed. The method includes a pulse cycle defined by the larger period of two input frequencies; a pulse width defined by the accumulation value of period difference. Each pulse cycle is divided into two linear regions, a first voltage at the beginning of the pulse cycle as an initial value then applying a first linear equation to obtain a second voltage, and then the second voltage as an initial value then applying a second linear equation to obtain a third voltage which is used to be an initial value for next pulse cycle. An average voltage of the first region and the second region is inputted into the VCO to generate an output as the PFD input. The aforementioned steps are repeated to complete a simulation of PLL transient response.

Abstract: A method for simulating an effect of at least one electrical/electronic load includes: providing a controllable power supply unit that is connected to at least one terminal of a control unit; and simulating a first current theoretically flowing through a simulated load at the at least one terminal by drawing a second current from the control unit by the controllable power supply unit or impressing a third current on the control unit by the controllable power supply unit.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (?1) and the substrate is a second dielectric with a second permittivity (?2). The method models the capacitance (C1) for values of the first and second permittivity (?1, ?2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (?1) and a different second permittivity (?2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

Abstract: The invention provides a device for simulating a multi-antenna radio channel, a module and a method. The device comprises channel modules for incorporating propagation effects into channel signals which represent radio signals propagating along propagation paths, which channel modules are electrically connected to neighbour channel modules for forming an (m,n) array configuration. The (m,n)th channel module is configured to receive a first (m,n?1)th channel signal and a second (m?1,n)th channel signal and comprises: a processing resource for processing the first (m,n?1)th channel signal according to a channel model, thus generating a processed (m,n)th channel signal, and a combiner for combining the processed (m,n)th signal and the second (m?1,n)th channel signal, thus generating a second (m,n)th channel signal. The (m,n)th channel module is further configured to output the second (m,n)th channel signal.

Abstract: The response of linear and non-linear systems to an arbitrary pulse train is modeled for efficient and accurate circuit simulation. First, a harmonic balance analysis is performed for a system incorporating linear and non-linear components. Then, the even and odd frequency components of the harmonic balance result are separated and interpolated. Finally, the resulting interpolated components are combined to generate the frequency domain positive step response and the frequency domain negative step response of the system. These resulting frequency domain step responses are utilized to generate a low order pole/zero model of the step responses. The pole/zero model can then be used to efficiently and accurately model the response of the system to an arbitrary sequence of positive and negative going pulses.

Abstract: A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.

Abstract: Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement data is collected from a specific manufacturing environment and sorted by channel lengths. Then, an optimizer is used to generate customized modeling parameters based on the measurement data. The optimization processes is a multi-step process. First, a first set of modeling parameters is generated based on measurement data associated with a long channel length. Second, a second set of modeling parameters is generated based on the first set and on measurement data associated with a short channel length. Finally, the customized modeling parameters are generated based on both the first set and the second set. The customized modeling parameters are used to generate a customized compact device model representative of the specific manufacturing environment.

Abstract: In one embodiment, the present invention receives sensitivity data corresponding to a plurality of first sensor channels of a respective plurality of capacitive sensing devices and utilizes the sensitivity data to determine a range of expected variation pertaining to the plurality of first sensor channels. The range of expected variation has an upper and a lower limit. The present embodiment also relates the range of expected variation to a sensitivity value corresponding to one of the plurality of first sensor channels. The present embodiment determines at least one performance characteristic of the one of the plurality of first sensor channels near at least one of the upper limit and the lower limit. In this embodiment, the at least one performance characteristic enables the tuning of the plurality of first sensor channels of the respective plurality of capacitive sensing devices.

Abstract: An NSET method and apparatus for modeling and monitoring the status of a system is disclosed. The NSET employs a nonlinear similarity operator in place of linear matrix multiplication, to estimate a set of sensor data based on learned reference data, responsive to receiving a set of actual sensor data. Regularization is used in the generation of the estimate. The estimated data values and the actual sensor data are differenced to produce residuals, which are statistically tested with a SPRT to detect anomalies. Cluster centers may be used to represent learned reference data. The detection of anomalies can be used advantageously for sensor calibration verification.

Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.

Abstract: An online simulation system for a flexible AC transmission system (FACTS) which is capable of analyzing operation control effect of the FACTS in advance through an online data connection with a supervisory control and data acquisition (SCADA) system used for operating an electric power system.

Abstract: An apparatus and method for the identification of arcing phenomena in a faulted electrical network. By continually updating a model for the load on an electrical branch, an estimate of the behavior of that load may be calculated. Since electrical arcing faults result in a chaotic behavior that is difficult to describe, when arcing occurs, the model will be unable to adequately describe the arcing behavior and this inability indicates a fault condition, in response to which, power may be removed in full or in part from the faulted electrical network. In some embodiments, a current shunt is used to distinguish between source side and load side arcing. Some embodiments utilize a solid state switch as both current shunt and interruption means.

Abstract: The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the correspondence between engineering objects and runtime objects to be determined at object level and no information is lost as a result of the mapping. In addition, a direct communication between engineering and runtime objects can take place, which can be utilized when the method is carried out.

Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.

Abstract: A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

Abstract: A technique is disclosed for generating markup information to be displayed on a client computer system. The client system includes memory configured to store at least one update file which comprises keyword information relating to keywords suitable for markup. In one implementation, the update file is generated at a remote server system and downloaded to the client system. When a new document (e.g. a web page) is displayed on the client system to an end user, selected context associated from the document is analyzed for selected keywords. In a specific implementation, the selected keyword information is provided by an entity other than the end user. Using the selected keyword information, specific context in the document is selected to be marked up. According to a specific embodiment, the selection of the document context to be marked up may be performed at the client system.

Abstract: A system of finite state machines built with asynchronous or synchronous logic for controlling the flow of data through computational logic circuits programmed to accomplish a task specified by a user, having one finite state machine associated with each computational logic circuit, having each finite state machine accept data from either one or more predecessor finite state machines or from one or more sources outside the system and furnish data to one or more successor finite state machines or a recipient outside the system, excluding from consideration in determining a clock period for the system logic paths performing the task specified by the user, and providing a means for ensuring that each finite state machine allows sufficient time to elapse for the computational logic circuit associated with that finite state to perform its task.

Abstract: A non-linear test load is provided for calibrating a plasma system. The test load is a substrate for modeling the electrical characteristics of the plasma such that multi frequency testing can be performed in the absence of a plasma reaction. An exemplary substrate includes a first semiconductor junction for providing a non-linear response to the multi-frequency RF source provided from the anode. The first semiconductor junction exhibits a first capacitance for modeling a first plasma sheath of the anode. A plasma component is responsive to the first semiconductor junction and exhibits a resistance for modeling a resistance of the plasma, an inductance for modeling an inductance of the plasma, and a gap capacitance for modeling capacitance of the plasma.

Abstract: A system and method for authenticating and authorizing computer users with a single, standard, directory-based set of applications. The invention combines dynamic directory services (DDS) with a directory access protocol such as the light weight directory access protocol (LDAP) to provide authentication and application-authorization for secured networks, applications, and programs. Dynamic information such as session information or user ID numbers is stored in a directory each time a user logs into the systems and is maintained in the directory until the user logs out. While the information exists in the directory, it can be queried by other programs, applications, or networks that use a directory service to authenticate or authorize the user for the program, application, or network.

Abstract: In one embodiment, a method for designing a radiographic imaging system includes 1) receiving a number of design constraints for the system, and then 2) in response to the constraints, generating a plurality of radiographic imaging system designs, each having a different number of radiographic sources, and each requiring a different number of nominal scan passes to image a specimen region of interest. Designs having a greater number of radiographic sources have sets of translated radiographic detection areas sharing at least some coincident, nominal scan passes as compared to radiographic imaging system designs having fewer radiographic sources. Each set of translated radiographic detection areas is associated with a radiographic source that is replicated and translated with respect to a radiographic source that forms part of a radiographic imaging system design having fewer radiographic sources. Related systems and apparatus are also disclosed.

Abstract: A user of a computer aided design (CAD) system graphically places fire alarm appliances, such as smoke detectors and sirens, in a drawing area. After elements are placed and physical paths are determined, a series of electrical circuit connections between alarm source elements and alarm appliance elements are determined. Labels for alarm system device are automatically generated and automatically resequenced. Riser details may be generated in multiple formats. The system also allows standard CAD drawings to be imported into the alarm CAD system. This feature includes a gravitate command which automatically connects unconnected wire paths to the nearest alarm appliance. Circuit requirements can be listed with either a base unit, an appliance, or both. When both the base unit and the corresponding appliance have circuit requirements listed, the circuits are combined into a single listing.

Abstract: A computerized model provides a display of a physical environment in which a communications network is or will be installed. The communications network is comprised of several components, each of which are selected by the design engineer and which are represented in the display. Errors in the selection of certain selected components for the communications network are identified by their attributes or frequency characteristics as well as by their interconnection compatibility for a particular design. The effects of changes in frequency on component performance are modeled and the results are displayed to the design engineer. A bill of materials is automatically checked for faults and generated for the design system and provided to the design engineer. For ease of design, the design engineer can cluster several different preferred components into component kits, and then select these component kits for use in the design or deployment process.

Abstract: Pre-amplifier apparatus, for use for example in a home hi-fi system, compoosed of one or a plurality of reconfigurable circuits used to configure the apparatus to implement the desired audio processing functions and audio protocols for use in different audio systems. The reconfigurable circuits are configured and reconfigured in real time. The apparatus is also modular allowing expansion through the use of mezzanine and or PC cards, which contain, amongst other things, signal processing logic and programmable logic. All signal processing is performed in the digital domain so any analogue input signals are first converted to digital signals using an analogue to digital converter. Remote audio feedback to the apparatus allows the apparatus to adapt in real time to the desired acoustic settings.

Abstract: Detecting a collision of a three-dimensional model from three-dimensional data defining a bone includes obtaining a bounding volume for the bone, detecting a collision of the three-dimensional model with a second three-dimensional model using the bounding volume, and applying a collision response only to a colliding area of the three-dimensional model and the second-three-dimensional model.

Abstract: A method for determining the movement of particles, particularly impurities, in a medium, under the influence of a changing interface between two neighboring phases. In a first step, the temporal and/or local evolution of said interface is determined. In a second step, the movement of said particles in dependence of the temporal and/or local evolution of the phase interface as determined in the first step is calculated. Optionally, the distribution of the particles within the medium at a certain time is then determined.

Abstract: A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for timing and noise circuit simulations, particularly for deep sub-micron circuit design simulations. Briefly, a measurement of both total capacitance of a line and cross coupling capacitance between two lines is determined by applying predetermined voltage signals to specific circuit elements. The resulting current allows simple computation of total capacitance and cross coupling capacitance. Multiple cross coupling capacitance can be measured with a single device, thus improving the art of library generation, and the overall method is free of uncertainties related to transistor capacitance couplings.

Abstract: In order to simulate the input or output load of an analog circuit, the output of the analog circuit is connected to the input of a driver stage. A measuring element is placed between the input of the driver stage and the reference potential, in order to record the output voltage of the analog circuit. A digital simulator controls a controllable transfer impedance, arranged between the output of the driver stage and the reference potential, in order to simulate various output loads. An alternative is to connect the output of the driver stage to the input of the analog circuit. The input of the driver stage has a shunt connection of a controllable current or voltage source, a first resistance and a first capacitance. The digital simulator controls the controllable current or voltage source, in order to simulate various output loads. The driver stage is switched off when appropriate.

Abstract: An adaptive learning method for automated maintenance of a neural net model is provided. The neural net model is trained with an initial set of training data. Partial products of the trained model are stored. When new training data are available, the trained model is updated by using the stored partial products and the new training data to compute weights for the updated model.

Abstract: A system and method for performing rapid control prototyping using a plurality of graphical programs that share a single graphical user interface. A first graphical program may be created that models a product being designed. The first graphical program may be deployed on a target device for execution. A second graphical program that performs a measurement function may be created. The target device may be coupled to a physical system. The first graphical program may be executed on the target device to simulate operation of the product. The second graphical program may be executed to measure characteristics of the operation of the physical system and/or characteristics of the operation of the product. A single graphical user interface comprising a first one or more graphical user interface elements for the first graphical program and a second one or more graphical user interface elements for the second graphical program may be displayed.

Abstract: A process and method for projection beam lithography which utilizes an estimator, such as a Kalman filter to control electron beam placement. The Kalman filter receives predictive information from a model and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as wafer heating and beam drift. The process and method may also utilize an adaptive Kalman filter to control electron beam placement. The adaptive Kalman filter receives predictive information from a number of models and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as heating and beam drift. The Kalman filter may be implemented such that real-time process control may be achieved.

Abstract: According to an electric network simulating method, element cells representing electric functions of a plurality of circuit elements and connection pipes representing wiring lines for connecting the circuit elements are defined. A current is defined as the number of particles moving through the connection pipe per unit time, and a voltage is defined as the number of particles present in the connection pipe. A rule for expressing the electric function of each circuit element in accordance the state of the connection pipe is set beforehand in units of element cells. The particles are transferred between the element cell and the connection pipe in accordance with the rule. The state of the electric network is simulated in accordance with the number of particles passing through the connection pipe per unit time and the number of particles present in the connection pipe.

Abstract: A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.

Abstract: A technique is disclosed for sharing information between closely-related SAT instances (instances with a non-empty intersection between their sets of clauses), which enables a speed-up in the overall solution time. This technique is particularly effective in SAT-based bounded model checking (BMC), and in problems of planning and logistics.

Abstract: A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated circuits, comprises the steps of: estimating a representation of component mismatch from device performance measurements in a form suitable for circuit simulation; reducing the complexity of statistical simulation by performing a first level principal component or principal factor decomposition of global variation, including screening; further reducing the complexity of statistical simulation by performing a second level principal component decomposition including screening for each factor retained in the first level principal component decomposition step to represent local mismatch; and performing statistical simulation with the joint representation of global variation and local mismatch obtained in the second level principal component decomposition step.

Abstract: A multimedia object retrieval and annotation system integrates an annotation process with object retrieval and relevance feedback processes. The annotation process annotates multimedia objects, such as digital images, with semantically relevant keywords. The annotation process is performed in background, hidden from the user, as the user conducts normal searches. The annotation process is “semi-automatic” in that it utilizes both keyword-based information retrieval and content-based image retrieval techniques to automatically search for multimedia objects, and then encourages users to provide feedback on the retrieved objects. The user identifies objects as either relevant or irrelevant to the query keywords and based on this feedback, the system automatically annotates the objects with semantically relevant keywords and/or updates associations between the keywords and objects. As the retrieval-feedback-annotation cycle is repeated, the annotation coverage and accuracy of future searches continues to improve.

Abstract: A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.

Abstract: In the simulation of an analog and mixed-signal analog-digital physical circuit, events are assigned scheduled times. The events are stored in buckets in a hash table, with the scheduled times of the events in each bucket associated with the bucket. The scheduled times are organized into a heap, with the earliest scheduled time at the root of the heap. The earliest scheduled time is removed from the heap, and the events in the associated bucket are performed. Performing the scheduled events can cause new events to be scheduled, and existing events to be de-scheduled. When all the events in the bucket associated with the earliest scheduled time are simulated, the remaining scheduled times are re-organized into a new heap, and the steps of removing the earliest scheduled time, performing the scheduled events, and re-organizing the remaining scheduled times are repeated.

Abstract: A software tool is created to migrate computer files that define ICs from older to newer computer-readable directory structures. The old and new directories are compared to identify differences that are mapped and sorted on the basis of directory source names. A computer file defining an IC is migrated by identifying source names in the file that are referenced by the tool. For each identified source name, the associated directory reference is changed from the old to the new directory structure.

Abstract: A method is described for reducing delays in an analogue simulation model of a hardware circuit. The method includes the steps of stimulating via an input an output of said analog model, said output and said input having a relatively high resistance therebetween and applying a pulse to a relatively low resistance, whereby when said pulse is applied to the relatively low resistance, the input is connected to said output via the relatively low resistance so that the time constant of the circuit is reduced.

Abstract: The value of a constraint parameter for a given combination of circuit parameters is estimated based on any prior computed values for other combinations of circuit parameters. As the estimate may be close to the actual value of the constraint parameter, a search may be performed (e.g., using simulation) in a narrow search range around the estimated value. As a result, the constraint parameters at different combinations of circuit parameters may be measured quickly. According to another aspect of the present invention, a curve is generated based on the results of multiple search points (with at least one point generating a pass result and another one point generating a fail result), and searches may be conducted between the pass and fail points by first checking whether the delay corresponding to intermediate points on the curve is lower than a desired threshold value.