Of Electrical Device Or System Patents (Class 703/4)
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Patent number: 8032338Abstract: A computer-implemented method for the design of a power supply is disclosed. Multiple lists of power supply design variables are provided. The method includes simulating a first power supply design in response to power supply design variables selected from these multiple lists of variables. The method then calculates a score of the first power supply design and determines whether the score is better than the score of any power supply design included in a set of power supply designs. If so, the method replaces a power supply design having a worst score from the set of power supply designs with the first power supply design.Type: GrantFiled: June 13, 2008Date of Patent: October 4, 2011Assignee: Power Integrations, Inc.Inventors: Arkady Akselrod, Sameer Kelkar, Timothy E. W. Starr
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Patent number: 8032848Abstract: Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.Type: GrantFiled: January 29, 2009Date of Patent: October 4, 2011Assignee: Synopsys, Inc.Inventor: In-Ho Moon
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Publication number: 20110238393Abstract: In one embodiment, a SPICE model parameter output apparatus is configured to output a SPICE model parameter of a high-frequency or analog MOSFET for a simulation of a semiconductor circuit. The apparatus includes a data input part to input shape data of the MOSFET and measurement data on frequency characteristics of the MOSFET. The apparatus further includes a substrate resistance calculating part configured to calculate a substrate resistance of a one-terminal substrate resistance model regarding the MOSFET, based on the measurement data. The apparatus further includes a SPICE model parameter output part configured to calculate the SPICE model parameter, based on the substrate resistance of the one-terminal substrate resistance model and the shape data, to output the calculated SPICE model parameter.Type: ApplicationFiled: September 21, 2010Publication date: September 29, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Sadayuki YOSHITOMI, Naoki Wakita, Fumie Fujii, Yuka ITANO
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Patent number: 8010333Abstract: Process for developing and implementing a model (ASM) for the formal description of a collaborative system including multiple, distributed components, wherein analyzable models of the components are generated via simulation processes. The invention includes the steps of generation of models of collaborative units, preparation of a catalog of models of the collaborative units, assignment of a set of rules to the catalog for the specification of interactions among the autonomous models of the collaborative units and for the development of the model of the complex collaborative system, generation of the desired model using selected models of the collaborative units as the basic module from the catalog, and taking selected rules into account, and automatic adaptation of the model by deriving new rules, taking into account evaluation parameters for each application in one process operation.Type: GrantFiled: November 19, 2004Date of Patent: August 30, 2011Assignee: Schneider Electric GmbHInventors: Armando Walter Colombo, Ronald Schoop
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Patent number: 7990374Abstract: The invention provides methods for leveraging data in the graphics pipeline of a 3D graphics application for use in a haptic rendering of a virtual environment. The invention provides methods for repurposing graphical information for haptic rendering. Thus, at least part of the work that would have been performed by a haptic rendering process to provide touch feedback to a user is obviated by work performed by the graphical rendering process.Type: GrantFiled: June 28, 2005Date of Patent: August 2, 2011Assignee: SensABLE Technologies, Inc.Inventors: Brandon D. Itkowitz, Loren C. Shih, Marc Douglass Midura, Joshua E. Handley, William Alexander Goodwin
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Patent number: 7984354Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.Type: GrantFiled: June 29, 2009Date of Patent: July 19, 2011Assignee: Mentor Graphics CorporationInventors: Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
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Publication number: 20110172979Abstract: A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.Type: ApplicationFiled: January 11, 2010Publication date: July 14, 2011Applicant: International Business Machines CorporationInventors: Aditya Bansal, Pamela Castalino, Dallas M. Lea, Amith Singhee
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Patent number: 7979815Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.Type: GrantFiled: January 8, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha
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Patent number: 7975198Abstract: A test system for performing a test of a device is provided that comprises a source file of a test plan that describes a program for performing a test, and one or more of elements that are formed in a unit that divides the source file into one or more blocks. The test system further comprises an annotatable object that, when debugging of objects of the source file is performed, manages modification details of the debugging with reference to an element corresponding to a portion where the debugging is performed, and a controller that, after the debugging, rewrites the source file with details after the debugging is performed on an element basis based on the element and the annotatable object.Type: GrantFiled: March 19, 2009Date of Patent: July 5, 2011Assignee: Advantest CorporationInventor: Masaru Yokoyama
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Patent number: 7970482Abstract: A method and system for process control using a model predictive controller. The control system can have one or more control devices operably coupled to a processing system for controlling a process of the processing system; a modeling tool to provide a non-linear model based at least in part on the process and to provide a plurality of linearized models based at least in part on the non-linear model, where the plurality of linearized models are linearized at different linearization rates; and a controller operably coupled to the modeling tool. The controller can select one of the plurality of linearized models based on a comparison of the plurality of linearized models with a reference model. The controller can send one or more control signals to at least one of the one or more control devices. The one or more control signals can be determined using the selected one of the plurality of linearized models.Type: GrantFiled: August 9, 2007Date of Patent: June 28, 2011Assignee: Honeywell International Inc.Inventors: Ranganathan Srinivasan, J. Ward MacArthur
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Patent number: 7962317Abstract: A method and apparatus may linearize a model representing a dynamic system without using perturbation techniques. The model may include a differential-algebraic system of equations to represent the dynamic system. The mass matrix of the model may be singular. The linear model of the system may be generated in a state-space representation using the analytic Jacobians of the model.Type: GrantFiled: July 16, 2007Date of Patent: June 14, 2011Assignee: The Math Works, Inc.Inventor: Joseph Daniel Kanapka
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Patent number: 7957942Abstract: A position detection and simulation platform includes software configurable logic and programmable inputs and outputs to support software configuration only changes for use with a variety of position feedback devices including synchros, resolvers, linear variable differential transformers, and rotary variable differential transformers. The platform provides support for all of these devices without making hardware changes to the platform; all changes are accomplished through software programming of configurable registers and logic devices. In this way the platform can universally be applied to applications that require interfacing to any of the supported devices. Additionally, the platform can be reconfigured through software to provide complete simulation of any of the supported devices.Type: GrantFiled: June 22, 2008Date of Patent: June 7, 2011Assignee: United Electronic Industries, IncInventors: Olexiy Ivchenko, Denys Kraplin
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Patent number: 7933753Abstract: A modeling circuit includes a field-effect transistor, a first current source, a first bipolar transistor, a second current source and a second bipolar transistor. The first bipolar transistor and the second bipolar transistor are parasitic bipolar transistors that are arranged symmetrically to each other. Therefore, the modeling circuit can be used in simulating the field effect transistors reflecting electrostatic-discharge characteristic regardless of the polarity of a source and a drain.Type: GrantFiled: November 2, 2007Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Gi-Young Yang, Se-Young Kim
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Patent number: 7930609Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.Type: GrantFiled: September 17, 2008Date of Patent: April 19, 2011Assignee: Renesas Electronics CorporationInventor: Tsuyoshi Inagawa
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Patent number: 7877244Abstract: A simulating circuit for simulating a toggle magnetic tunneling junction (MTJ) element includes at least a synthetic Anti-Ferromagnetic free layer, a tunnel barrier layer, and a synthetic Anti-Ferromagnetic pinned layer. The simulating circuit is configured with a converting circuit, a status circuit, a storage circuit, a voltage computing circuit and a feature simulating circuit. The convert circuit converts the magnetic filed generated from a write in current to an equivalent voltage. The status circuit indicates the flipping status of the magnetic moment of the free layer. The storage circuit is used for representing data stored in the toggle magnetic tunneling junction element. The arrangement of the magnetic moment of the two Anti-Ferromagnetic adjacent to the tunnel barrier layer is represented by the voltage computing circuit. The voltage-current characteristic is represented by the feature simulating circuit.Type: GrantFiled: February 28, 2008Date of Patent: January 25, 2011Assignee: Industrial Technology Research InstituteInventor: Young-Shying Chen
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Patent number: 7877659Abstract: Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle read-write collisions and generally avoid reloading or resources. The model provides accurate result prediction, and allows write access restrictions to be removed from sensitive memory areas, such as control areas.Type: GrantFiled: October 30, 2006Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Felix Geller, Yehuda Naveh
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Patent number: 7865795Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.Type: GrantFiled: February 28, 2008Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Thomas Nirmaier, Wolfgang Spirkl
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Patent number: 7856152Abstract: A light condition recorder system and method including a light condition recorder (104) responsive to a lighting environment (102) and generating an environment signal (112), a light simulator (106) responsive to the environment signal (112) and generating a lamp control signal (114), and a lamp system (108) responsive to the lamp control signal (114) and generating a simulated lighting environment (110).Type: GrantFiled: March 22, 2006Date of Patent: December 21, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Elmo M. A. Diederiks, Martijn A. B. Santbergen, Bartel Marinus Van De Sluis, Tatiana A. Lashina, Astrid Van Spronsen, Andres Lucero Vera, Talitha Boom
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Patent number: 7856345Abstract: A method for managing and/or producing an output, the method comprising the steps of providing one or more layouts, each layout being divided into a number of zones, the one or more layouts in combination at least substantially covering the output; providing a number of rendering elements, each being adapted to perform a function and/or an action; assigning one or more relations and/or one or more orderings between the rendering elements and the zones; processing the zones of the one or more layouts according to the one or more relations and/or the one or more orderings, and by means of the rendering elements; providing, for each of the zones, an output based on the rendering elements and the one or more relations and/or orderings; and collecting the output of each of the zones into a final output.Type: GrantFiled: November 21, 2002Date of Patent: December 21, 2010Assignee: Sitecore A/SInventors: Jakob H. Christensen, Ole S. Thrane
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Patent number: 7844414Abstract: A method of calibrating an individual sensor of a particular sensor type whose output varies non-linearly with at least one measured quantity and at least one operating condition. The first step includes producing a set of calibration curves for each sample sensor of the particular sensor type. The resulting sets of calibration curves are then averaged and the results used to produce a generic calibration surface for the particular sensor type showing its variation. Individual calibration measurements are then taken for a number of different values of the measured quantity at a small number of discrete values. The individual calibration readings are then used to map the generic calibration surface to the individual calibration measurements of the individual sensor.Type: GrantFiled: December 4, 2008Date of Patent: November 30, 2010Assignee: Transense Technologies PLCInventor: Victor Alexandrovich Kalinin
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Patent number: 7827007Abstract: A battery characteristic simulating apparatus is provided for supplying electric power for simulating a battery characteristic of a battery to a battery-driven type electronic appliance. The battery characteristic simulating apparatus includes a voltage/current generating unit; a voltage/current measuring unit; a characteristic data acquiring unit; a storage unit; and a simulation signal producing unit that are provided within the same housing of the battery characteristic simulating apparatus.Type: GrantFiled: September 20, 2007Date of Patent: November 2, 2010Assignee: Yokogawa Electric CorporationInventors: Akihiko Ito, Masayoshi Honma, Takashi Tsuneoka
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Patent number: 7826989Abstract: In Internal Analysis Space analysis, assuming that no structural body and the like are placed outside of a conversion surface, an electromagnetic field distribution u0 inside of a conversion surface, on a conversion surface, and close to the outside of the conversion surface is found. In External Analysis Space analysis, on the assumption that there exists a structural body and the like outside of the conversion surface, an entire electromagnetic field distribution u is found. At this time, for the inside of the closed surface, an electric field distribution, where a differential electromagnetic field distribution e between electromagnetic field distribution u0 and electromagnetic field distribution u on the closed surface is a wave source, is found. Also at this time, for the outside of the closed surface, an electromagnetic field distribution, obtained by synthesizing electromagnetic field distribution u0 and electromagnetic field distribution e on the closed surface is found.Type: GrantFiled: December 10, 2007Date of Patent: November 2, 2010Assignee: Sharp Kabushiki KaishaInventor: Tatsuroh Kiso
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Patent number: 7822578Abstract: Predictive maintenance systems and methods are described. A method includes measuring environmental conditions using a plurality of sensors within the IED, processing the environmental measurements to determine long-term exposure factors representing historical operating conditions of the IED, applying a reliability model to the long-term exposure factors, determining a numerical measure of IED life based on the long-term exposure factors and the reliability model, comparing the numerical measure of IED life to preselected boundary values, and signaling if the numerical measure of IED life is outside of the preselected boundary values.Type: GrantFiled: June 17, 2008Date of Patent: October 26, 2010Assignee: General Electric CompanyInventors: Bogdan Z. Kasztenny, Lawrence A. Sollecito, Jeffrey G. Mazereeuw, Zhihong Mao
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Patent number: 7818693Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.Type: GrantFiled: January 8, 2008Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha
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Patent number: 7813301Abstract: A computer-implemented method receives a list of polygonal vertices associated with multiple polygons located in proximity to one another in a two-dimensional region and analyzes the polygonal vertices. The method automatically generates, based on the analysis, a polygonal hull that encloses the multiple polygons such that a line segment connecting any two polygonal vertices of the multiple polygons falls completely inside the generated polygonal hull. The multiple polygons may correspond to a two-dimensional geographic region. The computer-implemented method may be used for geographic regional segmentation.Type: GrantFiled: May 8, 2008Date of Patent: October 12, 2010Assignee: Verizon Patent and Licensing Inc.Inventors: Ching-Yun Yeh, Robert Funk, Kumar Annamraju
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Publication number: 20100250211Abstract: This invention relates generally to a method of simulating the signal of an electromagnetic source using one or more dipole sources. In the method a dipole source is located at an excitation location corresponding to a segment of the electromagnetic source to be simulated. The dipole source is activated, and an electromagnetic signal recorded at one or more receiver locations. This process is repeated for additional excitation locations corresponding to additional segments of the electromagnetic source. The data from the sequence of dipole source excitation locations is processed to determine the simulated signal of the electromagnetic source.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Inventors: Leonard J. Srnka, James J. Carazzone
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Patent number: 7774372Abstract: A computer system and a relational database management system (RDMS) computer program product are described for interfacing a number of concurrently running database sessions with a large database in which a plurality of local temporary object database descriptors are used in lieu of a single global temporary object database descriptor where the global and each of the local temporary object database descriptors include identifiers for temporary objects, each of the local temporary object database descriptors is associated with a single database session and each of the global database descriptors is shared among multiple database sessions.Type: GrantFiled: May 16, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Ramani M. Croisettier, Paramesh S. Desai, James Z. Teng
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Patent number: 7765067Abstract: A multicomponent induction logging tool is used on a MWD bottomhole assembly. Multifrequency focusing that accounts for the finite, nonzero, conductivity of the mandrel is applied. Using separation of modes, the principal components and relative dip angles in an earth formation are determined. The results are used for reservoir navigation in an earth formation.Type: GrantFiled: May 7, 2007Date of Patent: July 27, 2010Assignee: Baker Hughes IncorporatedInventors: Leonty A. Tabarovsky, Michael B. Rabinovich
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Patent number: 7761803Abstract: A system for designing light and sound systems for use in stage productions. Virtual reality interfaces facilitate the selection and location of lighting and sound displays by providing a real-time simulation of the devices and the display produced thereby. The system also calculates parameters with respect to structural elements used for mounting the lighting and sound equipment. In addition, the virtual reality interface permits the simulation of the packing of the lighting and sound equipment and the automatic calculation of parameters relating to packing space, package weight, preferred location, and order of packing.Type: GrantFiled: May 13, 2003Date of Patent: July 20, 2010Assignee: Production Resource Group, Inc.Inventors: Richard Parker, William Hewlett
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Patent number: 7761268Abstract: A non-linear transient analysis module and method for phase locked loop (PLL) is disclosed. The method includes a pulse cycle defined by the larger period of two input frequencies; a pulse width defined by the accumulation value of period difference. Each pulse cycle is divided into two linear regions, a first voltage at the beginning of the pulse cycle as an initial value then applying a first linear equation to obtain a second voltage, and then the second voltage as an initial value then applying a second linear equation to obtain a third voltage which is used to be an initial value for next pulse cycle. An average voltage of the first region and the second region is inputted into the VCO to generate an output as the PFD input. The aforementioned steps are repeated to complete a simulation of PLL transient response.Type: GrantFiled: May 2, 2007Date of Patent: July 20, 2010Assignee: National Changua University of EducationInventor: Zhi-Ming Lin
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Publication number: 20100156205Abstract: A compact, rugged, variable reluctance, variable speed, electric motor capable of producing high torque at high electrical energy conversion efficiencies is provided. The present invention provides for a multi-stage motor design having a number of discreet rotor and stator elements on a common shaft. This configuration provides for the simplest of magnetic structures and produces a powerful magnetic flux modelling design technique that is used to further optimize the motor design and subsequent control logic. Thermal mapping of the magnetic mass provides for advanced cooling techniques that are used to ensure long in-service life in the most extreme of industrial applications. The electric motor inherently provides low vibration thereby greatly reducing noise; low turn to turn voltage potentials thereby eliminating costly phase to phase shorting potential; efficient motor operation through the reduction in switching and copper losses in both the machine and its control system.Type: ApplicationFiled: August 22, 2008Publication date: June 24, 2010Applicant: SUNCO INVESTMENTS LTD.Inventors: John A. Davis, Iain C Davis, Feisal A Hurzook
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Patent number: 7739098Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.Type: GrantFiled: February 4, 2004Date of Patent: June 15, 2010Assignee: Synopsys, Inc.Inventors: Kayhan Küçükçakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew J. Seigel
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Publication number: 20100114543Abstract: A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Inventors: Yasuhiro NAMBA, Peter Lee
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Patent number: 7711538Abstract: A method and apparatus for simulating the operation of a rechargeable battery. A value is obtained for at least one parameter that describes an internal state of the battery. The obtained value is used for calculating a prediction value for a characteristic of the battery that is observable outside the battery. These steps are repeated a multitude of times in order to simulate the operation of the battery over a certain period of time. A difference is detected between a calculated prediction value and a known value of a corresponding characteristic in a corresponding situation. The obtained value of the at least one parameter is corrected before a further prediction value is calculated by an amount that is proportional to the detected difference.Type: GrantFiled: November 29, 2002Date of Patent: May 4, 2010Inventors: Teuvo Suntio, Robert Tenno, Ander Tenno
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Patent number: 7680644Abstract: A computerized model provides a display of a physical environment in which a communications network is or will be installed. The communications network is comprised of several components, each of which are selected by the design engineer and which are represented in the display. Errors in the selection of certain selected components for the communications network are identified by their attributes or frequency characteristics as well as by their interconnection compatibility for a particular design. The effects of changes in frequency on component performance are modeled and the results are displayed to the design engineer. A bill of materials is automatically checked for faults and generated for the design system and provided to the design engineer. For ease of design, the design engineer can cluster several different preferred components into component kits, and then select these component kits for use in the design or deployment process.Type: GrantFiled: October 31, 2003Date of Patent: March 16, 2010Assignee: Wireless Valley Communications, Inc.Inventors: Theodore Rappaport, Roger Skidmore, Eric Reifsneider
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Patent number: 7653524Abstract: Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.Type: GrantFiled: August 22, 2005Date of Patent: January 26, 2010Assignee: Carnegie Mellon UniversityInventors: Xin Li, Yang Xu, Peng Li, Lawrence Piileggi
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Patent number: 7650271Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.Type: GrantFiled: March 31, 2006Date of Patent: January 19, 2010Assignee: Intel CorporationInventors: Frank P. O'Mahony, Haydar Kutuk, Bryan K. Casper, Eyal Fayneh, Sivakumar Mudanai, Wei-kai Shih, Farag Fattouh
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Patent number: 7650275Abstract: Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.Type: GrantFiled: January 20, 2005Date of Patent: January 19, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Russ Herrell, Gerald J. Kaufman, Jr., John A. Morrison
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Publication number: 20100004909Abstract: In a method and system for simulating a magnetic resonance image of an examination subject, imaging parameters are determined that correspond to an imaging sequence that will be used to generate a magnetic resonance image of an examination subject, this being the magnetic resonance image that is to be simulated. At least one item of anatomical information of the subject is determined, and signal-to-noise information of the MR system, with which the magnetic resonance image of the subject will be generated, also is determined. The magnetic resonance image is simulated in a processor in real time dependent on the determined imaging parameters, the determined anatomical information, and the determined signal-to-noise information. The simulated magnetic resonance image is then visually displayed.Type: ApplicationFiled: July 7, 2009Publication date: January 7, 2010Inventor: Wolfgang Nitz
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Patent number: 7565637Abstract: A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and an internal connection terminal connected to the chip, the method comprising: setting an acceptable noise value of the package; designing a package layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on package layout data so that an amount of noises remains within a range which is set beforehand, on the basis of the package layout data obtained in the designing process of the package layout.Type: GrantFiled: November 3, 2006Date of Patent: July 21, 2009Assignee: Panasonic CorporationInventors: Koichi Seko, Shinya Tokunaga
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Patent number: 7555689Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.Type: GrantFiled: June 28, 2006Date of Patent: June 30, 2009Inventors: Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
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Publication number: 20090164180Abstract: Disclosed are an apparatus and a method for modeling a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The method can include the steps of: establishing an equation and a variable that determine the driving current characteristics of the MOS transistor; generating a random number; converting the random number such that the random number has a value satisfying an equation of a rotated ellipse and determining a variation degree of the variable based on the value of the random number; and outputting driving current distribution of the MOS transistor by using the equation and the variation degree of the variable.Type: ApplicationFiled: November 6, 2008Publication date: June 25, 2009Inventor: Seok Yong KO
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Publication number: 20090144035Abstract: A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Yuri Mirgorodski, Peter J. Hopper, William French, Philipp Lindorfer
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Patent number: 7542858Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.Type: GrantFiled: June 3, 2005Date of Patent: June 2, 2009Assignee: LSI CorporationInventors: Randall F. Horning, Edde Tin Shek Tang, Del Fafach, Jr.
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Patent number: 7538873Abstract: A method for determining the movement of particles, particularly impurities, in a medium, under the influence of a changing interface between two neighboring phases. In a first step, the temporal and/or local evolution of said interface is determined. In a second step, the movement of said particles in dependence of the temporal and/or local evolution of the phase interface as determined in the first step is calculated. Optionally, the distribution of the particles within the medium at a certain time is then determined.Type: GrantFiled: November 13, 2006Date of Patent: May 26, 2009Assignee: Synopsys Switzerland LLCInventor: Christoph Zechner
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Patent number: 7536675Abstract: A system for high level dynamic hot code generation. A class file container object is first created. Methods and code are then added to the class file container object. Byte code is then generated from the populated class file container object. From the byte code, instances of the new class object can by generated. The program code generator is configured to generate code at a programming language construct level, thereby working at a level of program language statements, expressions, variables, and other constructs.Type: GrantFiled: November 12, 2003Date of Patent: May 19, 2009Assignee: BEA Systems, Inc.Inventor: William John Gallagher
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Patent number: 7532317Abstract: A system and method for efficiently and accurately determining grating profiles uses characteristic signature matching in a discrepancy enhanced library generation process. Using light scattering theory, a series of scattering signatures vs. scattering angles or wavelengths are generated based on the designed grating parameters, for example. CD, thickness and Line:Space ratio. This method selects characteristic portions of the signatures wherever their discrepancy exceeds the preset criteria and reforms a characteristic signature library for quick and accurate matching. A rigorous coupled wave theory can be used to generate a diffraction library including a plurality of simulated diffraction spectrums based on a predetermined structural parameter of the grating. The characteristic region of the plurality of simulated diffraction spectrums is determined based on if the root mean square error of the plurality of simulated diffraction spectrums is larger than a noise level of a measuring machine.Type: GrantFiled: December 28, 2005Date of Patent: May 12, 2009Assignees: Industrial Technology Research Institute, Nanometrics IncorporatedInventors: Nigel Smith, Yi-sha Ku, Shih Chun Wang, Chun-hung Ko
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Publication number: 20090099821Abstract: A computer system to predict a value of a signal from a sensor schedule loads across a set of processor cores is described. During operation, the computer system generates N models to predict the value of the signal based on a set of quantized telemetry signals, where a given model produces a value of the signal using a subset of the set of quantized telemetry signals, and where the subset is selected from the set of quantized telemetry signals based on an objective criterion. Next, the computer system predicts the value of the signal by aggregating the values produced by the N models.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Ramakrishna C. Dhanekula, Keith A. Whisnant, Kenny C. Gross
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Patent number: 7514940Abstract: A system and method are disclosed for determining the effective channel width (Weff) and the effective channel length (Leff) of metal oxide semiconductor devices. One advantageous embodiment of the method provides a plurality of metal oxide semiconductor field effect transistor capacitors in which each capacitor has a same value of drawn channel length but a different value of drawn channel width. A value of Fowler-Nordheim tunneling current is measured from each capacitor. Channel width offset is the difference between the drawn channel width and the effective channel width. A value of channel width offset is obtained from the measured values of the Fowler-Nordheim tunneling currents and used to determine the value of effective channel width. A similar method is used to determine the value of the effective channel length.Type: GrantFiled: December 13, 2006Date of Patent: April 7, 2009Assignee: National Semiconductor CorporationInventor: Jiankang Bu
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Patent number: 7505886Abstract: A technique for programmatically obtaining experimental measurements for model construction. A user provides criteria for the model, such as computational algorithms which characterize behavior of the real system, specifications of experiments to be performed on the real system for collecting experimental data from the real system, an identification of sought parameters which are to be derived from results of the experiments and desired tolerance constraints on the sought parameters. From experimental data collected from the real system and from the provided criteria, the inventive method and apparatus programmatically determines in an iterative loop which additional experiments are to be performed in order to achieve the desired tolerance constraints. After one or more iterations of the loop, the values for the sought parameters are determined within the desired tolerance constraints.Type: GrantFiled: September 3, 2002Date of Patent: March 17, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Guillermo Alvarez, Fabian E. Bustamante, Ralph Becker-Szendy, John Wilkes