Abstract: A method determines and/or predicts a maximum power capacity of a battery by using a model of the battery based on an electric equivalent circuit diagram that predicts the maximum power capacity of the battery. The maximum power of the battery is prognosticated for a defined prognosis period and for the different operating modes with respect to the charging or discharging operation, considering the maximum allowable operating voltage and the maximum allowable operating current.

Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.

Abstract: The present invention proposes methods, devices and computer program products. To this extent, there is defined a set X including N distinct parameter values x_i for at least one input parameter x, N being an integer greater than or equal to 1, first measured the physical quantity Pm1 for each of the N distinct parameter values x_i of the at least one input parameter x, while keeping all other input parameters fixed, constructed a Vandermonde matrix VM using the set of N parameter values x_i of the at least one input parameter x, and computed the model W for emulating the physical quantity P based on the Vandermonde matrix and the first measured physical quantity according to the equation W=(VMT*VM)?1*VMT*Pm1. The model is iteratively refined so as to obtained a desired emulation precision. The model can later be used to emulate the physical quantity based on input parameters or logs taken from the field and thereby support device design optimization.

Abstract: In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers.

Abstract: Disclosed are various embodiments for transmission evaluation. In one embodiment, among others, a method includes evaluating a plurality of contingencies to generate a plurality of contingency results, where at least one of the contingency results includes an overload condition. The evaluation is based at least in part upon a case associated with a transmission network. The method further includes sorting the plurality of contingency results based upon corresponding overload-contingency pairs and determining a potential remediation solution to the overload condition based at least in part upon the overload-contingency pair. In another embodiment, a system includes a transmission evaluation application executed in a computing device.

Abstract: In a computerized, automated method to determine the conductor structure of a gradient coil of a magnetic resonance device, the conductor structure is determined depending on the theoretical oscillation response of at least one metallic structure of the magnetic resonance device that is arranged adjacent to the gradient coil at the installation point, with the oscillation response of the metallic structure being determined dependent on theoretical eddy currents generated in the structure by the gradient coil.

Abstract: Channel emulation in a PC computing platform including at least one general purpose parallel processor (GPPP) includes defining a plurality of fading channels in a GPPP and generating complex tap coefficients in a GPPP for the fading channels.

Abstract: With a simulation apparatus for a system including a motor-driven compressor, a compressor that does not suffer from a driving torque shortage and surging, but can operate at low costs, can be provided. A simulation apparatus for a motor-driven compressor system includes a simulation section in which a driving motor, a compressor driven by the driving motor, a suction throttle valve controlling the inlet flow rate of the compressor, and an anti-surge valve interposed between pipes for returning a part of gas discharged from the compressor to the inlet side of the compressor are translated into unit models and stored. The simulation apparatus further includes an input section through which designed specification data of the compressor is input, a data setting section storing the designed specification data, and a display section displaying unsteady-state Q-H characteristics and required driving torque obtained through simulation by the simulation section.

Abstract: Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example.

Abstract: The size distribution f(r) of powder particles is found, and the packing rate p of the powder particles is found based on the size distribution f(r) according to the following formula (a): p = ? i ? ? ? j ? ? r i 2 ? r j 3 ? f ? ( r i ) ? f ? ( r j ) ? r 2 ? ? ? r 3 ? ? p ji ? ( max ) ( a ) where f(ri): a frequency of i-particles having a radius of ri contained in the powder particles, f(rj): a frequency of j-particles having a radius of rj contained in the powder particles, ri: the radius of the i-particles contained in the powder particles, rj: the radius of the j-particles contained in the powder particles, ? r 2 ? : ? i ? ? r i 2 ? f ? ( r i ) ? r 3 ? : ? i ? ? r i 3 ? f ? ( r i ) pji(max): a void fraction in a hypothetical sphere having a radius of rj+ri around a j-particle having a radius of rj when the j-particle has i-particles most closely packed therearound so as be

Abstract: Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.

Abstract: A position detection and simulation platform includes software configurable logic and programmable inputs and outputs to support software configuration only changes for use with a variety of position feedback devices including synchros, resolvers, linear variable differential transformers, and rotary variable differential transformers. Power to the software configurable outputs is dynamically controlled so that the power supply voltage presented to the outputs satisfies a minimum threshold above the amplitude of the output signal. Dynamic control is based on at least one of a digital representation of a signal to be output, an analog version of the signal to be output, or the signal being output.

Abstract: A system for generating behavioral models for analog circuits may include a database that is configured to store a parameterized hardware description language model of an analog circuit and an analog circuit simulator template of the analog circuit. The system may also include an interface module configured to receive data for an instance of the analog circuit in a schematic format. The system may also include an analog circuit simulator configured to use the received data and the analog circuit simulator template to generate a value for a parameter of the parameterized hardware description language model of the analog circuit. The system may also include a model constructor configured to generate a behavioral hardware description language model of the instance of the analog circuit based on the parameterized hardware description language model of the analog circuit and the generated value.

Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.

Abstract: A mechanism is provided for determining fragmentation in a computing environment. A simulation of virtual machine requests for resources in the computing environment is run for a predetermined time. The simulation is scaled down when the predetermined time exceeds a threshold. The scaling down includes scaling down the resources in the computing environment and/or scaling down a number of the virtual machine requests. The scaled down simulation is run iteratively to estimate relative fragmentation of the virtual machine requests against the resources in the computing environment.

Abstract: A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior.

Abstract: Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs).

Abstract: A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.

Abstract: An improved algorithm for calculating multimode fiber system bandwidth which addresses both modal dispersion and chromatic dispersion effects is provided. The radial dependence of a laser transmitter emission spectrum is taken into account to assist in designing more effective optical transmission systems.

Abstract: Incoming data from, for example, an array of detectors, may be received. A dynamical system may be initialized corresponding to a modality of the incoming data so that a measurement probe based on the initialized dynamical system may be generated. Such a measurement probe may be injected into a quantum mechanical system so that it may be determined whether the injection of the measurement probe into the quantum mechanical system results in a collapse of the quantum mechanical system. Thereafter, it may be determined that a signal is present within the incoming data if the quantum mechanical system collapses. Related methods, apparatuses, systems, and computer-program products are also described.

Abstract: A method for identifying an anomaly in an electronic system includes receiving, from a computer-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, each of the plurality of entries including information about simulation time. The method also includes, with one or more computer processors, determining time sequence relationship between pairs of entries selected from the plurality of entries and identifying allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship. The method includes receiving a second plurality of entries from a failed simulation test of the electronic system, each of the second plurality of entries including information about simulation time. The method includes analyzing the second plurality of entries and identifying one or more anomalies in the electronic system based on the analysis of the failed simulation test.

Abstract: System and method for executing a graphical program. A first structure in a graphical program is displayed on a display. The first structure includes two or more frames, each configured to contain a respective portion of the graphical program. The respective portions of the graphical program are included in the two or more frames. During execution of the graphical program, the first structure executes the respective portions of the graphical program in the two or more frames in parallel via respective execution processes. When a first portion of the respective portions completes execution prior to all others of the portions, execution of the other portions is terminated.

Abstract: A method and a device are provided for performing channel simulation. The device includes a radio channel simulation block and a memory and it is configured to simulate a radio connection between a transmitter and a receiver in real time. The device is further configured to simulate a radio connection between at least one interfering signal source and the receiver in real time, and to store the simulation result in the memory, and to read the stored simulation results in real time from the memory and add the results read to the simulation during simulation of the radio connection between the transmitter and the receiver.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: A general, computational-mathematical modeling method for the solution of large, boundary-coupled transport problems involving the flow of mass, momentum, energy or subatomic particles is disclosed. The method employs a modeling processor that extracts a matrix operator equation (or set of equations) from a numerical transport code (NTC). The outputs of software codes, available for modeling physical problems governed by conservation laws in the form of differential equations, can be processed into closed-form operator equations with the method. Included is a numerical transport code functionalization (NTCF) model which can be determined numerically, based on a system of solutions of an NTC, evaluating outputs for a given set of inputs. The NTCF model is a linear or nonlinear, multi-variable operator equation or set of such equations. The NTCF model defines relationships between general, time-variable inputs and outputs, some known and some unknown, considered as boundary values.

Abstract: A semiconductor component on a semiconductor chip comprises at least one sensor element for measuring a physical quantity and an evaluator. The semiconductor component can be switched between a first and a second operating mode. In the first operating mode, the sensor element is sensitive to the physical quantity to be measured and a measurement signal output of the sensor element is connected to an input connection of the evaluator. In the second operating mode, the sensor element is not sensitive to the physical quantity to be measured and/or the signal path between the measurement signal output and the input connection is interrupted. A test signal source for generating a test signal simulating the measurement signal of the sensor element is arranged on the semiconductor chip. In the second operating mode, the test signal source is connected or capable of being connected to the input connection of the evaluator.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: The invention is a novel method and apparatus for optimal placement of actuators responsible for shaping of elastically deformable structures into desired target shapes using sparse number of actuators such that the discrepancy between deformed surfaces and target shapes is minimized. The invention utilizes a computational algorithm for optimal placement of actuators using particle swarm optimization, a biologically inspired evolutionary optimization paradigm that searches for the minima (or maxima) of objective functions with possibly large number of parameters.

Abstract: Disclosed herein are improved systems and methods for right sizing grid models for performing, for example, reservoir simulations. Implementations in accordance with the present disclosure may begin with a relatively fine scale grid model. Successive coarsening and resampling operations may be repeated until one or more characteristics of the coarsened grid model begin to unacceptably diverge from those of the fine scale model. Similarly, successive coarsening and upscaling operations may be performed until one or more characteristics of the coarsened grid model begin to unacceptably diverge from those of the previously-coarsened grid model. The resulting coarsened grid model may be suitably sized for reservoir simulations.

Abstract: A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

Abstract: Disclosed herein are improved coarsening and splitting techniques for preparing grids for performing simulations. In some implementations, methods in accordance with the present disclosure may include providing a grid having a plurality of grid pillars; and performing one or more splitting operations on at least a portion of the grid to increase a grid density within the portion of the grid, the plurality of grid pillars within the portion of the grid being forced to remain fixed in position during the one or more splitting operations.

Abstract: A road shape recognition device includes: distance and height detecting means for detecting distance data having a distance and height in real space regarding a road surface where a vehicle is traveling at multiple mutually different points; approximation line calculating means for dividing the plurality of distance data into near and far groups as viewed from the vehicle to calculate an approximation line of the distance data for each group each time the distance data of the boundary portion between the two groups is transferred from one of the groups to the other; statistics calculating means for calculating statistics from the corresponding approximation line for each group where the distance data is transferred; and road shape model generating means for selecting one out of combinations of the approximation lines to generate a road shape model using the selected combination.

Abstract: A method for calculating values of parameters of a TFT includes calculating a set of simulated current-voltage (I-V) values using state-density-functions over an entire energy band in a band gap of an amorphous semiconductor of the TFT. The method further includes comparing the set of simulated I-V values with a set of measured I-V values of the TFT to determine a value of a parameter of the TFT. The method may further include calculating values of an acceptor state-density-function gA using a set of electrostatic capacity-voltage (C-V) values of the TFT measured according to a frequency. The method may further include determining values of a donor state-density-function gD and values of an interface state-density-function Dit over the entire energy band in the band gap.

Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.

Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract: Methods and systems for modeling and displaying magnetic field intensities during Transcranial Magnetic Stimulation (TMS) are described, particularly methods and system for modeling and displaying TMS using overlapping magnetic fields to stimulate deep brain regions.

Abstract: An online simulation system for a flexible AC transmission system (FACTS) which is capable of analyzing operation control effect of the FACTS in advance through an online data connection with a supervisory control and data acquisition (SCADA) system used for operating an electric power system.

Abstract: In order to emulate the inputs from a DHS, RTD type sensors are typically employed, externally heated, and the input provided into an interface unit. At best such an approach provides a stop-gap solution that is cumbersome and not reliably repeatable. Such temporary inputs seldom provide the equivalent communications protocol verification between the surface controller of the DHS and the external communications device. Each DHS commercially available also uses different MODBUS register addresses for the requested data, as well as a variation in the number of parameters expected from the DHS itself, ranging from 3 to 7, depending on the vendor of choice. In this new design, a number of potentiometers are used to provide a variable signal level to the microprocessor, acting as variable parameters from the downhole sensor, the settings of which can be repeated for reliable test results.

Abstract: An electrical connection defect simulation test method is provided. The electrical connection state simulation test method includes the steps as follows. A device under test is provided, wherein the device under test includes a plurality of pin groups each having a plurality of signal pins. A zero-frequency signal is transmitted from a signal-feeding device to each of the signal pins to simulate an open condition. An open test is performed on each of the signal pins. The signal pins of the device under test are connected to a relay matrix. The relay matrix is controlled to make any two of the signal pins in one of the pin groups electrically connected to simulate a short condition. A short test is performed on any two of the electrically connected signal pins. An electrical connection state simulation test system is disclosed herein as well.

Abstract: A system and method for radio network planning comprises a grid generator and a Monte Carlo analysis module. The Monte Carlo analysis module comprises a snapshot generation module which draws, for each snapshot and for each pixel, a statistical realization from a distribution function relating to slow fading, and a snapshot evaluation module which establishes radio network parameters. The Monte Carlo analysis module further comprises a sub-snapshot generation module which generates at least one sub-snapshot for each evaluated snapshot result, and a sub-snapshot evaluation module (14) for evaluating HSDPA performance parameters based on the sub-snapshot. The sub-snapshot evaluation module (14) comprises a scheduler module (16) which is arranged for scheduling a HSDPA user according to a scheduling scheme.

Abstract: A method and device characterize linear properties of an electrical component having n>1 ports. The linear properties of the component are described in a matrix relating a voltage applied to the ports to a current through the ports. A frequency dependence of the matrix is approximated to preserve eigenvalues of the matrix by a pole-residual model. The method includes: (a) obtaining a set of values of the matrix at discrete frequencies, and obtaining eigenvalues and eigenvectors for each value; (b) fitting a set of vector equations to the eigenvalues and eigenvectors with a first set of pole frequencies; and (c) calculating a second set of pole frequencies by a vector fitting process for all modes of an element of the matrix. Steps (b) and (c) are repeated using the second set of pole frequencies in step (c) in a subsequent step (b) until a stop condition is met.

Abstract: Methods and apparatus are provided for a model-based diagnostic interface. An apparatus is provided for a diagnostic interface for a system having system data, system information, and a system model having a model nomenclature, the diagnostic interface comprising at least one computational object producing an output responsive to said system data, wherein said at least one object includes a binding of said system data to said system information, wherein said system data is mapped to said model nomenclature before being bound. A method is provided for making a model-based diagnostic interface for a system having system information and system data representing the status of said system, the method comprising the steps of modeling said system to create a system model having a system model nomenclature, mapping said system data into said system model nomenclature, and binding said system data mapped to said system model nomenclature to said system information.

Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

Abstract: The hybrid artificial immune system consists of three main layers, including a solution application layer that interacts with the environment, a solution generation layer that solves combinatorial optimization problems and a modeling layer that analyzes problems and presents solution scenarios. The system solves evolutionary multi-objective optimization problems in network computing, robotics, artificial neural networks, protein network modeling, evolutionary systems and evolutionary hardware.

Abstract: An automated approach is provided for evaluating stress upon analog components embedded in a digital electronic circuit design. The approach includes establishing a computer readable circuit definition of the digital electronic circuit design. The circuit definition is then partitioned into a plurality of circuit portions, which are re-defined to form a plurality of analog topologies. The analog topologies are adapted for automatic analog simulation one independent of the other, with all digital components substituted by at least one subcircuit including instantiation of a corresponding input output (IO) buffer model. Automatic analog simulation is carried out upon the analog topologies to generate simulated results data, which are automatically postprocessed to generate worst-case stress measurement data for one or more critical components identified in the analog topologies.

Abstract: A system for real-time optimization of power resources on an electrical system is disclosed. The system includes a data acquisition component, an analytics server, a control element and a client terminal. The data acquisition component is communicatively connected to a sensor configured to acquire real-time data output from the electrical system. The analytics server is communicatively connected to the data acquisition component and is comprised of a virtual system modeling engine, an analytics engine and a power flow optimization engine. The virtual system modeling engine is configured to generate predicted data output for the electrical system utilizing a virtual system model of the electrical system. The control element is interfaced with an electrical system component and communicatively connected to the analytics server. The client terminal is communicatively connected to the analytics server.