Abstract: The data processing device includes a virtual data sequence generator to extrapolate an approximate line approximating a temporal change of an input data sequence being inputted from outside and is a sequence of data at time points of a predetermined first number that are arranged in succession with at a predetermined time interval to a head or a tail of input data sequence and to generate a virtual data sequence being a sequence of data representing values on extrapolated approximate line at time points of a predetermined second number that are arranged in succession with the time interval, the time points including a time point being adjacent to input data sequence, a data sequence connector to generate a processed data sequence being a data sequence in which virtual data sequence is connected to input data sequence on a side where approximate line of input data sequence is extrapolated.

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Abstract: In some implementations, a method includes: obtaining a reference image frame and forward flow information; for a respective pixel within a target image frame, obtaining a plurality of starting points within the reference image frame with different depths; generating a plurality of intermediate warp results based on the plurality of starting points and the forward flow information, wherein each of the plurality of intermediate warp results is associated with a candidate warp position and an associated depth; selecting a warp result for the respective pixel from among the plurality of intermediate warp results, wherein the warp result corresponds to the candidate warp position associated with a closest depth to a viewpoint associated with the reference image frame; and populating pixel information for the respective pixel within the target image frame based on pixel information for a reference pixel within the reference image frame that corresponds to the warp result.

Abstract: A spectrum analyzer having a memory function to adopt a digital-data-based frequency sweep scheme while achieving performance comparable to performance of a high-speed FFT spectrum analyzer, and a method of controlling the spectrum analyzer, in which the spectrum analyzer includes: an ADC for converting a BWP signal, which is at least one analog unit frequency band signal, into a digital data sample at a predetermined sample rate according to a span set by a user; a digital sweep part for sweeping the data sample passed through the ADC while digitally decimating the data sample through a decimation processing block having a two-stage cascaded structure, and processing the swept data sample to increase a frequency sweep speed; and a control unit for controlling the digital sweep part according to various items input, set, and selected by the user to perform spectrum analysis and output a spectrum analysis result.

Abstract: A distributed control system may include a main processing unit, a distributed control module, and a controllable component. The distributed control module may be configured to receive a nominal command reference from the main processing unit, determine a series of cumulating command references based at least in part on the nominal command reference; and output a series of cumulating control commands to the controllable component. The series of cumulating control commands may be based at least in part on the series of cumulating command references.

Abstract: A method of operating an atomic force microscope (AFM), using a denoising algorithm, real-time, during AFM data acquisition. Total Variation and Non-Local Means denoising are preferred. Real time images with minimized sensor noise needing no post-image acquisition processing to account for noise as described herein results.

Abstract: A spectrum analyzer having a memory function to adopt a digital-data-based frequency sweep scheme while achieving performance comparable to performance of a high-speed FFT spectrum analyzer, and a method of controlling the spectrum analyzer, in which the spectrum analyzer includes: an ADC for converting a BWP signal, which is at least one analog unit frequency band signal, into a digital data sample at a predetermined sample rate according to a span set by a user; a digital sweep part for sweeping the data sample passed through the ADC while digitally decimating the data sample through a decimation processing block having a two-stage cascaded structure, and processing the swept data sample to increase a frequency sweep speed; and a control unit for controlling the digital sweep part according to various items input, set, and selected by the user to perform spectrum analysis and output a spectrum analysis result.

Abstract: Encoding and decoding systems are described for the provision of high quality digital representations of audio signals with particular attention to the correct perceptual rendering of fast transients at modest sample rates. This is achieved by optimising downsampling and upsampling filters to minimise the length of the impulse response while adequately attenuating alias products that have been found perceptually harmful.

Abstract: A method, system, and apparatus enabled to selectively choose a baud rate for communication of optical data using a modem enabled to operate with an optical signal modulated at plurality of finely tuned baud rates.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: This application relates to driver circuitry (200) for receiving a digital input signal (D) and outputting, at first and second output nodes (203p, 203n), first and second analogue driving signals respectively for driving a transducer (101), e.g. loudspeaker, in a bridge-tied-load configuration. The driver circuitry may particularly be suitable for driving low-impedance transducers. The driver circuitry has first and second digital-to-analogue converters (201p, 201n) configured to receive the digital input signal and the outputs of the first and second digital-to-analogue converters are coupled to the first and second output nodes respectively. A differential-output amplifier circuit (202) has outputs connected to the first and second output nodes and is configured to regulate the outputs of the digital-to-analogue converters at output nodes to provide the analogue driving signals.

Abstract: Systems and methods are provided for improving the operation of a computer or other electronic device that utilizes root-mean-square (RMS) measurements, e.g., RMS current measurements, by reducing error in the RMS measurement. A series of measurement samples are received at a processor, which executes a noise-decorrelated RMS algorithm including: calculating a current-squared value for each measurement sample by multiplying the measurement sample by a prior measurement sample in the series (rather by simply squaring each measurement sample as in conventional techniques), summing the current-squared values, and calculating an RMS value based on the summed values. The processor may also execute a frequency-dependent magnitude correction filter to correct for frequency-dependent attenuation associated with the noise-decorrelated RMS algorithm.

Abstract: An API latency estimation system estimates latencies as a function of subcomponent parameters. The system may obtain first information indicative of at least a characteristic of data of a request provided to an API and second information indicative of at least a utilization of a first subcomponent of the API used to fulfill a subtask of a task of the request. An estimated latency for the first subcomponent to fulfill the subtask is determined at least in part by applying a latency estimation model for the API to at least the first information and the second information. If a comparison of the estimated latency to a measured latency for the first subcomponent to perform the subtask indicates a potential anomaly, then an indication of the potential anomaly may be outputted. The model may be updated with API request fulfillment data that is not anomalous.

Abstract: A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Abstract: Approaches provide for determining spectral information for a communications signal, such as a wideband communications signal. For example, a communications signal (e.g., a wideband signal) is received at a set of analog-to-digital converters (ADCs). The output of the ADCs is divided into a set of segments. A center frequency for each segment is determined based on the segment bandwidth and a number of segments in the set. The segments can be filtered, buffered, and analyzed using at least one digital signal processing technique (e.g., Fast Fourier Transform (FFT) technique to generate a representation of the segments in the frequency domain. Thereafter, the spectrum of frequency components (i.e., the frequency-domain representation) of the segments can be used to determine the power spectral density of the communications signal for different resolutions based on a resolution mode of the system or other criteria of the system.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank.

Abstract: Systems and methods for implementing an application on a just-in-time basis can include selection of one of an application and a bundle of applications (“selected application”) by a user on a user interface of a portal application. An agent on the user device can obtain a use-policy for accessing a virtual disk corresponding to the selected application and launch the selected application. The virtual disk can be accessed with the agent according to the use-policy. The portal application can send a resource request to the agent for an update on a status of at least one of a virtual disk download and an application launch. The resource request can be one of a script request and an image request, and can be generated by the portal application based on an information package that incorporates the use-policy and is associated with an option selected through the PUI for the selected application.

Abstract: In a monitoring apparatus, a first analysis unit and a second analysis unit analyze inputted data. A first reception unit receives data of a first data stream and outputs the data of the received first data stream to the first analysis unit. A second reception unit receives data of a second data stream and outputs the data of the received second data stream to the second analysis unit. When an updating request indicating updating of the first analysis unit has been received, a control unit instructs the second reception unit to perform a sampling process on the second data stream and output data after the sampling process, and also changes an output destination of the first reception unit so that the data of the first data stream is at least partially outputted to the second analysis unit.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

Abstract: A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

Abstract: Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

Abstract: Improved techniques for presenting sound effects at a portable media device are disclosed. The sound effects can be output as audio sounds to an internal speaker, an external speaker, or both. In addition, the audio sounds for the sound effects can be output together with other audio sounds pertaining to media assets (e.g., audio tracks being played). In one embodiment, the sound effects can serve to provide auditory feedback to a user of the portable media device. A user interface can facilitate a user's selection of sound effect usages, types or characteristics.

Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif

Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

Abstract: A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

Abstract: A Scalable Finite Impulse Response (“SFIR”) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.

Abstract: In an embodiment, a touch sensitive device includes touch interface having rows and columns and a signal generator for generating unique orthogonal signals on a plurality of the rows, respectively. A touch processor identifies touch on the touch interface by processing touch signals present on the columns, and outputting a stream of touch events. A decimator receives the stream of touch events including information as to a pressure of the touch event or the contact area of the touch event, selectively identifies one or more of the touch events in the stream, and outputs a modified stream of touch events for use by the touch sensitive device.

Abstract: A power conversion apparatus can include: a power module configured to transfer an analog sensing signal corresponding to a current of an inductor and a voltage applied at both terminals of a capacitor, and to perform power conversion by driving a power semiconductor with a pulse-width modulation signal; and a controller configured to receive the analog sensing signal from the power module, to convert the analog sensing signal to a digital signal, to generate the pulse-width modulation signal, and to transfer the pulse-width modulation signal to the power module.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif

Abstract: In accordance with some embodiments, a method and apparatus for providing both a low-pass filter value and a high-pass filter value is presented. The combined filter receives an input value into a half-band finite impulse response (FIR) filter with an odd number of taps labeled 0 through N with corresponding filter coefficients labeled 0 through N where odd numbered filter coefficients are zero, the FIR filter providing a filter value. The median value from the FIR filter is digitally shifted to provide a half median value. The half median value is added to the filter value to provide the low-pass filter value and is subtracted from the filter value to provide the high-pass filter value.

Abstract: In a high resolution temperature sensor, first and second MEMS resonators generate respective first and second clock signals and a locked-loop reference clock generator generates a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals. A frequency-ratio engine within the MEMS temperature sensor oversamples at least one of the first and second clock signals with the reference clock signal to generate a ratio of the frequencies of the first and second clock signals.

Abstract: A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency fD×M, decimates data at the sampling frequency fs input from the integration calculation unit (10) in the last stage at a sampling frequency fD, and delays data obtained as a result of decimation by (M?1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency fD×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samp

Abstract: In an embodiment, a touch sensitive device includes touch interface having rows and columns and a signal generator for generating unique orthogonal signals on a plurality of the rows, respectively. A touch processor identifies touch on the touch interface by processing touch signals present on the columns, and outputting a stream of touch events. A decimator receives the stream of touch events including information as to a pressure of the touch event or the contact area of the touch event, selectively identifies one or more of the touch events in the stream, and outputs a modified stream of touch events for use by the touch sensitive device.

Abstract: Methods and devices for switching filters and medical apparatuses using the same are described. The method includes: detecting whether or not a frequency range of an input signal is changed from a first frequency range into a second frequency range; if changed, switching from a first filter to a second filter, and taking a sample value of the input signal at a current moment as an input value of the second filter at the current moment and sample values of the input signal at n moments before the current moment as input values of the second filter at the n moments, respectively, and taking output values of the first filter at m moments before the current moment as output values of the second filter at the m moments, to obtain an output value of the second filter at the current moment.

Abstract: A method for measuring waveform capture rate (WRC) of DSO based on average dead time measurement. First generating ramp signal or symmetric triangular wave signal as base signal, a trigger signal, the frequency which is higher than the nominal maximum waveform capture rate of the DSO under measurement; secondly, setting the parameters of DSO for measuring; then obtaining a plurality of test signals by delaying base signal K times with different delay time, for each test signal, inputting it the trigger signal simultaneously to DSO, calculating dead time between two adjacent captured waveforms according to their initial voltages, finally calculating waveform capture rate based on average dead times. The waveform capture rate obtained can effectively reflect the overall capturing capacity of DSO, more tellingly, the waveform capturing capacity of acquisition system of DSO.

Abstract: Encoding and decoding systems are described for the provision of high quality digital representations of audio signals with particular attention to the correct perceptual rendering of fast transients at modest sample rates. This is achieved by optimizing downsampling and upsampling filters to minimize the length of the impulse response while adequately attenuating alias products that have been found perceptually harmful.

Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.

Abstract: There is provided with a signal processing method. A filtering result is generated by performing spatial filtering on multi-dimensional data. Encoding result data is output by encoding the filtering result using a value at a pixel of interest of the filtering result and a value at a reference pixel located at a relative position with respect to the pixel of interest. The relative position of the reference pixel is decided in advance according to a characteristic of a spatial filter used in the spatial filtering step.

Abstract: In an embodiment, a touch sensitive device includes a touch interface having conductors and a signal generator for generating signals on the conductors. A touch processor identifies touch on the touch interface by processing touch signals present on the conductors, and outputting a stream of touch events. A decimator receives the stream of touch events and outputs a modified stream of touch events for use by the touch sensitive device, the modified stream of touch events may include predicted or estimated usable touch events.

Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.

Abstract: A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.

Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

Abstract: An apparatus for analyzing the condition of a machine having a part rotatable with a speed of rotation, includes an input for receiving an analog measurement signal indicative of a vibration signal signature having a vibration frequency and a repetition frequency; an A/D converter for generating a digital measurement signal dependent on the analog measurement signal, the digital measurement signal having a first sample rate, which is at least twice the vibration frequency; an enveloper for generating an enveloped signal indicative of the repetition frequency; a decimator for generating a decimated first digital signal dependent on the enveloped signal such that the decimated first digital signal has a reduced sample rate; an enhancer having an input for receiving the decimated signal, wherein the enhancer operates in the time domain to perform discrete autocorrelation for the decimated first digital signal so as to generate an enhancer output signal sequence; and an analyzer for performing a condition moni

Abstract: An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided.