Decimation/interpolation Patents (Class 708/313)
  • Patent number: 10750284
    Abstract: Improved techniques for presenting sound effects at a portable media device are disclosed. The sound effects can be output as audio sounds to an internal speaker, an external speaker, or both. In addition, the audio sounds for the sound effects can be output together with other audio sounds pertaining to media assets (e.g., audio tracks being played). In one embodiment, the sound effects can serve to provide auditory feedback to a user of the portable media device. A user interface can facilitate a user's selection of sound effect usages, types or characteristics.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 18, 2020
    Assignee: Apple Inc.
    Inventors: Aram Lindahl, Joseph Mark Williams, Muthya K Girish
  • Patent number: 10735022
    Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 4, 2020
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Wolfgang Hammel, Ulrich Neumayer
  • Patent number: 10644677
    Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Shawn Xianggang Yu
  • Patent number: 10615778
    Abstract: A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 7, 2020
    Assignee: Analog Devices, Inc.
    Inventor: James C. Camp
  • Patent number: 10581407
    Abstract: A Scalable Finite Impulse Response (“SFIR”) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 3, 2020
    Assignee: THE BOEING COMPANY
    Inventors: Kristina M. Skinner, Tyler J. Thrane, Jason A. Ching
  • Patent number: 10558293
    Abstract: In an embodiment, a touch sensitive device includes touch interface having rows and columns and a signal generator for generating unique orthogonal signals on a plurality of the rows, respectively. A touch processor identifies touch on the touch interface by processing touch signals present on the columns, and outputting a stream of touch events. A decimator receives the stream of touch events including information as to a pressure of the touch event or the contact area of the touch event, selectively identifies one or more of the touch events in the stream, and outputs a modified stream of touch events for use by the touch sensitive device.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 11, 2020
    Assignee: Tactual Labs Co.
    Inventors: Daniel Wigdor, Clifton Forlines
  • Patent number: 10505447
    Abstract: A power conversion apparatus can include: a power module configured to transfer an analog sensing signal corresponding to a current of an inductor and a voltage applied at both terminals of a capacitor, and to perform power conversion by driving a power semiconductor with a pulse-width modulation signal; and a controller configured to receive the analog sensing signal from the power module, to convert the analog sensing signal to a digital signal, to generate the pulse-width modulation signal, and to transfer the pulse-width modulation signal to the power module.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 10, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: ShinHye Chun, Hyung Bin Ihm
  • Patent number: 10474732
    Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 12, 2019
    Assignee: Dialog Semiconductor B.V.
    Inventor: Wessel Lubberhuizen
  • Patent number: 10467795
    Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 8, 2017
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
  • Patent number: 10454494
    Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 22, 2019
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Wolfgang Hammel, Ulrich Neumayer
  • Patent number: 10338263
    Abstract: In accordance with some embodiments, a method and apparatus for providing both a low-pass filter value and a high-pass filter value is presented. The combined filter receives an input value into a half-band finite impulse response (FIR) filter with an odd number of taps labeled 0 through N with corresponding filter coefficients labeled 0 through N where odd numbered filter coefficients are zero, the FIR filter providing a filter value. The median value from the FIR filter is digitally shifted to provide a half median value. The half median value is added to the filter value to provide the low-pass filter value and is subtracted from the filter value to provide the high-pass filter value.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 2, 2019
    Assignee: Metrotech Corporation
    Inventors: John Mark Royle, Stephen John Petherick
  • Patent number: 10247621
    Abstract: In a high resolution temperature sensor, first and second MEMS resonators generate respective first and second clock signals and a locked-loop reference clock generator generates a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals. A frequency-ratio engine within the MEMS temperature sensor oversamples at least one of the first and second clock signals with the reference clock signal to generate a ratio of the frequencies of the first and second clock signals.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 2, 2019
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Samira Zaliasl, Meisam Heidarpour Roshan, Sassan Tabatabaei
  • Patent number: 10243540
    Abstract: A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency fD×M, decimates data at the sampling frequency fs input from the integration calculation unit (10) in the last stage at a sampling frequency fD, and delays data obtained as a result of decimation by (M?1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency fD×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samp
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 26, 2019
    Assignee: AZBIL CORPORATION
    Inventor: Tetsuya Kajita
  • Patent number: 10133400
    Abstract: In an embodiment, a touch sensitive device includes touch interface having rows and columns and a signal generator for generating unique orthogonal signals on a plurality of the rows, respectively. A touch processor identifies touch on the touch interface by processing touch signals present on the columns, and outputting a stream of touch events. A decimator receives the stream of touch events including information as to a pressure of the touch event or the contact area of the touch event, selectively identifies one or more of the touch events in the stream, and outputs a modified stream of touch events for use by the touch sensitive device.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 20, 2018
    Assignee: Tactual Labs Co.
    Inventors: Daniel Wigdor, Clifton Forlines
  • Patent number: 10126339
    Abstract: Methods and devices for switching filters and medical apparatuses using the same are described. The method includes: detecting whether or not a frequency range of an input signal is changed from a first frequency range into a second frequency range; if changed, switching from a first filter to a second filter, and taking a sample value of the input signal at a current moment as an input value of the second filter at the current moment and sample values of the input signal at n moments before the current moment as input values of the second filter at the n moments, respectively, and taking output values of the first filter at m moments before the current moment as output values of the second filter at the m moments, to obtain an output value of the second filter at the current moment.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 13, 2018
    Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd.
    Inventors: Pei Wang, Wenyu Ye, Shen Luo
  • Patent number: 10119997
    Abstract: A method for measuring waveform capture rate (WRC) of DSO based on average dead time measurement. First generating ramp signal or symmetric triangular wave signal as base signal, a trigger signal, the frequency which is higher than the nominal maximum waveform capture rate of the DSO under measurement; secondly, setting the parameters of DSO for measuring; then obtaining a plurality of test signals by delaying base signal K times with different delay time, for each test signal, inputting it the trigger signal simultaneously to DSO, calculating dead time between two adjacent captured waveforms according to their initial voltages, finally calculating waveform capture rate based on average dead times. The waveform capture rate obtained can effectively reflect the overall capturing capacity of DSO, more tellingly, the waveform capturing capacity of acquisition system of DSO.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 6, 2018
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Qinchuan Zhang, Kuojun Yang, Lianping Guo, Hao Zeng, Jia Zhao, Jinpeng Song
  • Patent number: 10115410
    Abstract: Encoding and decoding systems are described for the provision of high quality digital representations of audio signals with particular attention to the correct perceptual rendering of fast transients at modest sample rates. This is achieved by optimizing downsampling and upsampling filters to minimize the length of the impulse response while adequately attenuating alias products that have been found perceptually harmful.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 30, 2018
    Inventors: Peter Graham Craven, John Robert Stuart
  • Patent number: 10090866
    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Suvam Nandi, Sundarrajan Rangachari
  • Patent number: 10050606
    Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Neha Bhargava, Ankur Bal
  • Patent number: 10038472
    Abstract: In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 31, 2018
    Assignee: Decawave Limited
    Inventors: Michael McLaughlin, Ciaran McElroy, Sinbad Wilmot, Tony Proudfoot
  • Patent number: 10026197
    Abstract: There is provided with a signal processing method. A filtering result is generated by performing spatial filtering on multi-dimensional data. Encoding result data is output by encoding the filtering result using a value at a pixel of interest of the filtering result and a value at a reference pixel located at a relative position with respect to the pixel of interest. The relative position of the reference pixel is decided in advance according to a characteristic of a spatial filter used in the spatial filtering step.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 17, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Daisuke Nakashima, Hiroshi Sato, Shunsuke Nakano
  • Patent number: 9990696
    Abstract: In an embodiment, a touch sensitive device includes a touch interface having conductors and a signal generator for generating signals on the conductors. A touch processor identifies touch on the touch interface by processing touch signals present on the conductors, and outputting a stream of touch events. A decimator receives the stream of touch events and outputs a modified stream of touch events for use by the touch sensitive device, the modified stream of touch events may include predicted or estimated usable touch events.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 5, 2018
    Assignee: Tactual Labs Co.
    Inventors: Ricardo Jorge Jota Costa, Clifton Forlines, Daniel Wigdor, Steven Leonard Sanders
  • Patent number: 9977753
    Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Naoki Mitsuishi, Seiji Ikari
  • Patent number: 9973171
    Abstract: A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 15, 2018
    Assignee: Azbil Corporation
    Inventor: Tetsuya Kajita
  • Patent number: 9964430
    Abstract: An apparatus for analyzing the condition of a machine having a part rotatable with a speed of rotation, includes an input for receiving an analog measurement signal indicative of a vibration signal signature having a vibration frequency and a repetition frequency; an A/D converter for generating a digital measurement signal dependent on the analog measurement signal, the digital measurement signal having a first sample rate, which is at least twice the vibration frequency; an enveloper for generating an enveloped signal indicative of the repetition frequency; a decimator for generating a decimated first digital signal dependent on the enveloped signal such that the decimated first digital signal has a reduced sample rate; an enhancer having an input for receiving the decimated signal, wherein the enhancer operates in the time domain to perform discrete autocorrelation for the decimated first digital signal so as to generate an enhancer output signal sequence; and an analyzer for performing a condition moni
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 8, 2018
    Assignee: S.P.M. INSTRUMENT AB
    Inventor: Lars-Olov Elis Hedin
  • Patent number: 9966932
    Abstract: An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 8, 2018
    Assignee: BEIJING SMARTLOGIC TECHNOLOGY LTD.
    Inventors: Donglin Wang, Leizu Yin, Yongyong Yang, Shaolin Xie, Tao Wang
  • Patent number: 9966933
    Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.
    Type: Grant
    Filed: May 21, 2016
    Date of Patent: May 8, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Volker Mauer, Martin Langhammer
  • Patent number: 9865275
    Abstract: The document relates to modulated digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the document discloses a method comprising accessing a time-domain audio signal and applying a first filter bank to the time-domain audio signal, thereby producing a first plurality of subbands of frequency-domain audio data representative of at least a part of the audio signal. The filter bank comprises an decimated modulated filter bank obtained from an asymmetric prototype filter. The method further comprises applying a second filter bank to at least a first subband of the first plurality of subbands of frequency-domain audio data, thereby producing a second plurality of subbands of frequency-domain audio data representative of at least a part of the audio signal. The second modulated filter bank comprises an asymmetric modulated filter bank which includes no decimation.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Dolby International AB
    Inventors: Per Ekstrand, Nicholas Luke Appleton
  • Patent number: 9846920
    Abstract: In an embodiment, a touch sensitive device includes a touch interface having rows and columns and a signal generator for generating unique orthogonal signals on a plurality of the rows, respectively. A touch processor is identifies touch on the touch interface by processing touch signals present on the columns, and outputting a stream of touch events. A decimator receives the stream of touch events, selectively identifies one or more of the touch events in the stream, and outputs a modified stream of touch events for use by the touch sensitive device.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 19, 2017
    Assignee: Tactual Labs Co.
    Inventors: Ricardo Jorge Jota Costa, Clifton Forlines, Daniel Wigdor, Steven Leonard Sanders
  • Patent number: 9831970
    Abstract: A selectable bandwidth filter has an analysis filter bank and a synthesis filter bank having M paths. A masking vector is disposed between the analysis filter bank and the synthesis filter bank. The masking vector enables select ones and disables unselected ones of the M paths, so as to define an output signal bandwidth.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: November 28, 2017
    Inventor: Fredric J. Harris
  • Patent number: 9820154
    Abstract: Methods, systems, and devices are described for making scaling adjustments with respect to a fractional subsystem in a wireless communications system. To handle the effects of scaling associated with fractional bandwidth systems, different adjustments may be made to maintain certain quality of service (QoS) requirements, for example. Scaling adjustments may include identifying a scaling factor for the fractional subsystem and a parameter and/or a timer associated with the fractional subsystem. An adjustment associated with the parameter and/or timer may be determined based on the scaling factor. The adjustment may be applied with respect to the parameter and/or timer for at least a portion of the fractional subsystem or another portion of the wireless communications system.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: November 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Soumya Das, Edwin C. Park, Bongyong Song, Ozgur Dural, Samir Salib Soliman
  • Patent number: 9608597
    Abstract: The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: March 28, 2017
    Assignee: The Swatch Group Research and Development Ltd
    Inventor: Massimiliano Bracco
  • Patent number: 9608598
    Abstract: The implementation of non-integer sample rate conversion and filtering of data sequences may be improved by performing both operations together with a system that includes a CIC filter and a control block that modifies internal states of the CIC filter. In one embodiment, input data samples provided at a first sample rate may be filtered by a CIC filter that includes a cascade of an integrating stage and a comb filter stage, each stage operating at a different sampling rate. A control block coupled to the CIC filter may modify at least one internal state of at least one of the integrating stage and comb filter stage of the CIC filter, wherein filtering by the CIC filter and modifying the at least one internal state causes the CIC filter to output data samples at a second sample rate unequal to the first sample rate.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: March 28, 2017
    Assignee: CIRRUS LOGIC, INC.
    Inventor: John L. Melanson
  • Patent number: 9484946
    Abstract: Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 1, 2016
    Assignee: NXP B.V.
    Inventors: Mattieu Deloge, Arnoud Pieter van der Wel
  • Patent number: 9391731
    Abstract: Aspects of the present invention include apparatus and methods for transmitting and receiving signals in communication systems. A beam splitter splits an optical signal into a plurality of signals. At least one QPSK modulator generates a plurality of QPSK modulated signals from the plurality of signals. An optical multiplexer combines the plurality of QPSK modulated signals into a multiplexed signal. The multiplexed signal is then transmitted.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: July 12, 2016
    Assignee: ZTE (USA) Inc.
    Inventors: Zhensheng Jia, Jianjun Yu, Hung-Chang Chien
  • Patent number: 9391634
    Abstract: Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of ?1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 12, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Sundarrajan Rangachari
  • Patent number: 9379687
    Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 28, 2016
    Assignee: ALTERA CORPORATION
    Inventors: Volker Mauer, Martin Langhammer
  • Patent number: 9374067
    Abstract: A method and system for the design and implementation of an optimally factored interpolated finite impulse response (IFIR) filter is presented. Techniques used to increase the implementation efficiency of the filter include joint sequencing of the filter stages, use of an nested IFIR filter, taming of a stage by relocation of that stage, fusing two or more stages together to form a single stage, and manual manipulation of a post-stage multiplier. IFIR filters using this approach may be realized as low pass filters or high pass filters, and in either analog or digital form.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 21, 2016
    Assignee: Pentomics, Inc.
    Inventors: Alireza Mehrnia, Alan N. Willson, Jr.
  • Patent number: 9362945
    Abstract: An Analog-Digital Converter (ADC) is provided. The ADC includes a plurality of sigma-delta modulators, a plurality of decimators, a plurality of differentiators, and a plurality of XOR operators. The plurality of sigma-delta modulators respectively convert analog signals to digital pulses. The plurality of decimators respectively convert a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling. The plurality of differentiators respectively differentiate signals converted at the second sampling rate to perform delta modulation. The plurality of XOR operators extract a signal component changing with respect to the delta-modulated signals. Therefore, the number of interface pins between a modem and an RFIC can be reduced.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Woo Lee
  • Patent number: 9362890
    Abstract: The present invention is directed to systems and methods which provide an improved compensation filter, as may be used with respect to a decimator, optimally designed using a convex optimization approach. Compensation filters of embodiments of the invention may, for example, be used with respect to a CIC decimator. In accordance with embodiments of the invention, compensation filters are designed with minimum order to approximate target frequency response in the target frequency bands. Additionally or alternatively, compensation filters of embodiments are optimally designed for passband drop and stopband attenuation improvement, such as to satisfy the specified peak ripple in the passband and/or to satisfy the specified peak errors over a set of target sub-bands in the stopband.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 7, 2016
    Assignee: Hong Kong Applied Science and Technology Research Institute Co. Ltd.
    Inventor: Zhao Shaohua
  • Patent number: 9337805
    Abstract: A new and more efficient filtering system (e.g., digital microphone decimation filter architecture system) is described. A key to this architecture is the use of two parallel filter paths. Each path operates at the output sample rate, and comprises a shorter FIR filter followed by a series of allpass stages (e.g., implementing IIR filters). The FIR filter is designed to remove all but the last octave of out-of-band noise. The allpass stages are designed such that when the two paths are summed together, the out-of-band noise for the final octave cancels out, leaving only the desired sign.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: May 10, 2016
    Assignee: Creative Technology Ltd
    Inventor: David Philip Rossum
  • Patent number: 9336579
    Abstract: A particular method includes generating a first result of a first integration operation performed on a first subset of elements of the plurality of elements. The first integration operation is associated with a first level of integration. The method includes generating a second result of a second integration operation performed on the first subset of elements. The second integration operation is associated with a second level of integration. The method further includes performing a third integration operation on a second subset of elements of the plurality of elements. The third integration operation is associated with the second level of integration. The third integration operation is performed based on the first result and the second result.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 10, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Qinwen Xu, Bo Zhou, Shuxue Quan, Junchen Du
  • Patent number: 9331711
    Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 3, 2016
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Wolfgang Hammel, Ulrich Neumayer
  • Patent number: 9292908
    Abstract: A system, method, and computer program product are provided for enhancing an image utilizing a hyper-clarity transform. In use, an image is identified. Additionally, the identified image is enhanced, utilizing a hyper-clarity transform. Further, the enhanced image is returned.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: March 22, 2016
    Assignee: NVIDIA Corporation
    Inventor: Michael Edwin Stewart
  • Patent number: 9268745
    Abstract: Method for determining at least one wavelet coefficient Ws(?) of a wavelet transform of a signal in which the mother wavelet of the transform has a support subdivided into J?1 intervals bound by (J+1) extremity points, and is defined by a polynomial of a maximum level N?1 on each interval. The method includes calculating all or some of the primitives of the signal of order k between 2 and N+1, at least at (J+1) points corresponding to extremity points of the intervals of the wavelet support dilated by a factor of s and translated by a time ?; calculating the convolution of said or each primitive sampled in this way with a respective succession of (J+1) coefficients Cik(s), dependent upon said wavelet; and determining the wavelet coefficient by calculating a linear combination of convolutions. Steps a) to c) are implemented by a processor configured or programmed in an appropriate manner.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 23, 2016
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Tetiana Aksenova
  • Patent number: 9264736
    Abstract: A encoding apparatus decomposes an original image into M (M is an integer and M>2) uniform subbands, and encodes the decomposed signals by using an embedded type entropy encoding method. A decoding apparatus receives the coded data encoded by the encoding apparatus, extracts N signals from the coded data from a low frequency component side in decomposed signals, decodes the N signals by using an entropy decoding method, and synthesizes the N decoded signals to obtain a decoded image of a resolution of N/M times (M and N are integers, and 1?N?M and M>2) that of an original image.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: February 16, 2016
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Takayuki Nakachi, Tomoko Sawabe, Tetsurou Fuji
  • Patent number: 9253640
    Abstract: A system and method for providing digital data content to a wireless device. Although a fee is typically charged for access to the digital data content, e.g., electronic books, the system and the method provides controlled access to this content for free while the wireless device is accessing the content in a specified location, e.g., a retail location. A content control server receives a request from the wireless device requesting access to the digital data content. The request is received over a secure connection, preferably a virtual private network (VPN). The content control server monitors how much of the digital data content has been provided to the wireless device, and/or an amount of time the wireless device has been accessing the digital data content. This content control server uses this monitored data to control, throttle, the provision of the digital data content to the wireless device.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: February 2, 2016
    Assignee: NOOK DIGITAL, LLC
    Inventors: Ted Cohn, Michael Reilly, Victoria Repice, Theresa Horner, Terri Pucin, Stanislav Tsvetanov, James Kung, David Mandelbaum
  • Patent number: 9214921
    Abstract: A position coordinate difference calculation section 5 calculates a position coordinate difference between a position coordinate of an output digital signal and a position coordinate of an input digital signal close to it. AN FIR coefficient memory 9 stores FIR coefficients of an FIR-LPF having such a characteristic as to cut off frequency components equal to or higher than ½ of an output sampling rate. When the position coordinate difference is input, the FIR coefficient memory outputs FIR coefficients corresponding to position coordinate differences between position coordinates of a certain number of input digital signals existing in the vicinity of the position coordinate of the output digital signal and the position coordinate of the output digital signal. AN FIR computation unit 3 performs FIR-LPF interpolation computation by using a certain number of the input digital signals and the FIR coefficients and obtains the output digital signal.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 15, 2015
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Yasuhiro Yamada, Yuichiro Koike
  • Patent number: 9176521
    Abstract: Embodiments related to signal generation for spectral measurements are described and depicted. In one embodiment, a signal generator for a spectral measurement is configured to generate a digital sigma-delta modulated signal. The signal generator has a digital output to feed the digital sigma-delta signal to a probe.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 3, 2015
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 9148125
    Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low-pass filter is presented. The filter utilizes capacitors and a gm-cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling and 6th-order voltage-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process-scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of this filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 29, 2015
    Assignee: Technische Universiteit Delft
    Inventors: Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski