Abstract: A sampling-rate conversion method receives N input channels which have been digitized at an input sampling rate, and converts the sampling rate of each input channel to produce N output channels at an output sampling rate. The method comprises computing a common FIR interpolating function which depends upon the input and output sample clocks and the instantaneous output time, and applying the common FIR interpolating function to all N input channels to compute all N output channels.

Abstract: A “Joint Bilateral Upsampler” uses a high-resolution input signal to guide the interpolation of a low-resolution solution set (derived from a downsampled version of the input signal) from low-to high-resolution. The resulting high-resolution solution set is then saved or applied to the original input signal to produce a high-resolution output signal. The high-resolution solution set is close to what would be produced directly from the input signal without downsampling. However, since the high-resolution solution set is constructed in part from a downsampled version of the input signal, it is computed using significantly less computational overhead and memory than a solution set computed directly from a high-resolution signal. Consequently, the Joint Bilateral Upsampler is advantageous for use in near real-time operations, in applications where user wait times are important, and in systems where computational costs and available memory are limited.

Abstract: There is described a pixel sensor converter for an image sensor array. In particular, a pixel sensor converter comprising: a delta-sigma converter comprising a modulator and a decimator. In some examples, the modulator is configured to be in communication with a detector, such as a photo-detector, and is configured to sample an analogue signal received from a detector at a particular sampling rate. The modulator is further configured to provide a bit stream of a particular bit rate. The provided bit stream corresponds to a sampled analogue signal. The decimator is in communication with the modulator, and is configured to receive and modify a bit stream provided from the modulator in order to provide a digital output signal. The provided digital output signal is representative of an analogue signal received at the modulator, but having a reduced bit rate than a corresponding bit stream provided by the modulator.

Abstract: Minimizing the power consumption in a field programmable gate array (FPGA) when used for convolution. The power consuming parts of the calculation are determined, and symmetry in those parts is exploited. For example, when multiplying by a filter have in common Values, the symmetry in the taps is detected. The values to be multiplied by the common tap values are edited and then the added value is multiplied. This minimizes the number of multipliers, thereby reducing power consumption.

Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.

Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

Abstract: A sample rate converter in which filtering is decomposed into phases as permitted by zero padding is described. The outputs of the phases are issued in the correct sequence to provide the resampled sequence.

Abstract: The invention relates to the improvement of the passband of physical systems. Use is made of a finite impulse response filter which is calculated in the following manner, on the basis of the behavior (observed or known) of the physical system: the impulse response a(t) of the physical system according to a temporal or spatial variable is determined; an impulse response b(t) of similar form but compressed according to the scale of the variable t in a ratio n and expanded in amplitude in the same ratio is calculated sample by sample, and the coefficients of a finite impulse response filter able to provide at its output the signal b(t) when the signal a(t) is applied to its input are calculated. This finite impulse response filter is incorporated into the physical system, preferably at the output, so as to improve the passband thereof in the ratio n.

Abstract: The invention discloses a finite impulse response (FIR) filter for processing a digital input signal to generate a digital output signal. The FIR filter has a tap amount N and a decimation ratio D. The FIR filter includes a first memory, a multiplier, and an accumulation module. For each input sample of the digital input signal, the first memory provides N/D corresponding tap coefficients from a plurality of tap coefficients in turn. The multiplier multiplies the input sample with the N/D corresponding tap coefficients in turn to generate N/D product values. The accumulation module adds the N/D product values to N/D previous accumulation values to generate N/D renewed accumulation values respectively. If one of the accumulation values has already accumulated N product values, the accumulation module outputs the accumulation value as an output sample of the digital output signal.

Abstract: A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

Abstract: A system and method for decimating a digital signal is disclosed. The system includes an input to receive digital data, a control input to receive a desired decimation rate, and an integrator stage responsive to the input. The system also includes a variable rate down sampling module responsive to the integrator stage and a differentiator stage responsive to the variable rate down sampling module. The down sampling module has a decimation rate that is dynamically adjustable based on the desired decimation rate.

Abstract: A discrete time filter includes a plurality of sampling cells and a first dummy sampling cell. Each of the sampling cells performs a current mode sampling operation based on current input to an input terminal in response to a corresponding one of a plurality of sampling clock signals and is reset in response to a corresponding one of the plurality of sampling clock signals and a first dummy sampling clocks. The first dummy sampling cell alternately performs with the first sampling cell the current mode sampling operation based on current input to the input terminal in response to the first dummy sampling clock signal and is alternately reset with the first sampling cell in response to the first sampling clock signal.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: A digital signal processor for interpolating a gain (coefficient) to be applied to a digital signal, the processor including: first memory means for storing a target gain coefficient; second memory means for storing a current gain coefficient; response determining means for determining an output gain coefficient based on the target gain coefficient and the current gain coefficient; means for storing the output gain coefficient in the second memory means in place of the current gain coefficient, to be used as the current gain coefficient in subsequent operations. In this way, a gain coefficient interpolator can be implemented using hardware rather than the previous DSP software approach.

Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.

Abstract: A method and system for the design and implementation of desensitized digital filters with droop correction. The desensitized digital filter includes a first filter configured to receive an input signal, a decimator or upsampler, and a modified desensitized half-band filter. The first filter introduces droop into the passband of the desensitized digital filter. The desensitized half-band filter has a transfer function F(z)=K(1+z?1)G(z) wherein K?0 is a scale factor, that is modified to omit a (1+z?1) factor block. The modified desensitized half-band filter compensates for the passband droop introduced by the first filter. The first filter may be a sinc filter, CIC filter, or filter having similar properties.

Abstract: Filter system embodiments are provided for realizing interpolation and decimation processes with interleaved filter structures. These interleaved structures enable the systems to obtain output data rates that exceed the highest operation rates of the system components.

Abstract: A method and an apparatus for digital up-down conversion using an Infinite Impulse Response (IIR) filter are provided. The method for digital up-down conversion for frequency conversion in a mobile communication system using plural frequency converts, includes IIR-filtering, by a magnitude response IIR filter having the same magnitude response as in Finite Impulse Response (FIR) filtering, an input signal and a stable filter coefficient calculated according to a Levinson polynomial; and receiving, by the magnitude response IIR filter, the IIR filtered signal, and performing IIR filtering by a phase compensation IIR filter having a filter coefficient compensating for a non-linear phase to a linear phase.

Abstract: The structure of a digital filter is provided through exponentiation of a polyphase digital filter. This exponentiation may be accomplished by determining an expression for the polyphase digital filter in terms of its polyphase components, and raising the expression for the polyphase digital filter to a power. The polyphase components are then arranged in a structure based on this exponentiated expression.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: A timing recovery circuit capable of enhancing the reliability of timing recovery in a receiver apparatus in a communication system that employs the scheme of modulating the amplitude of a carrier wave.

Abstract: A digital-to-analog converting system with sampling rate conversions includes an interpolator, S orders of operating and filtering units, an up-converting and down-converting circuit, and a signal processing circuit. The interpolator performs an N-times interpolation on a first digital input signal to generate a second digital input signal. Each order of the operating and filtering unit includes a K-times zero-padding circuit and a filtering circuit. The filtering circuit performs a filtering operation to generate a filtered digital input signal. The up-converting and down-converting circuit performs a B-times up-conversion and an A-times down-conversion on the filtered digital input signal to generate a fourth digital input signal. The signal processing circuit generates an analog output signal according to the fourth digital input signal.

Abstract: Certain aspects of the present disclosure provide methods for distributed sensing and centralized reconstruction of two correlated signals, modeled as the input and output of an unknown sparse filtering operation.

Abstract: The invention relates to sampled filters with finite impulse response, or FIR filters. According to the invention, there is proposed an FIR filter comprising a transconductance amplifier with controllable gain (AGM), at least one sampling capacitor (CE) intended to receive an output current (di) from the amplifier and to periodically accumulate the charges produced by N successive samples of this current, and means for controlling the gain of the amplifier to give the amplifier a desired individual gain for each of the N samples. The weighting of the coefficients of the finite impulse response filter is effected through the transconductance gain of the amplifier and not through the value of a capacitor.

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a subsampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively.

Abstract: Method and apparatus for decimating or sub-sampling image data which uses fixed delay intervals to accumulate a weighted sum of input samples. The accumulated sum is output at selected intervals, the interval determining the degree of decimation. The apparatus can take the form of a Finite Impulse Response (FIR) decimation filter. Decimation can be horizontal, vertical or temporal, and the decimation factor can be made non-integral.

Abstract: A block polyphase filter is constructed of a set of filter blocks having different filter functions, and being arranged for parallel processing of portions of an input sequence of signals. Signals of the input sequence are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. The filter blocks are arranged in groups, wherein output signals of the blocks in any one group are summed to produce an output signal of the filtered group. Output signals of all of the filter groups are multiplexed to provide an output signal sequence wherein the repetition frequency of the signals may be higher, lower, or equal to the repetition frequency of the input signal sequence depending upon the ratio of the number of filter groups to the number of filter blocks in the set of filter blocks.

Abstract: An apparatus for sub-band processing of an input signal includes an analysis filter bank, signal processors and a synthesis filter bank. The analysis filter bank includes first and second signal branches for decomposing the input signal into two sub-band signals. The first signal branch includes a decimation filter connected upstream of a down-sampling unit and a basis filter. The second branch includes an all-pass filter and a subtractor that is connected downstream of the all-pass filter and the basis filter in the first signal branch via an up-sampling unit and a subsequent interpolation filter. At least one of the decimation filter and the interpolation filter is an infinite impulse response filter, and the all-pass filter has a phase response that compensates for a phase response of at least one of the decimation filter and the interpolation filter.

Abstract: A novel and useful apparatus for and method of upsampling/interpolating a discrete-time input sample stream with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism is an effective implementation of a second order interpolator that eliminates the need for a conventional filter as the filtering action is effectively built into the mechanism. The upsampling mechanism takes the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator takes the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks effectively provides an additional order of interpolation. High frequency noise (i.e. dithering) is added to the differentiated samples in order to eliminate the spectral regrowth spurs that would otherwise appear in the output after rounding.

Abstract: The invention allows the interpolation factor, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as CLOCK1=2*CLOCK2). This relationship leads to degenerate cases where, in fact, there are only one or two clocks to consider rather than three. Furthermore, the invention allows for input data rates that are higher than the DSP clock rate. The invention also provides for an arbitrary time delay to be applied to the output signal.

Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.

Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.

Abstract: According to one embodiment, a first correlation calculator calculates a correlation between first pixel blocks, and detects as first reference pixels actual pixels contained respectively in the first pixel blocks with the highest correlation. A second correlation calculator calculates a correlation between second pixel blocks, and detects as second reference pixels actual pixels contained respectively in the second pixel blocks with the highest correlation. The first pixel blocks include pixels arranged in a plurality of rows and columns The second pixel blocks include pixels arranged in at least one row less than the rows of the first pixel blocks and a plurality of columns. An interpolation calculator calculates, when the first reference pixels are located perpendicular to the actual pixel lines, the pixel value of the interpolation pixel based on the second reference pixels.

Abstract: A digital signal processor receives samples of a first digital signal which is to be decimated and samples of a second digital signal which is to be interpolated. A digital signal processing engine performs a decimation function on samples of the first digital signal and an interpolation function on samples of the second digital signal on a time-shared basis. The digital signal processor has a first dual memory space for storing the samples of the first digital signal and a second dual memory space for storing the samples of the second digital signal. Outputs retrieved from a dual memory space are pre-added and applied to a multiplication and accumulation stage which operates on the pre-added outputs and a filter coefficient of a digital filter.

Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.

Abstract: A plurality of initial decimation filters are concatenated into an initial combined decimation filter. The initial decimation filters are assigned to a plurality of classes which associate the initial decimation filters with regions of an image to be predicted. An input signal is generated from the initial combined decimation filter and is weighted with a plurality of prediction filters. A correlation matrix and an observation vector are generated for the initial combined decimation filter from the input signal. An optimized combined decimation filter is extracted from the correlation matrix and observation vector. The optimized filter comprises a plurality of optimized decimation filters. The optimized combined decimation filter is de-concatenated into the plurality of optimized decimation filters.

Abstract: A method of adding high frequency content to an input signal to form an augmented signal, the method comprising the steps of: (a) providing an initial signal having a first predetermined lower spectral range; (b) utilizing the initial signal to form synthesized high frequency components of the initial signal; (c) filtering the initial signal with a low pass filter and filtering the synthesized high frequency components with a high pass filter (d) combining the filtered signals to form the augmented signal.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: A digital data bandpass filter process using digital signal processing processes raw digital data twice using distinct all-pass filters, wherein the two filters perform different frequency-dependent phase shifts of the digital content. The two filter output streams may be subtracted to remove out-of-band energy. The process produces lower levels of noise and conversion artifacts when used for filtering fixed-point data that may have low energy, and thus few non-zero bits, in the analog input signals, than conventional digital bandpass filters.

Abstract: An interpolation filter for interpolating a digital signal includes a cascade of template filters, each having an identical template transfer function A(z), which is arranged to receive and filter an input sequence representing the digital signal sampled at an input sampling rate. Ancillary circuitry is coupled to the cascade so as to produce first and second phase outputs. A multiplexer is arranged to multiplex the phase outputs in order to generate an output sequence having an output sampling rate equal to twice the input sampling rate.

Abstract: The present invention describes a system and method for general parameter estimation using adaptive processing that provides a performance that significantly exceeds existing reduced-rank schemes using reduced computational resources with greater flexibility. The adaptive processing is accomplished by calculating a reduced-rank approximation of an observation data vector using an adaptive decimation and interpolation scheme. The new scheme employs a time-varying interpolator finite impulse response (FIR) filter at the front-end followed by a decimation structure that processes the data according to the decimation pattern that minimizes the squared norm of the error signal and by a reduced-rank FIR filter. According to the present invention, the number of elements for estimation is substantially reduced, resulting in considerable computational savings and very fast convergence performance for tracking dynamic signals.

Abstract: A method is provided to reduce delay in signal processing of a digital control system. The method includes receiving outputs from a digital controller at a first frequency. A pre-load data value is then loaded into an accumulator register and output to a digital to analog converter (DAC). In one preferred embodiment, the pre-load data value is the value of the current digital controller output. In another preferred embodiment, the pre-load data value is the value of a previous digital controller output. The method additionally includes computing a step increment value that includes the difference between the most recent value output from the digital controller and the value output by the digital controller just prior to the most recent value. The step increment value is added to the pre-load data value in the accumulator register to create an augmented value, which is then output to the DAC.

Abstract: An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data.

Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Abstract: A coefficient compensating unit 33 calculates based on a loop point and a cross-fade point of impulse response coefficient data renewed compensation impulse response coefficients specified for a cross-fade period defined between the cross-fade point and an end point of the impulse response coefficient data, and stores the calculated impulse response coefficients in a compensation coefficient memory 34, wherein the cross-fade point corresponds to a beginning point of the cross-fade period in which a cross-fading is performed to smoothly connect the end point with the loop point.

Abstract: Method and apparatus for a complimentary discrete Fourier transform processor. An input signal is sampled, samples then being sequentially delayed, channelized, and processed. Synthesized outputs are provided in complimentary form. Channels are independent so as to allow for the application of gain, equalization and interference cancellation on a channel-by-channel basis. Both real and complex valued input signals may be processed. The invention optimizes computational efficiency.

Abstract: Efficiently implemented multi-channel integrators and multi-channel differentiators utilize a delay section in a single integrator or differentiator in lieu of parallel integrator or differentiator lines to handle multi-channel data flow and processing. The delay section functions like a shift register, greatly reducing the space and/or resources required for implementing the integrator or differentiator. Such integrators and differentiators can be used in multi-channel decimators, interpolators and numerically controlled oscillators in place of multiple instances of single channel integrators that have had to be used in earlier systems. These structures and devices can be implemented in programmable devices such as PLDs and similar devices, in which the delay section can be implemented in embedded memory in the device. Multi-stage decimators and interpolators can use multiple instances of an integrator and/or differentiator in series.

Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.

Abstract: A digital signal, x(n) (where n is an integer), is decimated by determining a signal vector, y(k), of size M by partitioning samples of the digital signal, x(n) according to sampling phases of the samples. The signal vector, y(k), is projected onto an N-dimensional sub-space, wherein N is an integer and N<M. Where the digital signal is generated by means of oversampling, it is possible to perform decimation in a way that optimizes the signal-to-noise ratio (SNR) of the decimated signal by suitably determining the sub-space onto which the signal vector will be projected.

Abstract: The digital filter has a first-stage decimation filter and a second-stage decimation filter. The second-stage decimation filter has a shifter that performs shift operation on a filter coefficient, a complementer that performs complementary operation on the filter coefficient, a reset circuit that resetting the filter coefficient, and an adder that adds values selected from the filter coefficient, a shift operation result from the shifter, and a complementary operation result from the complementer.