Abstract: Methods, systems, and devices are described for making scaling adjustments with respect to a fractional subsystem in a wireless communications system. To handle the effects of scaling associated with fractional bandwidth systems, different adjustments may be made to maintain certain quality of service (QoS) requirements, for example. Scaling adjustments may include identifying a scaling factor for the fractional subsystem and a parameter and/or a timer associated with the fractional subsystem. An adjustment associated with the parameter and/or timer may be determined based on the scaling factor. The adjustment may be applied with respect to the parameter and/or timer for at least a portion of the fractional subsystem or another portion of the wireless communications system.

Abstract: The implementation of non-integer sample rate conversion and filtering of data sequences may be improved by performing both operations together with a system that includes a CIC filter and a control block that modifies internal states of the CIC filter. In one embodiment, input data samples provided at a first sample rate may be filtered by a CIC filter that includes a cascade of an integrating stage and a comb filter stage, each stage operating at a different sampling rate. A control block coupled to the CIC filter may modify at least one internal state of at least one of the integrating stage and comb filter stage of the CIC filter, wherein filtering by the CIC filter and modifying the at least one internal state causes the CIC filter to output data samples at a second sample rate unequal to the first sample rate.

Abstract: The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.

Abstract: Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.

Abstract: Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of ?1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative.

Abstract: Aspects of the present invention include apparatus and methods for transmitting and receiving signals in communication systems. A beam splitter splits an optical signal into a plurality of signals. At least one QPSK modulator generates a plurality of QPSK modulated signals from the plurality of signals. An optical multiplexer combines the plurality of QPSK modulated signals into a multiplexed signal. The multiplexed signal is then transmitted.

Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

Abstract: A method and system for the design and implementation of an optimally factored interpolated finite impulse response (IFIR) filter is presented. Techniques used to increase the implementation efficiency of the filter include joint sequencing of the filter stages, use of an nested IFIR filter, taming of a stage by relocation of that stage, fusing two or more stages together to form a single stage, and manual manipulation of a post-stage multiplier. IFIR filters using this approach may be realized as low pass filters or high pass filters, and in either analog or digital form.

Abstract: An Analog-Digital Converter (ADC) is provided. The ADC includes a plurality of sigma-delta modulators, a plurality of decimators, a plurality of differentiators, and a plurality of XOR operators. The plurality of sigma-delta modulators respectively convert analog signals to digital pulses. The plurality of decimators respectively convert a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling. The plurality of differentiators respectively differentiate signals converted at the second sampling rate to perform delta modulation. The plurality of XOR operators extract a signal component changing with respect to the delta-modulated signals. Therefore, the number of interface pins between a modem and an RFIC can be reduced.

Abstract: The present invention is directed to systems and methods which provide an improved compensation filter, as may be used with respect to a decimator, optimally designed using a convex optimization approach. Compensation filters of embodiments of the invention may, for example, be used with respect to a CIC decimator. In accordance with embodiments of the invention, compensation filters are designed with minimum order to approximate target frequency response in the target frequency bands. Additionally or alternatively, compensation filters of embodiments are optimally designed for passband drop and stopband attenuation improvement, such as to satisfy the specified peak ripple in the passband and/or to satisfy the specified peak errors over a set of target sub-bands in the stopband.

Abstract: A new and more efficient filtering system (e.g., digital microphone decimation filter architecture system) is described. A key to this architecture is the use of two parallel filter paths. Each path operates at the output sample rate, and comprises a shorter FIR filter followed by a series of allpass stages (e.g., implementing IIR filters). The FIR filter is designed to remove all but the last octave of out-of-band noise. The allpass stages are designed such that when the two paths are summed together, the out-of-band noise for the final octave cancels out, leaving only the desired sign.

Abstract: A particular method includes generating a first result of a first integration operation performed on a first subset of elements of the plurality of elements. The first integration operation is associated with a first level of integration. The method includes generating a second result of a second integration operation performed on the first subset of elements. The second integration operation is associated with a second level of integration. The method further includes performing a third integration operation on a second subset of elements of the plurality of elements. The third integration operation is associated with the second level of integration. The third integration operation is performed based on the first result and the second result.

Abstract: In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the dif

Abstract: A system, method, and computer program product are provided for enhancing an image utilizing a hyper-clarity transform. In use, an image is identified. Additionally, the identified image is enhanced, utilizing a hyper-clarity transform. Further, the enhanced image is returned.

Abstract: Method for determining at least one wavelet coefficient Ws(?) of a wavelet transform of a signal in which the mother wavelet of the transform has a support subdivided into J?1 intervals bound by (J+1) extremity points, and is defined by a polynomial of a maximum level N?1 on each interval. The method includes calculating all or some of the primitives of the signal of order k between 2 and N+1, at least at (J+1) points corresponding to extremity points of the intervals of the wavelet support dilated by a factor of s and translated by a time ?; calculating the convolution of said or each primitive sampled in this way with a respective succession of (J+1) coefficients Cik(s), dependent upon said wavelet; and determining the wavelet coefficient by calculating a linear combination of convolutions. Steps a) to c) are implemented by a processor configured or programmed in an appropriate manner.

Abstract: A encoding apparatus decomposes an original image into M (M is an integer and M>2) uniform subbands, and encodes the decomposed signals by using an embedded type entropy encoding method. A decoding apparatus receives the coded data encoded by the encoding apparatus, extracts N signals from the coded data from a low frequency component side in decomposed signals, decodes the N signals by using an entropy decoding method, and synthesizes the N decoded signals to obtain a decoded image of a resolution of N/M times (M and N are integers, and 1?N?M and M>2) that of an original image.

Abstract: A system and method for providing digital data content to a wireless device. Although a fee is typically charged for access to the digital data content, e.g., electronic books, the system and the method provides controlled access to this content for free while the wireless device is accessing the content in a specified location, e.g., a retail location. A content control server receives a request from the wireless device requesting access to the digital data content. The request is received over a secure connection, preferably a virtual private network (VPN). The content control server monitors how much of the digital data content has been provided to the wireless device, and/or an amount of time the wireless device has been accessing the digital data content. This content control server uses this monitored data to control, throttle, the provision of the digital data content to the wireless device.

Abstract: A position coordinate difference calculation section 5 calculates a position coordinate difference between a position coordinate of an output digital signal and a position coordinate of an input digital signal close to it. AN FIR coefficient memory 9 stores FIR coefficients of an FIR-LPF having such a characteristic as to cut off frequency components equal to or higher than ½ of an output sampling rate. When the position coordinate difference is input, the FIR coefficient memory outputs FIR coefficients corresponding to position coordinate differences between position coordinates of a certain number of input digital signals existing in the vicinity of the position coordinate of the output digital signal and the position coordinate of the output digital signal. AN FIR computation unit 3 performs FIR-LPF interpolation computation by using a certain number of the input digital signals and the FIR coefficients and obtains the output digital signal.

Abstract: Embodiments related to signal generation for spectral measurements are described and depicted. In one embodiment, a signal generator for a spectral measurement is configured to generate a digital sigma-delta modulated signal. The signal generator has a digital output to feed the digital sigma-delta signal to a probe.

Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low-pass filter is presented. The filter utilizes capacitors and a gm-cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling and 6th-order voltage-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process-scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of this filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

Abstract: The high quality PCS communications are enabled in environments where adjacent PCS service bands operate with out-of-band harmonics that would otherwise interfere with the system's operation. The highly bandwidth-efficient communications method combines a form of time division duplex (TDD), frequency division duplex (FDD), time division multiple access (TDMA), orthogonal frequency division multiplexing (OFDM), spatial diversity, and polarization diversity in various unique combinations. The method provides excellent fade resistance. The method enables changing a user's available bandwidth on demand by assigning additional TDMA slots during the user's session.

Abstract: Polyphased input data is filtered. A number of delay lines are provided corresponding to the number of polyphases. Each delay lines stores a set of input data samples. Filter elements are provided for each delay line. The filter elements operate at a particular time on different subsets of the input data samples stored in the delay line. During a given time interval a number of new input data samples corresponding to the number of filter elements in the group of filter elements are shifted into the delay line. During a plurality of subintervals within the time interval, groups of filter coefficients are supplied to the group of filter elements. In each subinterval, all of the filter elements within the group receive the same set of filter coefficients, and output an output data sample. Output data samples from corresponding filter elements for different delay line are combined to produce filtered data.

Abstract: Systems and methods of determining motion vectors, such as for video encoding, are disclosed. In one example, motion vectors are determined for a current frame, using sampled pixel information from a reference frame. Sampled pixel information is obtained using a sampling pattern. The sampling pattern, in one example, includes subsampling pixels at different rates for horizontal and vertical directions. The subsampling rate can differ, based on an amount of motion represented by a matching block (e.g., the farther a match is found away from an origin of the block, the more subsampling can be done). In another example, a full pixel resolution is maintained proximal an original location of the block; as distance increases in one or more directions, subsampling can begin and/or increase. Sampled pixels can be stored. Interpolation of the sampled pixels can be performed and the sampled and resulting interpolated pixels can be used for comparison.

Abstract: A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M?1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.

Abstract: Systems and methods for sample rate tracking are provided. An example method includes computing an actual latency associated with an output sample from an output sample stream. The actual latency is calculated using a phase and a phase increment (conversion rate ratio). A measured latency is determined using an internal clock using a presentation time of the output sample, or an input sample from an input sample stream, or both. The measured latency is compared to the actual latency to generate a latency error. A successive phase increment can be determined based on the latency error by using a low-pass or adaptive filter to adjust the latency error.

Abstract: A digital radio signal is processed by converting an analog signal to a digital signal, decimating the digital signal using a CIC filter and supplying the decimated digital signal directly to an asynchronous sample rate converter (ASRC). The decimated signal is resampled in the ASRC and the ASRC output is supplied directly to a droop compensation filter to compensate the output of the ASRC. By carefully choosing the response of the CIC filter and the resample rate of the ASRC, aliased artifacts in the pass band can be kept below a threshold magnitude without the need for a channelization filter.

Abstract: A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2N clock periods are set as an operation-period unit, N?2. The second decimation filter unit receives the outputs from the first decimation filter unit and receives several feedback data of the second decimation filter unit by TD, so that the received data are distributed into the 2N clock periods for filtering and decimation and outputting by TD.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: A subtraction section subtracts from a received signal point a replica obtained by reflecting an influence of a propagation path state in a likely transmitted signal point. A calculation section calculates a metric for the received signal point and the replica from a value which the subtraction section calculates by subtracting the replica from the received signal point by the use of a linear interpolation formula obtained by separating a quadratic function at a power of 2.

Abstract: One embodiment of the present invention relates to a combined mixer filter circuit. The circuit includes a sampler, a plurality of filter branches, and a coefficient generator. The sampler is configured to provide a sampled signal by sampling a received signal at a specified rate. The plurality of filter branches has selectable filter coefficients. The plurality of filter branches are configured to receive the sampled signal and generate a mixed and filtered output signal without a separate mixer component. The coefficient generator is coupled to the plurality of filter branches. The coefficient generator is configured to assign filter coefficient values to the selectable filter coefficients to yield a selected mixing function for the mixed filtered output signal.

Abstract: An asynchronous sample rate converter prevents the folding back of a signal in the passband of an input sample rate into the passband of the output sample by adaptively controlling the decimation rate. The ASRC includes an adaptive decimation rate controller that selectably controls a decimation filter based on the ratio of the input sampling rate to the output sampling rate. By adaptively controlling the decimation rate in the ASRC, a significant amount of area and power is saved.

Abstract: Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value.

Abstract: A method for updating the processing capacity of an encoder or decoder to use a modulated transform having a size greater than a predetermined initial size is provided, particularly, where the encoders or decoders are for storing an initial prototype filter defined by an ordered set of initial size coefficients. A step is provided for constructing a prototype filter of a size greater than the initial size to implement the modulated transform of the greater size by inserting at least one coefficient between two consecutive coefficients of the initial prototype filter.

Abstract: Methods for sample rate conversion are provided that use a polynomial interpolator with minimax stopband attenuation. A method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a discrete polyphase index m. Another method for sample rate conversion of an input signal is provided that uses a time-varying polyphase filter having a continuous polyphase index ?. In these methods, an output time index is mapped to an input sample index and the polyphase index, the polynomial coefficients of a polyphase filter are computed using the polyphase index, and the polyphase filter is applied to an input sample at the input sample index to generate the output sample at the output time index.

Abstract: An image or other sample processor has a resampling filter adapted to provide output samples at an output sampling frequency which can be selected to be higher or lower than the input sampling frequency. The width of the resampling filter aperture is scaled according to either the input sampling frequency or the output sampling frequency so as to obtain the wider of the two possible filter apertures.

Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.

Abstract: The multi-branch rate change filter of the present invention achieves higher effective output rates by processing the input sample stream in two or more parallel filter branches with offset states.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: There is described a pixel sensor converter for an image sensor array. In particular, a pixel sensor converter comprising: a delta-sigma converter comprising a modulator and a decimator. In some examples, the modulator is configured to be in communication with a detector, such as a photo-detector, and is configured to sample an analogue signal received from a detector at a particular sampling rate. The modulator is further configured to provide a bit stream of a particular bit rate. The provided bit stream corresponds to a sampled analogue signal. The decimator is in communication with the modulator, and is configured to receive and modify a bit stream provided from the modulator in order to provide a digital output signal. The provided digital output signal is representative of an analogue signal received at the modulator, but having a reduced bit rate than a corresponding bit stream provided by the modulator.

Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

Abstract: A technique for performing parallel-input parallel-output infinite impulse response (IIR) filtering uses two parallel-input-parallel-output finite impulse response (FIR) filters. One FIR filter is used as a feed-forward filter and one FIR filter is used as a feed-back filter. The feed-back filter is coupled to delays and summers to allow the filter operations to be performed in parallel.

Abstract: Digital fine delay processing provides an accurate and continuous delay for an analog signal generated from source digital data. A digital processor generates processed digital data corresponding to a delayed analog signal having a desired delay relative to the analog signal represented by the source digital data. The processed digital data is directly derived from the source digital data by digital processing, and both digital data are processed by a reference clock, or by the same phase and cycle of the reference clock. The processed digital data is converted into a the delayed analog signal. Modifying coefficients in a convolution function performed by the digital processor changes the desired delay so that the delay is accurately controlled and is continuous. Since the entire process is digital, degradation of the delayed analog signal is minimal.

Abstract: Method of predicting capacity demands on a desired device used to support services for a number of subscribers within a market area having a number of devices. The method includes predicting the capacity demands as a function of historical capacity demands for the desired device and average subscriber capacity demands on the number of devices in the market area.

Abstract: An RF signal reception device including: a transposition device of signals of frequency fRF to a first intermediate frequency IF1<fRF; a first bandpass filter centered on IF1; a sampler at a frequency fs<IF1; a second discrete-time filter centered on a second intermediate frequency IF2=?·fs/M+fs/(M·n); a decimation device of a factor M; an analog-digital convertor to operate at a frequency fs/M; where ?, n and M are strictly positive real numbers chosen such that: ?<fs/(2·BWch·M), and BWch/2<fs/M·n), with BWch: bandwidth of a channel of the received RF signals.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A sampling circuit and a receiver are provided having a high flexibility of filter design and excellent characteristics for removing an interfering wave. Provided also are a sampling circuit and a receiver having a low level of the higher harmonic spurious. The sampling circuit includes a charge sampling circuit, which executes sampling of an input signal, and a plurality of charge sharing circuits connected in parallel to the output stage of the charge sampling circuit. The charge sharing circuits include a charge sharing circuit group having transmission functions different from one another, a synthesis circuit, which is arranged at the output side of the charge sharing circuit group and synthesizes the outputs of the charge sharing circuits, and a digital control unit, which outputs a control signal for controlling the operation of the charge sharing circuit group and the synthesis circuit.

Abstract: On a device having a maximum data rate, an interpolation filter can be configured in stages, with each stage may be broken into subfilters, which divides the output into phases. The ratio of the number of subfilters or phases in the final stage to the number of subfilters or phases in the initial stage is equal to the factor by which the data rate would otherwise increase. Thus for an interpolation factor of M, the output data rate can be kept the same as the input data rate by providing M subfilters, yielding M output phases each having an output rate equal to the input rate. The effective, or synthesized, output rate is M times the input rate. A decimation filter can be provided in the same way, with the effective input rate M times the output rate, even where the effective input rate would exceed the maximum data rate.

Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.

Abstract: A method and system for the design and implementation of filters is presented in which the filter's transfer function can be provided with a significant insensitivity to the filter's tap coefficient values. A desensitized digital filter includes a first halfband filter and a second filter coupled in cascade between an input of the digital filter and the output of the digital filter. In embodiments, the first filter has the transfer function F(z)=K(1+z?1)(1+z?1) wherein K?0 is a scale factor. The digital filter may also interact with an up-sampler or a down-sampler. A desensitized Hilbert transformer includes an FIR filter having filter-tap coefficients whose absolute values equal the absolute values of the coefficients of an FIR filter F(z) for which the product (1+z?1)F(z) is a halfband filter coupled in cascade with a second filter.