Abstract: A normalizer normalizes the power of a dither signal calculated by a power calculator based on the average power of a PCM signal in the range of 18 kHz to 20 kHz, wherein the average power is calculated by the power calculator. An oversampling processor oversamples the PCM signal with a quantization frequency of 44.1 kHz and a quantization word length of 16 bits, wherein the PCM signal is inputted from an input terminal at a sampling frequency of 2×44.1 kHz, and then supplies an output of the oversampling process to an adder. The adder adds the normalized output from the normalizer to the oversampling output from the oversampling processor, and then supplies the addition output to an oversampling processor.

Abstract: In the process of interpolation of video and/or audio digital data Sn, an interpolated value is chosen depending on whether or not an edge is detected. The edge detection is performed as follows. Let L=|S2n?S2n?2|, C=|S2n+2?S2n|, and R=|S2n+4?S2n+2|. An edge is detected when R>9(C+L) or L>9(C+R). A predictor P2n+1=K1S2n+K2S2n+2 provides the interpolated value for S2n+1 when an edge is detected, where K1=kL/(kL+kR), K2=kR/(kL+kR), where kL=1/(1+L), kR=1/(1+R) or kL=d2n+1,2n+2/(1+L) and kR=d2n,2n+1/(1+R). A different predictor (e.g. a cubic predictor) is used when no edge is detected. Other embodiments are also provided.

Abstract: A resampling address generator updates period data in a resampling period address register when the periods of input and output clocks are not stable, and generates a read address by supplying the output of a register to an accumulative adder. When the periods of the input and output clocks are stable, and a command is internally or externally received, the resampling address generator stops updating of the period data in the register, and generates the read address by supplying the output of the register to the accumulative adder. When the updating of the period data in the register is stopped, and a phase difference detector finds that the phase difference between the write address and the read address is outside a predetermined allowable range, the data in the register is updated based on correction data, and the read address is generated by supplying the output of the register to the accumulative adder.

Abstract: A system and methods for generating a variable rate filtered output using synchronous filters having the same filter sampling time, that avoids complexities of asynchronous filters. A system employs multiple filters that are staggered in time and set so that the output of one of the multiple filters is available whenever a secondary process requires state information. In another embodiment, the synchronous filters are programmable so as to change the filter sampling time. This configuration is possible when it is known that the prescribed time interval of the secondary process is longer than the filter sampling time and the prescribed time interval is an integer multiple of the filter sampling time. By using programmable filters, the number of filters required to accommodate a certain prescribed time interval can be minimized.

Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Abstract: The present invention provides a methodology, apparatus and system for resampling digital data utilizing a Fourier series based interpolation engine 104. A quick means to up-sample or down-sample data is provided without requiring computationally intensive processing. This is accomplished by utilizing low order coefficients of terms of a complete Fourier series expansion for a continuous signal. The summation of the expansion is limited to input samples immediately adjacent in time to the desired output. Generally speaking, the output is normally required to be a constant sampling rate, therefore, the input and output rates are related by an integer ratio. This ratio can be greater or smaller than one, providing up-sampling or down-sampling as appropriate. By employing the present invention, a DSP engine can be constructed that is adjustable to any ratio of sampling rates in a computationally efficient manner with low RMS error while preserving convolution through the resampling process.

Abstract: The present invention relates to an interpolation method and an interpolation apparatus for a digital audio signal or a digital image signal that has a predetermined sampling cycle and quantization bit length, and in particular, to an interpolation method and an interpolation apparatus that can effectively reduce quantization noise in a digital signal that is obtained by information compression. In the method and apparatus according to the present invention, it is made to perform interpolation processing of signal levels in a interpolation object interval in a given digital signal in accordance with a predetermined function curve, which monotonously changes, with the interpolation object interval including a discontinuous part that exists between one signal interval, where the same gradation levels continue, and another signal interval, which is adjacent to the one signal interval and in which the same gradation levels that are different continue.

Abstract: An apparatus and method for generating finite impulse response (FIR) filter coefficients are presented. The apparatus includes an address generator that multiplies a desired cutoff frequency f by an integer n to generate an address, a first look-up table that generates a sine function value of the address, a divider that divides the sine function value by n*pi, a multiplexer that generates an impulse response function value by selecting one of a value produced from the divider and 2*f based on an outside control signal, and a multiplier that multiplies the impulse response function value by a corresponding window function value to generate an nth filter coefficient for the FIR filter.

Abstract: Data other than inserted “0”s are selected by first selectors from among a plurality of data included in input data to which zero value interpolation is carried out at an interpolation circuit. Besides, coefficients by which the data selected by the first selectors should be multiplied are selected by second selectors. The data selected by the first selectors are multiplied by the coefficients selected by second selectors in multiplication circuits. Then, an adding circuit adds all of the multiplied results and outputs the added result as the desired filter characteristic.

Abstract: Parallel adaptive filters and filtering methods that enable processing of an input signal in a circuit that has an clock speed many times slower than the input rate of the input signal that is processed. A polyphase decimator structure processes a data stream requiring a low pass filtered bandlimited (low-rate) output that is used for high-rate output structures. The filters and methods break an input data stream into parallel paths that efficiently produce a bandlimited (decimated, low-rate) filtered output. Each of the parallel paths is processed at a decimated rate to provide a filtered output signals corresponding to a filtered version of the input signal.

Abstract: A 108-tap 1:4 interpolation FIR filter device for digital mobile telecommunication having a single bit input that employs a look-up table minimum scheme and a pipeline structure in which the size of the entire look-up tables is significantly reduced by dividing four coefficient groups into three parts, respectively, and effectively using the symmetry of the 108-tap filter coefficient and the symmetry within the look-up table.

Abstract: Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having (a) an FIR filter (4), which filters the digital input signal received with the symbol-clock data rate in such a way that, in the passband frequency range of the interpolation filter circuit (1), the power spectral density characteristic of the filtered digital output signal emitted by the interpolation filter circuit essentially coincides with a prescribed desired characteristic of the power spectral density PSDdes; (b) a resampling filter (6) connected downstream of the FIR filter (4) for increasing the clock data rate of the digital input signal filtered by the FIR filter (4); and having (c) an IIR filter (8), which is connected downstream of the resampling filter and filters the resampled digital signal emitted by the resampling filter (6) in such a way that, in the cutoff frequency range of the interpolatio

Abstract: Techniques related to a digital filter include at least one decimator disposed between an integrator section and a comb section such that the transfer function of the filter has split zeros. The resulting filter implementation employs considerable less silicon real estate than other prior art implementations with spread zeros, and has more design flexibility with improved resulting performance than the Hogenauer implementation.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: Interpolating filter banks are constructed for use with signals which may be represented as a lattice of arbitrary dimension d. The filter banks include M channels, where M is greater than or equal to two. A given filter bank is built by first computing a set of shifts ?i as D?1 ti, i=1, 2, . . . M?1, where ti is a set of coset representatives taken from a unit cell of the input signal lattice, and D is a dilation matrix having a determinant equal to M. A polynomial interpolation algorithm is then applied to determine weights for a set of M?1 predict filters Pi having the shifts ?i. A corresponding set of update filters Ui are then selected as Ui=P*i/M, where P*i is the adjoint of the predict filter Pi. The resulting predict and update filters are arranged in a lifting structure such that each of the predict and update filters are associated with a pair of the M channels of the filter bank.

Abstract: A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

Abstract: A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Abstract: A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 27 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A comb filter arrangement has an integrator that outputs an input value to a signal path. The signal path includes a delay stage for adjusting the input value using a delay factor, a decimator that converts the input value into a decimated output value using a non-integral factor, a differentiator that generates an intermediate output value from the input value, and an interpolation arrangement that receives the intermediate output value and generates a decimated sequence of the output value.

Abstract: A method including decimating a signal x using a filter f to obtain a decimated signal y, interpolating the decimated signal y to obtain a reconstructed signal z, determining a refinement factor s by decimating z and comparing decimated z to the decimated signal y, and determining an improved reconstructed signal r by using the refinement factor s, the filter f, and the reconstructed signal z is disclosed.

Abstract: A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

Abstract: Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated by interpolation from a table of oversampled values with the oversampling rate lower for outlying lobes of the impulse response.

Abstract: A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values.

Abstract: A method and apparatus to accelerate the evaluation of complex, computationally intense digital signal processing algorithms is disclosed. In one embodiment, a filter accelerator is connected in parallel with a conventional digital signal processor (DSP). The accelerator enhances the speed at which the DSP performs some filtering operations by calculating and maintaining a number of partial results based on a selected number of prior data samples. Each time the DSP receives a new data sample for filtering, the DSP makes use of one or more partial results from the accelerator to speed the calculation of the filtered result. Receipt of the new data sample causes the accelerator to recalculate the partial results, this time using the new data sample. The accelerator thus prepares for receipt of the subsequent data sample, freeing the DSP to perform other operations.

Abstract: Over-sampled timing signal jitter tolerance is improved in a q-times over-sampled architecture by phase-sampling the timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}. An output phase value &phgr;out=&phgr;in is initialized for each input sample &phgr;in. A difference vector di is derived for each input sample &phgr;in, where di=Fj(n,k). F denotes a vector operation, n is the number of input samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors ai di. The scaled difference vectors are summed: d j = ∑ i = 1 n ⁢ a i ⁢ d i .

Abstract: A trigonometric interpolator interpolates between two data samples at an offset &mgr;, where the two data samples are part of a set of N data samples. The trigonometric interpolator fits a trigonometric polynomial to the N data samples and evaluates the trigonometric polynomial at the offset &mgr;. The trigonometric inteprolator can be utilized for data rate changing and to correct mismatches between received samples and transmitted symbols. Simulations demonstrate that the trigonometric interpolater attains better performance than “conventional” interpolators, while simultaneously reducing the required hardware. In embodiments, the filter response of the trigonometric interpolator can be modified to achieve an arbitrary frequency response in order to enhance the interpolator performance. More specifically, the frequency response of the interpolator can be shaped to effectively correspond with the frequency response of the input data samples and the offset &mgr;.

Abstract: Methods and systems for filtering an analog signal sampled at a very high frequency and outputting a digital signal that has a very low sampling frequency to drive a material metering machine. The high frequency digital input signal is input to a first decimation element, which filters out the noise in the signal introduced by an analog-to-digital (A/D) converter and reduces the sampling frequency of the digital signal to a lower sampling frequency of 1200 hertz. The reduced rate digital signal is input into a second decimation element that contains several decimation filters, which reject the 60 hertz line noise and its harmonics while simultaneously reducing the sampling frequency of the digital signal to 10 hertz. The output of the second decimation element is then passed to a bank of selectable filters with sub-hertz cutoff frequencies to remove the machine noise from the material metering machine.

Abstract: A table-driven, integer-based method for approximating down sampling of wave data is disclosed. This method provides an efficient approximation of the desired down sampled wave data without a significant impact to overall system performance. Integer calculations are exploited by: (1) multiplying all values of ti by a large enough value to include all significant portions of the decimal value; (2) making all values of &Dgr;t integer values; and (3) using integer arithmetic for most calculations of &Dgr;t and ti. The following static integer tables assist in the final calculations: (1) T[ ], where each element contains the value of ti divided by &Dgr;t and multiplied by a large enough value, M, to place all significant decimal values to the left of the decimal; and (2) D[ ], where each element contains the number of samples of San to drop before arriving at a useable San and San+1 pair.

Abstract: A method for converting sample rates includes obtaining coefficients from a sample rate conversion coefficient table. In this method, the table is generated prior to the real-time sample rate conversion using LaGrange Interpolation based on the ratio of the input sample rate to the output sample rate.

Abstract: The present invention is directed to efficient and accurate filtering and interpolation techniques. Methods of the present invention reduce the number of required operations and reduce computational errors in the filtering and interpolation of discrete input signals.

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.

Abstract: The invention relates, in the field of subband decomposition, to the design of filter banks adapted to the input signal statistics. In most cases, two channel filter banks are iteratively applied over several levels of decomposition, the signals in the resulting subbands representing decimated and filtered versions of the input signal. According to the invention, it is proposed a perfect reconstruction critically decimated polyphase filter bank with a ladder structure, which adapts to the nonstationarities in the input signal.

Abstract: A data interpolating system by which the operating quantity can be decreased and no truncation error is produced. A data processor comprises a discrete value extracting section 10, a sampling function operating section 20, and a convolution operating section 30 so as to perform interpolation between discrete values. The discrete value extracting section 10 extracts just previous four value from successively inputted discrete data, and the sampling function operating section 20 calculates, when the data interpolating position is specified, the value of the interpolating position based on the distances between the data interpolating position and the discrete values by using a sampling function of local support which can be differentiated only once over the whole region. The convolution operating section 30 multiplies the values of the four sampling functions by the discrete values, and adds up the products, thus performing convolution operation and outputting the interpolation value.

Abstract: If there are N inputs into a decimate-by-M filter, a plurality (N/M) of decimate-by-N sub-filters is configured in parallel. Each decimation sub-filter outputs one sample, resulting in an aggregate of (N/M) output samples per processing cycle. The inputs to each sub-filter should be out of phase by M samples.

Abstract: A demodulation circuit for demodulating a frequency diverse complex modulated carrier comprises an A/D converter generating a series of samples representing the modulated carrier, a mixer operating to mix the series of samples with a sine wave of one fourth the sampling frequency represented by a series of sine wave values occurring at the sampling frequency, and a decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples.

Abstract: A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: A method and apparatus are disclosed for reducing aliasing between neighboring subbands in cascaded filter banks. An alias reduction filter bank is included to reduce the aliasing components between different subbands. Generally, the magnitude response and phase of the alias reduction filter bank is similar to the magnitude response of the synthesis filter bank of the first stage filter bank. The alias reduction filter bank filters and adds the signals from a set of M2 subbands from the M1 subbands of the first stage analysis filter bank. A higher frequency resolution is obtained after the alias reduction stage by a following analysis filter bank. The signals of these subbands are first fed into an alias reduction filter bank to reduce the aliasing.

Abstract: Efficient reconstruction of a discrete signal in a range from subband coefficients of multirate analysis filtering translates the range into required input coefficient ranges and minimizes computation and memory access.

Abstract: A mobile communication terminal device comprises: an A/D converter 101 for converting a transmitting analog signal into a transmitting digital signal, a digital filter 109 for applying a decimation process to a first output of a multiplexer 111 to send out to an outside if the first output is an output of the A/D converter 101 and for applying an interpolation process to a second output of a multiplexer 112 if the first output is an R-ch audio digital signal whereby the first output and the second output can be processed on time-division basis, a D/A converter 104 for converting the R-ch audio digital signal which is subjected to the interpolation process by the digital filter 109 into an analog signal, and a D/A converter 103 for converting any one of an L-ch audio digital signal and a receiving digital signal which are subjected to the interpolation process by the digital filter 109 into the analog signal.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.

Abstract: A method for producing a plurality of successive output data values defining an output curve that approximates an input curve defined by a plurality of input sample values, the output data values having a higher sampling frequency than the input sample values, the method comprising the steps of: pre-emphasizing the plurality of input sample values; defining successive and overlapping intervals including at least three of the pre-emphasized input sample values; interpolating a plurality of the output data values in an interpolation interval by calculating a moving average of a linear interpolation curve based on the at least three pre-emphasized input sample values, each of the output data values being influenced by the at least three pre-emphasized input sample values; and, emphasizing differently the influence of the at least three pre-emphasized input sample values for determining different ones of the output data values in the interpolation interval, whereby the pre-emphasizing step brings the output curve

Abstract: A method and apparatus for block-oriented pixel filtering reduces the number of hardware multipliers required for an image processing operation by increasing the speed of the pixel filter and rearranging the math operations. A sorter is employed in the line buffers so that defined groups of input pixel components are provided to the multipliers of the pixel filter. An accumulator is employed to receive products from the multipliers and assemble output pixels. The savings in gate count from reducing the number of multipliers is greater than additional costs, if any, of the sorter and other logic. The method and apparatus of the invention also simplify the addressing logic for the provision of scaling coefficients during an image processing operation.

Abstract: A method for generating a convergence correction curve from a plurality of successive output data values determined from a plurality of input sample values smaller in number than the plurality of output data values, the method comprising the steps of: defining successive and overlapping intervals including exactly three of the input sample values; interpolating a plurality of the output data values in an interpolation interval by calculating a moving average of a linear interpolation curve based on the three input sample values, each of the output data values being influenced by the three input sample values; emphasizing differently the influence of the three input sample values for determining different ones of the output data values in the interpolation interval; and, adjusting the input sample values to control convergence correction, whereby each incremental slope of the correction curve between adjacent output data values varies smoothly.

Abstract: A digital input is 8-fold oversampled, delay circuits 11−1 to 11−4 and multipliers/adders 12 to 15 perform a convolution arithmetic while multipliers/adders 4 to 10 process the oversampling data into predetermined digital basic waveforms, and continuous interpolation values can be obtained, thereby requiring no low pass filter which causes deterioration of phase characteristics, and suppressing an interpolation abortion error by setting finite interpolating functions. Furthermore, by obtaining apart of oversampling data as input data by using an AND gate 2, a subsequent process using the digital basic waveform and the convolution arithmetic can be performed in a very simple process.

Abstract: An input data word contains multiple abutting input data values An. The input data word is split into two intermediate data words into which respective high order portions and low order portions of the data values are written spaced apart by vacant portions. Each intermediate data word may then be subject to one or more data processing operations with bits of the results extending into the vacant portions without corrupting adjacent data values. Finally, the intermediate data words may be recombined to produce result data values.

Abstract: Methods and apparatus for implementing digital resampling circuits which create one or more bitstreams which include samples at desired rates, from an input bitstream having a fixed sample rate, are described. The resampling circuits of the present invention achieve the desired sample rates by performing digital interpolation on samples included in the input signal. The interpolation is performed using a filter, e.g., an all-pass infinite impulse response filter which produces an output as a function of a controllable signal delay.

Abstract: An input signal having a first sampling rate is converted to an output signal having a second sampling rate. This is done by obtaining an intermediate sampling value from the input signal and filtering the intermediate sampling value to obtain the output signal. The intermediate sampling value corresponds to a sample taken at the second sampling rate on a continuous-time representation of the input signal.