Abstract: An apparatus for readjustment of a sampling time in a radio receiver includes a component for determination of any sampling time error in a discrete-value received signal that emits a sampling time error signal. A filter arrangement is provided that includes a multi-rate filter that filters the sampling time error signal. A correction element receives the discrete-value received signal and the filtered sampling time error signal, and emits a discrete-value received signal whose timing has been corrected in accordance with the sampling time error.

Abstract: A multirate filter according to the invention comprises, a) an input unit (10) for receiving an input signal (Sin) and for providing a plurality of intermediate signals (IS1, IS2) in response to said input signal, b) a filter unit (20) coupled to the input unit (10), and c) an output unit (30) coupled to the filter unit (20), for generating an output signal (Sout). The filter unit (20) comprises at least a first and a second filter module (21, 22), with a transfer function H0(z) and a transfer function H1(z) respectively, which are mutually related according to the relations H0(z)=c0(HB(z)+M?,?HB(z)) and, H1(z)=c1(HB(z)+M?,?HB(z)) wherein, M?,?(HB(z))=?z?2?HB*(z?1), and wherein Formula (I), being the z-transform of hb[m]. The multirate filter comprises a combination unit (11) coupled to said filter modules (21, 22) for generating a first combination signal (Ssum) and a second combination signal (Sdiff).

Abstract: The invention concerns data processing by passage between different subband domains, of a first number L to a second number M of subband components. After determining a third number K, least common multiple between the first number L and the second number M: a) if K is different from L, it consists in arranging in blocs, by a serial/parallel conversion, an input vector X(z) to, obtain p2 polyphase component vectors (p2=KL); b) applying a square matrix filtering T(z) of dimensions K×K, to the p2 polyphase component vectors to obtain p1 polyphase component vectors for forming an output vector Y(z), with p1=K/M, and if the third number K is different from the second number M, providing a block arrangement by a parallel/serial conversion to obtain the output vector Y(z).

Abstract: Provided is a digital filter for radio communication processing capable of dynamically modifying the characteristic and simultaneously processing a plurality of systems. In the digital filter, calculation core groups (1010-1017) capable of modifying function are arranged and connected to one another by an input interface unit (102) and an output interface unit (103). When the communication mode is modified, the number of calculation resources to be used and its setting contents are decided according to the setting candidate of the filter characteristic required and the calculation resource empty state.

Abstract: A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing. The front-end processing includes a front-end input processing and a front-end output processing. The front-end input processing is coupled to an input of the NICAM processing and the front-end output processing is coupled to an output of the NICAM processing.

Abstract: The invention relates to a method for processing a digital input signal (x(i)) in a digital domain, comprising: -sampling a wideband of input frequencies of said digital input signal (x(i)) with a sampling frequency (fs), which decimates with a decimation factor (D), -linear shaping said sampled input frequencies with a configurable delay, -producing an output signal (y(i)) containing said linear shaped input frequencies, wherein the output signal (y(i)) has the same sampling frequency (fs) as said input signal (x(i)).

Abstract: A sampling rate conversion system reduces the signal processing burdens carried by cellular phones, headsets, and other electronic devices. Because the system consumes fewer resources to convert between signal sampling rates, the system may significantly reduce processing time and resource requirements in the device. As a result, the device may instead devote resources to performing other useful tasks, such as interacting with the user through a graphical user interface and performing selected processing tasks.

Abstract: A device generates coefficient data of an estimating equation for converting a first information signal to a second information signal. The device performs decimation on a teacher signal to generate a student signal and acquires plural training data items from the teacher signal corresponding to the second information signal and the student signal corresponding to the first information signal. For each training data item, a similarity determination unit acquires the similarity of the student signal with respect to the first information signal corresponding to a second information signal at a position of interest. Coefficient seed data, which are coefficient data of a generation equation including the similarity as a parameter, are determined using the training data items and the similarity. A coefficient data computing unit determines, based on the generation equation, coefficient data of the estimating equation using the coefficient seed data and a similarity value indicating the highest similarity.

Abstract: Techniques are described for sampling rate conversion in the digital domain by up-sampling and down-sampling a digital signal according to a selected intermediate sampling frequency. A prototype anti-aliasing filter that has a bandwidth with multiple factors is stored in memory. The techniques include selecting an intermediate sampling frequency to be an integer multiple of a desired output sampling frequency of a digital signal based on the factors of the prototype filter, and selecting a down-sampling factor to be the same integer associated with the selected intermediate sampling frequency. A filter generator generates an anti-aliasing filter for the selected down-sampling factor based on the prototype filter.

Abstract: Methods, systems and components for producing a scanning probe microscope (SPM) image. One method embodiment includes receiving sample data from a scanning probe microscope wherein said sample data comprises data sample many times per pixel of the SPM image to be displayed; selecting at least one decimation scheme from a plurality of different decimation schemes, for decimating the sample data to provide a single data value per pixel; and decimating the sample data, using the at least one selected decimation scheme.

Abstract: Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are used with a first delay module designated as a monitor delay module to monitor the clock edge transitions, while a second delay module is designated as a data delay module that provides a data output. A controller provides for incrementing or decrementing the tap delay of both delay modules to assure clock data falls at the center of the monitoring window as determined using the monitor delay module. The controller further selects between the two delay modules as to which provides data and which is used as for clock edge monitoring when the clock edge transitions drifts to an edge of the monitoring window.

Abstract: Asynchronous sampling rate converter using multistage oversampling with final stage polyphase filter coefficients approximated by polynomials of the filter index. The approximation polynomial coefficients occupy smaller memory than the polyphase filter coefficients being approximated.

Abstract: An interpolation function generation circuit is formed by cascade connecting a first FIR filter (10) having a numerical value string composed of a ratio “??, ?, ?, ?, ?, ??” (? is an emphasis coefficient and ? is a fixed value) as a filter coefficient and a second FIR filter (20) having a numerical value string composed of a ratio “1, 3, 5, . . . , m?1, m?1, . . . , 5, 3, 1” when the tap length is an odd number and “1, 3, 5, . . . , n?2, n?1, n?2, . . . , 5, 3, 1” if the tap length is an odd number (m and n are multiples of the oversampling). With only the two FIR filter (10, 20), it is possible to easily realize an interpolation function having a variable emphasis.

Abstract: A system and method for sampling signal in a Global Positioning System (GPS) receiver or Code Division Multiple Access (CDMA) communication device are provided. In general, decimation circuitry is provided. The decimation circuitry includes filtering circuitry that performs a number of integrations of an input signal for each code chip, where each the number of integrations has a different start time but has a common integration period equal to the duration of a code chip. Each of the integrations provides an output sample of the input signal for one of a corresponding number of chip-phases. The output samples for the chip-phases are provided to processing circuitry for numerous code chips. The processing circuitry processes the output samples corresponding to a select one of the chip-phases such that the sampling rate of the digital signal is reduced.

Abstract: Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

Abstract: A filter for high speed digital signal processing. In one embodiment the filter includes a linear, phase-B, interpolating cubic spline filter having a pre-filter section and an interpolating post-filter section. The pre-filter section may be formed to implement any one of a 1-4-1 cubic spline function, a 2-5-2 cubic spline function or a 1-2-1 cubic spline function. The post-filter may be formed using a plurality of running average filters arranged in a cascade (i.e., serial) fashion. The filter can be constructed using significantly fewer independent component parts for a given level of pass band and stop band performance criteria, as compared with a conventional finite impulse response (FIR) filter. The filter is thus ideally suited for implementation with very large scale integration (VLSI) technology, and in a wide variety of electronic devices where high speed digital filtering is required.

Abstract: An image scaling system for converting a sampling rate of an input video signal comprising input pixel data to produce a magnified or reduced output video image comprising output pixel data includes a first one-dimensional image scaler comprising a single-stage finite-duration impulse response (FIR) filter structure with poly-phase filter responses that receives and scales the input pixel data by a scaling factor in either a horizontal or vertical direction to produce output pixel data and a second one-dimensional image scaler comprising a single-stage FIR filter structure that is coupled in tandem to the first one-dimensional image scaler and scales by the scaling factor the output pixel data from the first one-dimensional image scaler in a direction perpendicular to that of the first one-dimensional image scaler to produce the magnified or reduced output video image.

Abstract: A method and system for time sharing N consecutive half-band decimating-by-2-filters using a single filter. Aspects of the method may comprise selecting a latched input signal and filtering, via a single decimating filter, the selected latched input signal to generate a first output signal. The method may also comprise latching the fed back portion of the first output signal. This latched signal may also be filtered by the single decimating filter to generate at least a second decimated output signal. A final output signal may be generated by latching at least one of the first output signal and the second decimated output signal. The final output signal may be latched utilizing at least one of a plurality of clocking signals.

Abstract: The present invention is a filter design that extracts information from a signal by employing D scale nonuniform sampling. In one embodiment a D scale multiresolution sampler, filter bank router, filter bank sampler controller, phase shifter, and consolidator constitute a maximal arrangement for a D scale FIR/IIR filter design.

Abstract: Methods for processing waveforms may include decimating an over-sampled waveform by identifying samples for which the sample's position within a data period indicates that is closest to a selected time within a data period. In some example applications, the selected time may be determined as a preferred time to sample the waveform within a data period. In an illustrative example, a sequence of samples representing an over-sampled waveform may be reduced by identifying a sample in each data period that is closest in time to the selected time. In another illustrative example, a sample within each data period may be identified if it falls within a range that is a function of the selected time within the data period and an integral ratio of a sample period to the data period. The identified samples may be used to reconstruct the original waveform with fewer samples than the over-sampled waveform.

Abstract: There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an arithmetic section that performs a predetermined convolution operation on the respective divided data of the respective amplitude data in a time-sharing mode and outputs the result, and a coupling section that couples the divided data output from the arithmetic section for each of the amplitude data.

Abstract: Described herein is a method and system for sampling rate conversion. A clamped cubic spline interpolator (CCSI) may be utilized to interpolate or decimate a source signal to provide samples at times based on a sink rate. The source clock and sink clock may be driven by independent oscillators, and may therefore drift independently. A rate tracking algorithm may monitor the relative drift and adjust the conversion of the source signal to track the sink rate.

Abstract: Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.

Abstract: Systems, techniques, and machine-readable instructions for coupling simulations with filtering. In one aspect, a method is for coupling simulations with filtering of data. The method includes generating a first visual rendition of a first collection of display data and a second visual rendition of a second collection of display data, receiving user input changing a variable rendered in the second visual rendition, and representing an impact of the change to the variable on the first visual rendition of the first collection of display data. The second collection of display data is a product of filtering the first collection of display data.

Abstract: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Abstract: A method of searching for a best-match decimation vector of decimation factors for non-uniform filter bank, the best match vector allowing perfect or near-perfect reconstruction of an input signal of the non-uniform filter bank, the method including the steps of: a) selecting a partial decimation vector having a number, l, of decimation factors, where l does not exceed a maximum number, K, of decimation factors of said best-match decimation vector; b) testing said l decimation factors to determine whether said partial decimation vector satisfies a feasibility criterion; c) testing a least common multiplier value of said l decimation factors to determine whether said least common multiplier value is greater than a predetermined value; d) testing a maximum decimation value, Dmax, of said partial decimation vector to determine whether Dmax is less than one; e) testing a minimum decimation value, Dmin, of said partial decimation vector to determine whether Dmin is greater than one; and f) if said feasibility crit

Abstract: There are included a three-tap FIR calculating part (2) that multiples data outputted from three taps on a tapped delay line by respective filter factors comprising a ratio value sequence of “?1, m, ?1”; and an n-tap FIR calculating part (3) that multiples data outputted from n taps on a tapped delay line by respective filter factors comprising a predetermined value sequence. Interpolation values can be determined by use of sum-of-products calculations using various factor sequences comprising various values of m and n. The three-tap FIR calculating part (2) is adapted to determine interpolation values by use of the sum-of-products calculations that always use only three values. In this way, the circuit scale can be reduced and further the calculation process can be simplified, thereby achieving a high-rate interpolation process.

Abstract: An adaptive proportional integral control loop determines a ratio of the input sampling rate to the output sampling rate for use in asynchronous sample rate conversion. An input counter counts input samples and its output is sampled at the output sampling rate by a latch. The output of the latch is passed through a closed loop circuit comprising variable gain and integrator sections.

Abstract: The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples created or mixed using any of the standard audio frequencies in the set H={8, 11.025, 22.05, 44.1, 48, 96, and 192} kHz and played back using any other frequency from the set H. The synchronizer can be used where audio data are streamed or otherwise broadcast from, for example, the Internet, along with a system timestamp, and where this timestamp needs to be matched to the local audio clock for proper play-back. The same synchronizer can also be used for audio/video or video only synchronization.

Abstract: Methods and apparatus are provided for decimated interpolated clock/data recovery (ICDR) to perform asynchronous sampling of a received signal. A received signal is converted to a plurality of digital samples at a downsampled rate that is lower than a rate of the received signal. The plurality of digital samples are interpolated using a plurality of parallel interpolation filters operating at the downsampled rate. An output of each parallel interpolation filter is applied to a corresponding data detector operating at the downsampled rate to generate digital data. An estimate of a timing error is generated based on the digital data. The timing error values are processed to generate an interpolation phase value that is applied to the parallel interpolation filters. A recovered clock is optionally generated, having edges corresponding to a desired synchronous sampling period.

Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

Abstract: An interpolation FIR filter uses a coefficient to generate an interpolation value of a first and second input value. The interpolation FIR filter has several arithmetic units, an adder, and a divider. The nth arithmetic unit outputs a partial product by selecting one of the first and second input values according to an nth bit of the coefficient, and multiplying the selected input value by 2(n?1). The adder outputs a sum all the partial products and the first input value. The divider divides the sum by 2m, wherein m is an amount of the arithmetic units.

Abstract: A digital filter combination for interpolating primary sample values of a sampled signal using an mth-order discrete-time filter and a kth-order continuous time interpolation filter, with m?3 and k?2, wherein the discrete-time filter forms n secondary sample values from at least m+1 primary sample values at equal time intervals, with n?m, and the continuous-time interpolation filter forms from at least part of the n secondary sample values an interpolated value whose temporal position with respect to that of the primary sample values is predeterminable by a normalized interpolating instant dp=tin/T, where tin is the absolute interpolating instant, and T is the period of the primary sampling rate.

Abstract: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

Abstract: A simple to implement sample rate conversion system consisting of an input/output data flow controller, interpolation coefficient generation, and output data flow control to generate the converted data stream. Sample rate conversion may be done at real time video rates, without restrictions on the conversion ratios.

Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.

Abstract: A signal processing system includes a digital sample rate converter to convert a signal sampled at a first sampling frequency into a corresponding signal sampled at a second sampling frequency. In at least one embodiment, the sample rate converter includes a digital sample rate conversion filter. The digital sample rate conversion filter includes a digital filter that models a continuous time filter such as a low pass RC filter and generates filtered samples. The digital sample rate conversion filter also includes an interpolation filter that determines samples between the digital filtered samples. A sample selector selects the samples generated by the interpolation filter at the second sampling frequency. In at least one embodiment, the sample selector determines when to generate interpolated samples and the amount of time offset from an adjacent sample generated by the digital filter.

Abstract: The present invention relates to an interpolation FIR (finite impulse response) filter having multiple data rates in a mobile communication system, and a method of filtering data using the same. In the method of filtering data using the interpolation FIR filter, a first filter uses an FIR low pass filter that restricts a band to satisfy a bandwidth corresponding to a data spectrum mask required in the mobile communication system. The other filters use interpolation FIR halfband filters that are implemented by a small number of taps. Accordingly, the interpolation FIR filter having multiple data rates can be easily implemented, and can be easily applied to the mobile communication system that transmits and receives data having various data rates.

Abstract: There provided is a low-cost, high performance sampling rate conversion calculating apparatus which achieves both a low delay characteristic required for conversational voice data and high quality required for audio data in a concurrent manner. A first digital signal processing section outputs conversational voice data, which requires the low delay characteristic, in accordance with a sampling frequency of an output terminal (111). A second digital signal processing section outputs audio data, which requires the high quality, rather than the low density characteristic, in accordance with the sampling frequency of the output terminal (111). An adder section (107) adds the conversational voice data outputted from the first digital signal processing section and the audio data outputted from the second digital signal processing section and outputs the added data from the output terminal (111).

Abstract: A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm.

Abstract: A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the plurality of calculating devices in synchronization with a clock signal. When a decimation ratio is n, filter coefficients which are sequentially shifted by an n number of filter coefficients are read out from the plurality of coefficient memories, and multiplied with a signal in the multipliers of the calculating devices, and results of the multiplications are accumulated in the accumulators to be output.

Abstract: A finite impulse response (FIR) decimation filter includes an input to receive an oversampled signal, and an output to provide an output signal having a sampling rate that is reduced by a decimation factor relative to the oversampled signal. The decimation factor corresponds to a sum of one and an order N of the FIR decimation filter. A supply is used to provide filter coefficients for the FIR decimation filter. One multiplication and addition entity is used in generating the output signal. The multiplication and addition entity is configured to perform multiplication by bit shifting and/or addition.

Abstract: An architecture for a cascaded digital filters comprises independently programmable controlling registers and independent interpolating factors; a digital to analog converter for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter property (filters order, coefficient symmetry, half-band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.

Abstract: The present invention relates to a data processing apparatus, a method and apparatus for encoding, a method and apparatus for decoding, and a program, that allow a reduction in an algorithm delay. An interpolator 51 produces interpolated PCM data by performing R-times oversampling on original PCM data. A frame encoder 54 fetches a predetermined number of samples of the oversampled data as one frame, encodes the oversampled data on a frame-by-frame basis, and outputs resultant encoded data. A frame decoder 55 decodes the encoded data on a frame-by-frame basis at a rate R times higher than a predetermined normal rate. A decimator 56 decimates data obtained as a result of the decoding such that the number of samples is reduced to 1/R of the number of sampled included in the original data. The present invention is applicable, for example, to an IP telephone system.

Abstract: Embodiments of a signal processing system, a method, and fractionally modulated digital delay lines are generally described herein. Other embodiments may be described and claimed. In some embodiments, a fractional address is generated by adding a delay value to a fractional offset value, and input sample values are interpolated based on a fractional portion of the fractional address. A write operation may be performed to the integer portion of the fractional address for each sample period using the interpolated input sample values. Adjusted addresses may be generated when addresses are either skipped of duplicated.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: A method of determining filter coefficients for filter stages in a multirate digital filter device to achieve a desired filter response. The method includes the step of determining a first plurality of evenly spaced sample points representing the desired response function on a logarithmic time scale, such that the sample points of the first plurality have an increasing spacing when viewed in a linear time scale. The method further includes the step determining filter coefficients for each filter stage from an associated group of sample points out of the first plurality of sample points.

Abstract: An over-sampling unit 2 that over-samples inputted sequential respective sample values to be N sample values and an FIR filter unit 3 that applies filter processing to the over-sampled respective sample values using coefficients formed by a sequence of numerical values (1/2N2, 3/2N2, 5/2N2, . . . , (N?3)/2N2, (N?1)/2N2, (N?1)/2N2, (N?3)/2N2, . . . , 5/2N2, 3/2N2, 1/2N2} (when N is an even number) are provided. Consequently, original discrete sample points are smoothly interpolated along a spline curve according to over-sampling and FIR filter processing and, in a frequency characteristic of an output, a pass band is limited to 2/N of a sampling frequency.

Abstract: A method for representation, interpolation and/or compression of data includes identifying a two-dimensional interpolation function s(z) based on a sampling function a(z). A Cauchy integral theorem is applicable for the interpolation function s(z). The interpolation function s(z) is used for the representation, interpolation and/or compression of the data.

Abstract: In the digital filtering of an input signal (3), which has been produced by interpolation of a pilot signal (2), under certain circumstances numerous values originating from the past have to be stored. In order to reduce the storage space required for these and the associated power consumption, the values of the input signal (3), which are needed for computation of the values of an output signal (4), are compressed and stored in compressed form. More particularly here the values of the input signal (3) are divided into symbol periods, in which a coherent range of memory values, which are the only data-carrying values in the symbol period, occurs in each case. These values are stored together with the length of the symbol period, so that although each symbol period can be described completely, storage space is reduced.