Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: A system for tracking selected wave parameters from a received sinusoidal wave with noise and methods for making and using the same. The method includes performing a multi-track double integral analysis of the sinusoidal wave with noise and creating time dependent outputs. These time dependent outputs may be analyzed mathematically to determine the amplitude, frequency and/or phase of the wave with reduced noise. In one embodiment, the method may employ multiple passes through double integral analysis. The method advantageously can measure output sinusoidal wave parameters with reduced noise, measurements that are close to theoretical noise reduction limits.

Abstract: It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.

Abstract: A hardware-friendly transform method in codecs for plenoptic point clouds. Given that existing video-based point cloud compression codec (V-PCC) is based on multimedia processor video codecs embedded in System-on-Chip (SoC) mobile devices, the remaining V-PCC steps should be as efficient as possible to ensure fair power consumption. In this sense, the method seeks to reduce the complexity of the transform, using integer transforms and imposing limits on the number of distinct transform dimensions, in which these limits are designed in order to minimize the losses of coding efficiency.

Abstract: A fault detector for detecting a fault in a digital processing circuit configured to transform an input data set to an output data set based on an energy conserving function. The fault detector includes an input sum of absolute squares circuit configured to determine an input sum of absolute squares value of the input data set, which has a predetermined length; an output sum of absolute squares circuit configured to determine an output sum of absolute squares value of the output data set; and an energy conservation check circuit configured to identify a fault in the digital processing circuit if a comparison based on the input sum of absolute squares value and the output sum of absolute squares value does not meet a predetermined energy conservation criteria.

Abstract: An OFDM (orthogonal frequency division multiplexing) transmitter includes an inverse fast Fourier transform circuit, which, in operation, generates, based on digital input data, a complex time-varying digital signal having real and imaginary components; and a multiplexer adapted to generate a time-multiplexed digital signal by time-multiplexing one or more of the real components with one or more of the imaginary components.

Abstract: A system for determining the frequency coefficients of a one or multi-dimensional signal that is sparse in the frequency domain includes determining the locations of the non-zero frequency coefficients, and then determining values of the coefficients using the determined locations. If N is total number of frequency coefficients across the one or more dimension of the signal, and if R is an upper bound of the number of non-zero ones of these frequency coefficients, the systems requires up to (O (R log(R) (N))) samples and has a computation complexity of up to O (R log2(R) log (N). The system and the processing technique are stable to low-level noise and can exhibit only a small probability of failure. The frequency coefficients can be real and positive or they can be complex numbers.

Abstract: The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method including at least one step for: obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2p points on a signal coming from the input signal, the integer p being greater than or equal to 1, applying an inverse discrete Fourier transform to M/2p points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

Abstract: A high-frequency signal stimulator system has at least two mutually independent data producers, signal processing and a signal generator. The at least two mutually independent data producers are each configured to produce at least one data packet describing a high-frequency signal to be produced. The signal processing is configured to extract a signal of the data packet produced by the first of the at least two mutually independent data producers and contents of the data packet produced by the second of the at least two mutually independent data producers. The signal generator is configured to produce a high-frequency signal based on the extracted contents.

Abstract: Conventional real-time spectrum analyzers have a degree of technical complexity in the hardware which increases disproportionately as the analysis bandwidth increases for Fourier transformations of the measured sampling values. When using high analysis bandwidths, a detailed resolution is not needed of each analyzed individual frequency on the time plane at the same time; instead, detection of the presence of short pulses can be important as well. For this application, mixing sampling values on the time plane using a variable auxiliary frequency allows the sampling rate to be reduced, in that the bandwidth is maintained but a compression is carried out on the time plane. A very high time resolution which far exceeds the capabilities of conventional real-time spectrum analyzers can additionally be achieved overall for the analysis bandwidth, the time resolution then being computationally assignable to the individual frequencies for signal forms, in particular pulses, which occur in practice.

Abstract: In one embodiment, a computer-implemented method of discrete Fourier transform (DPT), FFT, or DCT computations on a system comprising a processor is described herein. In one example, the method includes receiving, with the processor, input complex samples from memory of the system, determining input vectors based on the received input complex samples, determining a DFT radix p of p macro blocks based on the input vectors, determining p independent DFT-L vectors based on the p macro blocks with L being based on p, and generating p DFT-N output vectors without reordering or shuffling output data based on the p independent DFT-L vectors.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A putative circuit design is represented as a set of movable blocks of predetermined size which must fit into a bounding box, with a plurality of subsets to be interconnected by wires. A total weighted wire length is determined as a function of coordinates of centers of the movable blocks by summing a half perimeter wire length over the plurality of subsets, and a density penalty is determined as a convolution of an indicator function of the current placement and a convolution kernel, via incremental integer computation without use of floating point arithmetic. Blocks are moved to minimize a penalty function which is the sum of the total weighted wire length and the product of a density penalty weight and the density penalty. The process repeats until a maximum value of the density penalty weight is reached or the density penalty approaches zero.

Abstract: Systems and methods for predicting feature values in a matrix are disclosed. In example embodiments, a server accesses a matrix, the matrix having multiple dimensions, one dimension of the matrix representing features, and one dimension of the matrix representing entities. The server separates the matrix into multiple submatrices along a first dimension, each submatrix including all cells in the matrix for a set of values in the first dimension. The server provides the multiple submatrices to multiple machines. The server computes, using each machine, a correlation between values in at least one second dimension of the matrix and a value for a preselected feature in the matrix, the correlation being used to predict the value for the preselected feature based on other values along the at least one second dimension. The server provides an output representing the computed correlation.

Abstract: A telecommunications system may include a measurement receiver to confirm the presence of a MIMO signal prior to decoding signals to avoid decoding spectrum that does not include MIMO signals. The measurement receiver may determine a fast Fourier transform (FFT) spectrum for asynchronous wideband digital signals received from two or more ports. The measurement receiver may determine an average FFT spectrum based on the determined FFT spectrum and identify a bandwidth of signals present in the average FFT spectrum. The measurement receiver may identify the MIMO signals present in the bandwidth of signals and decode only the identified MIMO signals.

Abstract: Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain.

Abstract: A method of ultrasound imaging and a corresponding ultrasound scanner are provided. The method includes the steps of receiving an echo signal induced by an ultrasonic plane wave transmission from a transducer of an ultrasound scanner, resampling the echo signal in time domain and/or space domain, performing a spectrum zooming on a band of interest (BOI) of an input signal, performing a Fourier transform on a result of the spectrum zooming, and generating an ultrasound image based on a result of the Fourier transform. The input signal is generated based on the resampling of the echo signal.

Abstract: A computer-implemented method is provided that includes identifying an input dataset formatted as an input matrix, the input matrix including a plurality of rows and a plurality of columns. The computer-implemented method also includes dividing the input matrix into a plurality of input matrix blocks. Further, the computer-implemented method includes distributing the input matrix blocks to a plurality of different machines across a distributed filesystem, and sampling, by at least two of the different machines in parallel, at least two of the input matrix blocks. Finally, the computer-implemented method includes generating at least one sample matrix based on the sampling of the at least two of the input matrix blocks.

Abstract: A system for providing information about electrical devices in a residence includes a power measurement device, an electrical device identification component, and a notification component. The power measurement device measures characteristics of electrical power in one or more electrical power lines in the residence. Based on the measured electrical characteristics, the electrical device identification component determines electrical signatures specific electrical devices at the residence that are receiving electrical power through the electrical power lines, associates the electrical devices with a device type, and groups the electrical devices into zones of the residence. Based on power consumption by the specific electrical devices, the notification component determines events or conditions associated with specific electrical devices (for example abnormal usage, device failure, excess power consumption).

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying an original matrix by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between a row order and a column order. The second circuit may be configured to generate a given matrix by reading the intermediate matrices from the memory in a second order that alternates between the column order and the row order.

Abstract: A system and method prevent interference caused by images resulting from mixing an incoming periodically modulated RF signal with multiple LO signals generated by a LO in a receiver system. The method includes determining tone frequencies of multiple tones and determining tone spacing between adjacent tones in the periodically modulated RF signal using a known period of modulation of the periodically modulated RF signal; identifying a sampling rate of an ADC of the receiver system; determining a DFT record size of samples provided by the ADC based on at least the tone spacing and the ADC sampling rate; and determining LO frequencies of the multiple LO signals based on at least the DFT record size and the ADC sampling rate, such that images created by respectively mixing the determined LO frequencies with portions of the periodically modulated RF signal avoid interfering with direct mixing components of the plurality of tones.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for augmenting neural networks with an external memory. One of the methods includes receiving a plurality of high-dimensional data items; generating a circulant embedding matrix for the high-dimensional data items, wherein the circulant embedding matrix is a matrix that is fully specified by a single vector; for each high-dimensional data item, generating a compact representation of the high-dimensional data item, comprising computing a product of the circulant embedding matrix and the high dimensional data item by performing a circular convolution of the single vector that fully specifies the circulant embedding matrix and the high dimensional data item using a Fast Fourier Transform (FFT); and generating a compact representation of the high dimensional data item by computing a binary map of the computed product.

Abstract: An apparatus and method for sharing a function logic between functional units and a reconfigurable processor are provided. The apparatus for sharing a function logic may include a storage which is configured to store data which is received from two or more functional units in order to share one or more function logics, and an arbitrator which is configured, based on a scheduling rule, to transmit the data stored in the storage into the function logic.

Abstract: Device and method for writing Discrete Fourier transform (DFT) samples in a memory in a reorder stage, the memory includes memory banks, each having a dedicated address generator. The method includes: dividing the DFT samples into R(reorder) equally sized segments, where R(reorder) is the radix value of the reorder stage of the DFT; checking whether a number of butterfly computations per cycle of a reorder stage of the DFT operation times R(reorder), denoted as P, is not larger than the number of segments; if P is larger than the number of segments: further dividing the segments or sub-segments into X equally sized sub-segments, where X is a radix value of a next stage of the DFT operation until P is not larger than the number of sub-segments; and mapping the sub-segments to the memory, each in a separate row, with an offset that includes segment offset and sub-segment offset.

Abstract: A telecommunications system is provided that includes a unit for communicating channelized digital baseband signals with remotely located units. The channelized digital baseband signals include call information for wireless communication. The unit includes a channelizer section and a transport section. The channelizer section can extract, per channel, the channelized digital baseband signals using channel filters and digital down-converters. The transport section can format the channelized digital baseband signals for transport together using a transport schedule unit for packetizing and packet scheduling the channelized digital baseband signals. A signal processing subsystem can control a gain of uplink digital baseband signals, independently, that are received from the remotely located units prior to summing the uplink digital baseband signals.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying a sequence of original matrices by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between (a) a first of the intermediate matrices in a row order and (b) a second of the intermediate matrices in a column order. The second circuit may be configured to (i) read the sequence of the intermediate matrices from the memory in a second order that alternates between (a) the first intermediate matrix in the column order and (b) the second intermediate matrix in the row order and (ii) generate a sequence of transform matrices by multiplying the intermediate matrices as read from the memory by another predetermined matrix.

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract: A fixed-coefficient variable prime length recursive discrete Fourier transform system includes a pre-processing device, a real-part computation device, an imaginary-part computation device and a post-processing device. The pre-processing device receives N digital input signals and performs order permutation operation to generate first and second temporal signals, wherein N is a prime number. The real-part computation device receives the real part of the first and second temporal signals and performs discrete cosine/sine transform to generate third and fourth temporal signals. The imaginary-part computation device receives the imaginary part of the first and second temporal signals and performs discrete cosine/sine transform to generate fifth and sixth temporal signals.

Abstract: A discrete Fourier calculation device includes a twiddle factor table storage unit that stores therein a twiddle factor table that associates twiddle factors with phases of the corresponding twiddle factors; a correction value specifying unit that specifies first and second correction values for correcting a phase of an input signal in accordance with an amplitude of the input signal; a generating unit that corrects the phase of the input signal by using the specified first and second correction values to generate first and second phases; an addition unit that adds an arbitrary phase corresponding to an arbitrary twiddle factor stored in the twiddle factor table, to each of the generated first and second phases; and a rotation calculation unit that acquires, from the twiddle factor table, first and second twiddle factors corresponding to the first and second phases and sums the acquired first and second twiddle factors.

Abstract: An approach is provided for correlation of a signal over time and frequency. The signal is correlated with a bit sequence over time instances and certain frequency offsets, wherein sub-segments of the signal are correlated with sub-segments of the bit sequence to generate a correlation factor associated with each signal sub-segment. The correlation factors are coherently combined to generate a final correlation factor, wherein a respective phase shift (for each frequency offset) is applied to each correlation factor to generate a set of frequency adjusted correlation factors, and the frequency adjusted correlation factors of a respective set are combined to generate the final correlation factor over the signal sub-segments, resulting in the matrix of final correlation factors over time and frequency. A signal parameter estimation is performed, based on the matrix of final correlation factors, to determine a highest correlation value for the signal over the frequency offsets.

Abstract: Implementations related to power reduction in physical layer wireless communications are disclosed.

Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

Abstract: A method and device for performing spectrum analysis of a signal in a plurality of frequency bands with respective different frequency resolutions. The method includes a data acquisition step and a subsequent data evaluation step for every frequency band. The data acquisition step and the subsequent data evaluation step proceeds cyclically and continuously for every frequency band of the spectrum analysis. The corresponding device for performing spectrum analysis of a signal cyclically stores a scanning sequence of the signal for every frequency band in one circular buffer each. A discrete Fourier transformer uses the cyclically stored scanning sequences to calculate the spectral values pertaining to the respective frequency band.

Abstract: A low-complexity inverse transform computation method, comprising following steps: firstly, analyzing an end-of-block (EOB) point in a matrix of a block; next, determining whether a bottom-left corner coefficient or a top-right coefficient before said EOB point is zero, and if it is zero, reducing further size of said matrix; then, determining an adequate operation mode to reduce computational complexity; and finally, realizing 2-D inverse transform through simplified 1-D inverse transforms. An inverse transform process of said method mentioned above is capable of lowering computation amount, reducing burden and computational complexity of a decompression system, and shortening effectively computation time of said 2-D inverse transform, such that it is applicable to inverse transforms of various video and still image codecs.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: The present invention relates to a signal transmitting apparatus, a method thereof, and an inverse fast Fourier transform (IFFT) apparatus for a signal transmitting apparatus. A signal transmitting apparatus according to an embodiment of the present invention receives data, and performs inverse fast Fourier transform (IFFT) on the data on the basis of a twiddle factor for shifting output data by the size of a cyclic prefix. In addition, the signal transmitting apparatus sequentially stores data corresponding to the size of the cyclic prefix starting with initial data among the transformed data, and generates an OFDM symbol on the basis of the stored data and the transformed data. According to the embodiment of the present invention, it is possible to efficiently reduce a time delay and a memory use amount when a cyclic prefix is added at a transmitting end, without changing the size of hardware and power consumption.

Abstract: A signal receiving apparatus includes: a processing unit configured to carry out Fourier transform on Fourier-transform data serving as a Fourier-transform object and carry out Fourier transform on inverse-Fourier-transform data serving as an inverse-Fourier-transform object; and a control unit configured to output pieces of data obtained as a result of the Fourier transform carried out on the Fourier-transform data in an order, in which the pieces of data have been obtained, in a process of outputting the pieces of data and output other pieces of data obtained as a result of the Fourier transform carried out on the inverse-Fourier transform data by rearranging the other pieces of data in a process of outputting the other pieces of data.

Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.

Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.

Abstract: Provided are methods and systems for digital signal processing by applying an improved SDFT technique for eliminating ripple in side lobes of a resulting spectrum. An exemplary method may comprise receiving an input signal which includes a number of discrete samples taken at regular time intervals. The input signal may then be filtered by a modified comb filter according to the sliding DFT technique to generate first and second filtered signals, the second filtered signal being filtered using a different filter coefficient. The first and second filtered signals may be processed by a first and second plurality of resonators respectively, according to the sliding DFT technique, to generate respective first and second SDFT output signals. The first and second SDFT output signals may then be selectively summed to generate a resulting output signal.

Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.

Abstract: Systems and methods are described herein for applying a predefined functional shape to coefficients of a discrete Fourier transform of a waveform. The waveform may based, at least in part, on an electro-cardiogram (ECG). The predefined functional shape may be parabolic, and may be defined on a logarithmic scale. The application of a predefined functional shape may allow a more accurate reconstruction of a waveform to be generated at a lower sampling rate.

Abstract: Phase information of a rotation system is obtained by a) reading the present output value Sk, (k=0, . . . , N?1) of the sensor at a sequence of N points of time during a first period of a periodic modulation function (PHA, PHB, PHC, PHD), b) storing read output values Sk or a value derived from this output value at least temporarily in a memory, c) extracting information on the phase of the rotating system, wherein said information is extracted based on evaluation of a function of the type, wherein=and, and d) sampling and storing sequentially further output values Sk, k=N, N+1, . . . of the sensor at corresponding points of time in the following periods of the periodic modulation function (PHA, PHB, PHC, PHD). Each reading information on the phase of the rotating system based on the function is extracted and a controller device (100) for application of this technique.

Abstract: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.