Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Abstract: A computer implemented method includes supplying stimuli to an organism, measuring brain activity of the organism responsive to the stimuli and producing a brain feature activity map characterizing the brain activity. The operations of supplying, measuring and producing are repeated for different stimuli to form a brain feature activity map database. New stimuli are received. New stimuli features are mapped to a projected brain activity map. The projected brain activity map is compared to the brain feature activity map database to identify similarities and dissimilarities between the projected brain activity map and entries in the brain feature activity map database to designate a match. The new stimuli are characterized based upon the match.

Abstract: This application provides a signal processing method and apparatus, and a coherent receiver. The signal processing method includes: obtaining P real-number signals; performing at least number theoretic transform NTT processing on the P real-number signals to obtain P transform-domain first real-number signals; performing at least clock recovery on the P transform-domain first real-number signals to obtain P transform-domain second real-number signals; performing at least polarization compensation and inverse number theoretic transform INTT processing on the P transform-domain second real-number signals to obtain m time-domain complex-number signals X and m time-domain complex-number signals Y; and performing phase recovery and decoding on the m time-domain complex-number signals X and the m time-domain complex-number signals Y to obtain bit signals.

Abstract: Apparatus and methods for training a neural network accelerator using quantized precision data formats having outlier values are disclosed, and in particular for storing activation values from a neural network in a compressed format for use during forward and backward propagation training of the neural network. In certain examples of the disclosed technology, a computing system is configured to perform forward propagation for a layer of a neural network to produced first activation values in a first block floating-point format. In some examples, activation values generated by forward propagation are converted by the compressor to a second block floating-point format having a narrower numerical precision than the first block floating-point format. Outlier values, comprising additional bits of mantissa and/or exponent are stored in ancillary storage for subset of the activation values. The compressed activation values are stored in the memory, where they can be retrieved for use during back propagation.

Abstract: The present invention herein is a method and apparatus that significantly limits the effect of high frequency (“HF”) interferences on acquired electro-physiological signals, such as the EEG and EMG. Preferably, this method comprises of two separate electronic circuitries and steps or electronics for processing the signals. One circuit is used to block the transmission of HF interferences to the instrumentation amplifiers. It is comprised of a front-end active filter, a low frequency electromagnetic interference (“EMI”) shield, and an isolation barrier interface which isolates the patient from earth ground. The second circuit is used to measure the difference in potential between the two isolated sides of the isolation barrier. This so-called “cross-barrier” voltage is directly representative of the interference level that the instrumentation amplifier is subjected to. This circuit is used to confirm that the acquired signals are not corrupted by the interference.

Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.

Abstract: A gateway in a computing system for interfacing a host with a subsystem for acting as a work accelerator to the host, the gateway having: an accelerator interface for enabling the transfer of batches of data to the subsystem at pre-compiled data exchange synchronisation points attained by the subsystem; a data connection interface for receiving data to be processed from storage; and a gateway interface for connection to a third gateway. The gateway is configured to store a number of credits indicating at least one of: the availability of data for transfer to the subsystem at a pre-compiled data exchange synchronisation point; and the availability of storage for receiving data from the subsystem at a pre-compiled data exchange synchronisation point. The gateway uses these credits to control whether or not synchronisation barrier is passed by transmitting synchronisation requests upstream to the third gateway or simply acknowledging the requests received.

Abstract: Exemplary aspects are directed to or involve a radar transceiver to transmit signal and receive reflected radar signals via a communication channel. The exemplary method includes radar receiver data processing circuitry that may be used to differentiate a subset of representations of the received signals. This differentiation may be used to select signals that are more indicative of target(s) having a given range than other ones of the received signals. The received signal's representations may then be compressed by using variable-mantissa floating-point numbers having mantissa values that vary based, at least in part, on at least one strength characteristic of the respective representations.

Abstract: A fast Fourier transform (FFT) circuit of an audio processing device configured to perform an N-points FFT and including a memory circuit and a butterfly operation unit circuit is provided. The butterfly operation unit circuit reads two points input data from the memory circuit, performs a butterfly operation for the two points input data according to a twiddle factor to generate two points output data, and writes the two points output data into the memory circuit. The butterfly operation unit circuit includes a multiplier and a plurality of adders/subtractors. The multiplier sequentially multiplies real or imaginary coefficients of one of the two points input data by real or imaginary coefficients of the twiddle factor in multiple clock cycles. The multiplier performs a multiplication once in each clock cycle. The adders/subtractors perform addition/subtraction, such that the butterfly operation unit circuit generates the two points output data.

Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.

Abstract: There are provided methods and apparatus for performing modified cosine transformation (MDCT) with an analysis/synthesis windowing function, using an analysis windowing function having a meandering portion which passes a linear function in correspondence of at least four points.

Abstract: The present invention discloses a data scheduling register tree structure for radix-2 FFT architecture. The operation method of the proposed invention, there is no need for the Random Access Memory (RAM) to store the data; instead, shift registers with some multiplexers are enough to perform the memory operation with less hardware. There are three steps in the FFT computation such as input storage, data processing and output retrieval. The data processing step is further configured in four different operations. The number of operation mainly depends upon the size of the FFT, which is equal to log2N modes. During each operation, the DSRT changes its structure and these structures are basically MDC (Multi-path Delay Commutator) structures.

Abstract: A range Doppler angle detection method executed by a range Doppler angle detection device includes steps of: receiving a first sensing signal and a second sensing signal; performing 1D Fast Fourier Transform (FFT) and 2D FFT to the first sensing signal for calculating one first 2D FFT map; performing the 1D FFT and the 2D FFT to the second sensing signal for calculating one second 2D FFT map; picking up one column of the first 2D FFT map and one column of the second 2D FFT map according to a given Doppler index; performing the 3D FFT to the picked column of the first 2D FFT map and the picked column of the second 2D FFT map for calculating a range Doppler angle. Therefore, a computation loading of the gesture recognition function can be reduced.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which reduces the maximum point size the FFT can process but saves power and reduces latency. For example, the FFT can have selection circuitry (e.g., multiplexers) disposed between each stage that permits the input data to either bypass the previous stage(s) or the subsequent stage(s), depending on the architecture of the FFT. The bypassed stages can then be deactivated to conserve power.

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

Abstract: A transcranial magnetic stimulation (TMS) treatment system is provided. The system includes a sensor device that senses EEG signals from a subject through one or more leads and a server device configured to receive EEG data corresponding to the subject. The server includes an analysis module configured to process the EEG data and determine a personalized resonant brain frequency and a minimum neuronal activation threshold of the subject based at least in part on EEG data corresponding to one or more leads of the sensor device. The analysis module is also configured to determine a TMS treatment protocol where the treatment protocol includes at least a frequency based on the personalized resonant brain frequency and an amplitude based on the minimum neuronal activation threshold. The system also includes a treatment device configured to deliver a TMS treatment to the subject based on the TMS treatment protocol received from the server.

Abstract: The present invention, herein is a method and apparatus that significantly limits the effect of high frequency (“HF”) interferences on acquired electro-physiological signals, such as the EEG and EMG. Preferably, this method comprises of two separate electronic circuitries and steps or electronics for processing the signals. One circuit is used to block the transmission of HF interferences to the instrumentation amplifiers. It is comprised of a front-end active filter, a low frequency electromagnetic interference (“EMI”) shield, and an isolation barrier interface which isolates the patient from earth ground. The second circuit is used to measure the difference in potential between the two isolated sides of the isolation barrier. This so-called “cross-barrier” voltage is directly representative of the interference level that the instrumentation amplifier is subjected to. This circuit is used to confirm that the acquired signals are not corrupted by the interference.

Abstract: A method is described for locating and/or classifying at least one object, a radar sensor that is used including at least one transmitter and at least one receiver for radar waves. The method includes: the signal recorded by the receiver is converted into a two- or multidimensional frequency representation; at least a portion of the two- or multidimensional frequency representation is supplied as an input to an artificial neural network, ANN that includes a sequence of layers with neurons, at least one layer of the ANN being additionally supplied with a piece of dimensioning information which characterizes the size and/or absolute position of objects detected in the portion of the two- or multidimensional frequency representation; the locating and/or the classification of the object is taken from the ANN as an output.

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

Abstract: A data management system is provided for facilitating in-memory indexing of data based on certain data access modes. The data management system includes an indexing module for indexing data stored in a data memory as a first data index. The first data index is further provided with a first data access mode, wherein the first data access mode enables the first data index to update itself by providing data write privileges to the first data index. The data management system further includes a synchronizing module for synchronizing a second data index with the first data index, wherein the second data access mode is provided with second data access mode to enable external systems to query data. The data management system further includes an index handling module for interchanging data access modes of the first and the second data indexes based on pre-defined rules.

Abstract: A resource allocation method and an apparatus in a communications system are provided. A terminal receives resource allocation indication information, where the resource allocation indication information is used to determine a subband corresponding to an allocated resource. The terminal receives second configuration information, where the second configuration information indicates one of a plurality of configurations of the first frequency domain resource unit size corresponding to the subband. And the terminal determines a size of a first frequency domain resource unit corresponding to the subband based on first configuration information and the second configuration information, where the first configuration information includes a correspondence between the subband and a plurality of configurations of the first frequency domain resource unit size.

Abstract: Embodiments of systems, apparatuses, and methods for performing controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Abstract: Systems, methods, and apparatuses relating to performing fast Fourier transform (FFT) configuration and computation operations are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of processing element circuits; a first plurality of registers that represents a first two-dimensional matrix coupled to the matrix operations accelerator circuit; a second plurality of registers that represents a second two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction; and an execution circuit of the core to execute the decoded single instruction to cause the two-dimensional grid of processing element circuits to operate on a first packed data input value and a first complex twiddle factor value to produce a first result and a second result.

Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: According to an aspect of the present invention, a signal processor comprises an N-point phase FFT transformer operative to perform a FFT like transformation according to a first relation Y ? [ k ] = ? n = 0 n = N - 1 ? ? exp [ j ? ? angle ? [ x ? ( n ) ] ] * exp ? [ - j ? ? 2 ? ? ? ? kn N ] , wherein angle [x(n)] representing the phase of the signal x(n). In that, a plurality of butterfly units with each butterfly unit in the plurality of butterfly units comprises an adder, subtractor and a multiplier, wherein the adder, the subtractor and multiplier receive a phase only signals with a signal amplitude less than unity. The butterfly units are arranged in plurality of stages to perform the operation as in the first relation.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

Abstract: A method for concurrent reading of mixed radix DFT/IDFT data, a method for concurrent calculation of mixed radix DFT/IDFT method, an apparatus for concurrent reading of mixed radix DFT/IDFT data, and an apparatus for concurrent calculation of mixed radix DFT/IDFT. The method for concurrent reading includes: configuring dual circulation parameters according to the number of points corresponding to the number of series to be computed and the number of points corresponding to the number of series accomplished; then, determining the value size between the maximum number of concurrently read data and the product of the number of points corresponding to the number of series accomplished; and based on the result of determination, calculating the dual circulation parameters corresponding thereto according to the result of determination, and concurrently reading data based on the calculated dual circulation parameters.

Abstract: Systems (100) and methods (700) for customizing a cryptographic algorithm. The methods comprise: providing an electronic device with the cryptographic algorithm implementing a permutation function ƒ configured to produce a first keystream using bits input thereto, the permutation function ƒ comprising a round function ƒround consisting of a mixing layer in which input bits are combined together; and customizing the mixing layer of the permutation function ƒ while the electronic device is in the field. The mixing layer is customized by: receiving, by the electronic device, a first user-software interaction for entering a first bit string comprising a plurality of first arbitrary bits; breaking the first bit string into a plurality of equal length segments each comprising only a portion of the plurality of first bits; and translating each of the equal length segments into irreducible polynomial coefficients and/or an irreducible polynomial identifier.

Abstract: An embedded system is described. The embedded system includes a processing circuit comprising ‘Q’ processing units that can be operated in parallel. A memory is operably coupled to the processing circuit and includes at least input data. The processing circuit is configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. The processing circuit is further configured to employ a customized instruction configured to perform an FFT operation of length less than ‘Q’ using a first of the at least two smaller FFTs.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: The present disclosure provides a multi-carrier time-division multiplexing (MC-TDMA) modulation and demodulation method and system. Before multi-carrier modulation is performed on an input symbol, an interleaving allocation and an FFT may be performed, a time domain symbol may be transformed into a frequency domain symbol signal to perform a MDFT treatment. A sending end may adopt an analyzing filter bank structure, and pre-filtering and an IFFT may be performed on a signal successively. A pre-filter may be positioned between an NM point FFT and an M point IFFT, a PAPR value of the system may be reduced using the symmetry of a coefficient of a filter, and a frequency domain symbol signal may be allocated to different sub-bands for multi-carrier modulation.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: A server receives, from each of a plurality of participant devices in a communication session, a respective one of a plurality of audio streams. The server estimates an audio energy of each of the plurality of audio streams and determines whether to perform a transform on at least one of the plurality of audio streams. If so, the server performs the transform on the at least one of the plurality of audio streams and transmits the at least one of the plurality of audio streams to at least one of the plurality of participant devices.

Abstract: A special-purpose hardware accelerator may include a cache configured to store an input matrix related to performing a convolution operation and a matrix-multiplication subsystem pre-configured with matrix-transform coefficients for performing matrix-transform operations. The matrix-multiplication subsystem may perform the convolution operation by (1) reading the input matrix from the cache, (2) transforming the input matrix via matrix multiplication, (3) transforming, via matrix multiplication, a parameter matrix that includes convolution parameters for performing the convolution operation, (4) applying the transformed parameter matrix to the transformed input matrix via an element-wise multiplication operation, and then (5) performing an inverse-transformation operation on the results of the element-wise multiplication operation to create an output matrix for the convolution operation. Various other systems and methods are also disclosed.

Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

Abstract: A system for implementing a mixed radix fast fourier transformation is disclosed. The system includes a data source 202, a digit-reverse address generator 204, a data memory 206, a register array 208, a control unit 210, a butterfly extraction unit 212, a twiddle factor generator 214, and a computation unit 216. The data source 202 provides input data. The digit reverse address generator 204 processes the input data (i) to generate a digit reverse index and performs a digits reverse address calculation. The data memory 206 stores the input data. The register array 208 includes one or more registers that are configured to cache multiple data words. The control unit 210 includes of identifying butterfly operations and generate addresses for fetching/storing data. The butterfly extraction unit 212 extracts data samples. The twiddle factor generator 214 generates and outputs a twiddle factors based on the current radix and radix configuration.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A circuit for fast matrix-vector multiplication and a method for constructing that circuit are provided, comprising processing a matrix to obtain a pair matrix, which is then used to construct a circuit.

Abstract: In some examples, an apparatus includes a transmitter configured to apply input data as a frequency-domain data sequence to modulate a set of subcarriers, and separate the frequency-domain data sequence into a first subsequence of elements and a second subsequence of elements. A first conjugate symmetric subsequence that is based on inserting a zero value into the first subsequence is formed, and a second conjugate symmetric subsequence that is based on inserting a zero value into the second subsequence is formed, where the zero values are inserted at different positions in the first and second subsequences. A time-domain sequence comprising a first component that is a function of the first conjugate symmetric subsequence, and a second component that is a function of the second conjugate symmetric subsequence is generated.

Abstract: A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix computations. The configurable mixed radix engine performs the selected radix computation on data received from the memory bank through the pipeline to generate a radix result. The apparatus also includes a controller that controls how many radix computation iterations will be performed to compute an N-point DFT/IDFT based on a radix factorization.

Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.

Abstract: Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2^2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2^2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.

Abstract: A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix computations. The configurable mixed radix engine performs the selected radix computation on data received from the memory bank through the pipeline to generate a radix result. The apparatus also includes a controller that controls how many radix computation iterations will be performed to compute an N-point DFT/IDFT based on a radix factorization.

Abstract: The invention discloses a method for generating a row transposed architecture based on a two-dimensional FFT processor, comprising the following characteristic: the FFT processor includes an on-chip row transposition memory for storing an image row transposition result. When the size of the row transposition result exceeds the capacity of the on-chip memory, the first 2k data of a row of the two-dimensional array after row transformation is written into the on-chip row transposition memory, the remaining data is written into the off-chip SDRAM, and k is acquired through calculation according to the row transposition result and the capacity of the on-chip row transposition memory. The on-chip memory is divided into two memories A and B used for storing the row transposition partial result and temporarily storing data read from off-chip SDRAM.