Abstract: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

Abstract: Systems and methods are disclosed for calculating Fast Fourier Transforms (FFT) in a power and memory bandwidth efficient manner. For example, an apparatus is provided that includes a memory interface operable to read data samples stored in a memory and store a first set of the data samples in a read reorder buffer, wherein the read reorder buffer selects a first portion of the first set of the data samples in accordance with a radix-reversed order. Also included is a first core circuit that is operable to process the first portion of the first set of the data samples in response to receiving the first portion from the read reorder buffer, wherein the processing includes calculating output samples corresponding to a part of an FFT.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: In an FFT computing apparatus, a computation-unit switching detection unit detects timing at which a complex multiplication is not being carried out in said butterfly computation of FFT computation, and a complex-multiplication power-computation unit switches computation between complex multiplication and power computation, based on a detection result by said computation-unit switching detection unit. The complex-multiplication power-computation unit performs power computation at timing at which complex multiplication is not carried out in said butterfly computation of FFT computation.

Abstract: A method of operating a data-processing unit to produce a transform comprises calculating first and second output data values based at least on first and second input data values. The method comprises reading the first and second input data values from locations of a first buffer, the locations being determined by first and second read addresses based on first and second read indices. The method also comprises writing the first and second output data values to adjacent memory locations of a second buffer during a single write cycle. Furthermore, the method comprises reading third and fourth input data values from locations of the second buffer, the locations being determined by third and fourth read addresses determined by swapping at least two of the bits of the first and second read indices respectively. A data-processing unit for producing a transform, a transform-computation unit and an electronic apparatus are also described.

Abstract: A multiplexer receives a plurality of data streams transmitted in parallel on a time axis, and outputs partial data of each data stream every unit time in determined data stream order. A butterfly computation section at a first stage receives as second input data the partial data outputted from the multiplexer. A delay section corresponding to the butterfly computation section at the first stage receives in the data stream order the partial data outputted from the multiplexer, delays the partial data, and outputs the partial data as first input data for the butterfly computation section at the first stage.

Abstract: Generally, this disclosure describes a method and apparatus for reduced memory footprint fast Fourier transforms (FFTs). An apparatus may include intermediate factor circuitry configured to generate an intermediate factors vector including a number of intermediate factors in response to a request to generate an FFT of an N-point input data set, N composite, wherein N is equal to a product of a number of nonunity integer factors, the number of intermediate factors is related to the nonunity integer factors of N and the number of intermediate factors is less than N. The apparatus may include intermediate result circuitry configured to reconstruct a subset of twiddle factors based at least in part on an element by element product of a first subset of the intermediate factors vector and a complex conjugate of a second subset of the intermediate factors vector, wherein the twiddle factors are complex roots of unity.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: In a single-carrier frequency division multiple access (SC-FDMA) system that utilizes interleaved FDMA (IFDMA) or localized FDMA, multiple transmitters may transmit their pilots using time division multiplexing (TDM), code division multiplexing (CDM), interleaved frequency division multiplexing (IFDM), or localized frequency division multiplexing (LFDM). The pilots from these transmitters are then orthogonal to one another. A receiver performs the complementary demultiplexing for the pilots sent by the transmitters. The receiver may derive a channel estimate for each transmitter using an MMSE technique or a least-squares technique. The receiver may receive overlapping data transmissions sent on the same time-frequency block by the multiple transmitters and may perform receiver spatial processing with spatial filter matrices to separate these data transmissions.

Abstract: The present invention relates to a signal transmitting apparatus, a method thereof, and an inverse fast Fourier transform (IFFT) apparatus for a signal transmitting apparatus. A signal transmitting apparatus according to an embodiment of the present invention receives data, and performs inverse fast Fourier transform (IFFT) on the data on the basis of a twiddle factor for shifting output data by the size of a cyclic prefix. In addition, the signal transmitting apparatus sequentially stores data corresponding to the size of the cyclic prefix starting with initial data among the transformed data, and generates an OFDM symbol on the basis of the stored data and the transformed data. According to the embodiment of the present invention, it is possible to efficiently reduce a time delay and a memory use amount when a cyclic prefix is added at a transmitting end, without changing the size of hardware and power consumption.

Abstract: Provided two CORDIC processors, each including: two input ports representing real and imaginary input ports; and two output ports representing real and imaginary output ports; wherein real and imaginary parts of a first input signal are applied to the imaginary input ports of the first and second CORDIC processors; real and imaginary parts of a second input signal are applied to the real input ports of the first and second CORDIC processors; the first and second CORDIC processors rotate the respective input signals applied thereto by 45 degrees in the clockwise direction; respective data from the real output ports of said first and second CORDIC processors constitute real and imaginary parts of a first output signal; and respective data from the imaginary output ports of said first and second CORDIC processors constitute real part and imaginary part of a second output signal.

Abstract: Using frequency characteristics determined for individual ones of a plurality of analyzed bands of a predetermined audio frequency range with frequency resolution that becomes finer in order of lowering frequencies of the analyzed bands, a synthesized band is set for each one or for each plurality of the analyzed bands, and then a time-axial response waveform is determined for each of the synthesized bands. The response waveforms of the synthesized bands are then added together to thereby provide a response waveform for the whole of the audio frequency range.

Abstract: An algorithm system to detect a broad class of signals in Gaussian noise using higher-order statistics. The algorithm system detects a number of different signal types. The signals may be in the base-band or the pass-band, single-carrier or multi-carrier, frequency hopping or non-hopping, broad-pulse or narrow-pulse etc. In a typical setting this algorithm system provides an error rate of 3/100 at a signal to noise ratio of 0 dB. This algorithm system gives the time frequency detection ratio that may be used to determine if the detected signal falls in Class Single-Carrier of Class Multi-Carrier. Additionally this algorithm system may be used for a number of different applications such as multiple signal identification, finding the basis functions of the received signal and the like.

Abstract: Techniques for implementing mixed-radix FFT on SIMD vector processors efficiently for the latest standard in wireless communication technology by dynamically reordering stages are provided. In one aspect, a mixed-radix FFT implementation method for vector processors is provided which includes the following steps. Input data is decomposed into segments of factors based on a size of the input data, wherein the decomposing is performed in one or more stages, and wherein at each of the stages the input data is processed in blocks using one or more FFT butterfly computations for each of the blocks. The stages in which the decomposing is performed are reordered to insure complete utilization of the vector processors. The butterfly computations for one or more of the blocks are reordered to insure that the input data have memory addresses which are next to each other and contiguous.

Abstract: A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.

Abstract: Techniques for implementing mixed-radix FFT on SIMD vector processors efficiently for the latest standard in wireless communication technology by dynamically reordering stages are provided. In one aspect, a mixed-radix FFT implementation method for vector processors is provided which includes the following steps. Input data is decomposed into segments of factors based on a size of the input data, wherein the decomposing is performed in one or more stages, and wherein at each of the stages the input data is processed in blocks using one or more FFT butterfly computations for each of the blocks. The stages in which the decomposing is performed are reordered to insure complete utilization of the vector processors. The butterfly computations for one or more of the blocks are reordered to insure that the input data have memory addresses which are next to each other and contiguous.

Abstract: The disclosure provides a device with a capability of processing a Fast Fourier Transform Algorithm (FFT) radix 2 butterfly operation and an operation method thereof, the device at least includes a latch, a complex multiplier, a complex adder-subtractor, a switch and a complex conjugate Arithmetic Logical Unit (ALU). The complex operation unit of the disclosure has a simple structure. The parallel processing array composed of the complex operation unit has the capability of efficiently processing vectors and the FFT operation.

Abstract: A method for removing cyclic noise from a borehole image includes transforming the image into the frequency domain using a two-dimensional (2-D) transform (e.g., using a discrete cosine transform). The cyclic noise components (peaks) are removed from the transformed image which is then inverse transformed back into the spatial domain using an inverse 2-D transform to obtain a corrected image. An automated method enables the cyclic peaks to be identified and removed from the borehole image via downhole processing.

Abstract: The present invention generally relates to a method for computing a Fast Fourier Transform (FFT). In one embodiment, the present invention relates to an interleaved method for computing a Fast Fourier Transform (FFT).

Abstract: A method for removing cyclic noise from a borehole image includes transforming the image into the frequency domain using a two-dimensional (2-D) Fourier Transform, removing cyclic noise components from the transformed image, and inverse transforming the image back into the spatial domain using an inverse 2-D Fourier Transform. The cyclic noise component may also be isolated by subtracting the corrected image from the original image or by removing all non-cyclic noise components from the transformed image prior to inverse transforming. Removal of the cyclic noise from a borehole image tends to enable the identification of borehole features and provide for improved accuracy in formation parameter evaluation. Evaluation of the cyclic noise component may also enable the source of the noise to be identified and mitigated.

Abstract: A signal receiving apparatus includes: a processing unit configured to carry out Fourier transform on Fourier-transform data serving as a Fourier-transform object and carry out Fourier transform on inverse-Fourier-transform data serving as an inverse-Fourier-transform object; and a control unit configured to output pieces of data obtained as a result of the Fourier transform carried out on the Fourier-transform data in an order, in which the pieces of data have been obtained, in a process of outputting the pieces of data and output other pieces of data obtained as a result of the Fourier transform carried out on the inverse-Fourier transform data by rearranging the other pieces of data in a process of outputting the other pieces of data.

Abstract: The present invention is directed to sub-filtering FIR (frequency impulse response) to provide the capabilities of an ambiguity function (i.e., search for a signal in time and frequency) without extensive computations. By minimizing the resources used for the signal search (increased efficiency), the size of the implementation of the ambiguity function in hardware, and thus its power consumption, can be reduced. Additionally, by making the frequency search more efficient, larger scale frequency searches are possible.

Abstract: A minimum resource FFT design may calculate the FFT for an input data series using minimal logic resources to implement the FFT. In one implementation, the FFT design may include a butterfly component for performing one or more complex addition and multiplication operations and outputting a plurality of results; a first memory coupled to the butterfly component, the first memory including a number of memory banks equal in number to the number of the plurality of the results; a second memory coupled to the butterfly component, the second memory including a number of memory banks equal in number to a number of the plurality of the results; and a control component to control reading and writing from the first and second memories and the butterfly component using a ping-pong access technique that reads and writes intermediate values to the first and second memories to implement the FFT.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.

Abstract: An SR-2/8 FFT apparatus includes a memory, an SRFFT processor and a control unit. The control unit includes an input control block, an SRFFT control block and an output control block. The input control block loads memory banks with the input data in a first order, such that the SRFFT processor is able to retrieve data from the memory banks simultaneously in a single clock cycle. The SRFFT control block determines a decomposition structure of a 2M-point FFT and controls the SRFFT processor to repeatedly perform a butterfly computation along the decomposition structure. The order of the input data of each butterfly computation fits in with the first order. The SRFFT control block controls output results of each butterfly computation to be written back into the memory banks corresponding to the input data. The output control block controls the output results to be outputted in a second order.

Abstract: Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A data processing method is disclosed, including: twiddling input data, so as to obtain twiddled data; pre-rotating the twiddled data by using a symmetric rotate factor, where the rotate factor is a·W4L2p+1, p=0, . . . , L/2?1, and ? is a constant; performing a Fast Fourier (Fast Fourier Transform, FFT) transform of L/2 point on the pre-rotated data, where L is the length of the input data; post-rotating the data that has undergone the FFT transform by using a symmetric rotate factor, where the rotate factor is b·W4L2q+1, q=0, . . . , L/2?1, and b is a constant; and obtaining output data.

Abstract: There is provided a signal receiving apparatus including first to pth stage computers configured to apply, in a step-by-step manner, butterfly operations to 2N input values; and 2N registers configured to store values obtained by a p?1th stage computer wherein the pth stage computer includes (a) 2L butterfly operation circuits configured to transmit, from corresponding 2M output ports, values obtained by the butterfly operations based on values provided to 2M input ports and (b) 2L selecting circuits arranged corresponding to the butterfly operation circuits, each selecting circuit providing a value of a register corresponding to different one of 2L BFInOrder_i(j,t) (wherein, BFInOrder_i(j,t) denotes values obtained by converting BFOutOrder_i(j,t)=t+j*2(N?M)+i*2N?(M+L) or (2(N?(M+L))?1?t)+j*2(N?M)+i*2(N?(M+L)) expressed by base H to base 2M of (log2M 2N)?1 words, word-reversing the values converted to base 2M, and converting the word-reversed values to the base H).

Abstract: In a data processing system, a first instruction is received at an input of a processor. A specifier indicates both a first portion of a value and a second portion of the value. The first portion of the value is identified to be modified by the processor and the second portion of the value is identified to remain unchanged. The first instruction is decoded, and in response the processor modifies the first portion of the value by performing a bit-reversed increment to form a modified first portion. The modified first portion is combined with the second portion of the value which remained unchanged to form a first address. The first address is stored in first storage circuitry. A second instruction is decoded and in response the processor accesses data located at the first address which is assigned to a second storage circuit.

Abstract: Disclosed are apparatus and methods for dynamic data-based scaling of data. The disclosed methods and apparatus involve storing one or more input data samples, which are to be scaled and input to a processing function such as a Fast Fourier Transform. A scaling value operable for scaling the one or more data samples is determined based on the one or more input data samples, and then the stored data samples are scaled based on the computed scaling value when read out of storage prior to the processing function. The scaling of data based on the input data allows the data to be scaled dynamically, not statically, and ensures that the data fits within a desired bit width constraint of the processing function thereby economizing processing resources.

Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Abstract: An N-point Fast Fourier Transform (FFT) using mixed radix stages with in-place data sample storage may be performed by decomposing N into a product of R sequential mixed radix stages of radix-r(i). N data samples are partitioned into at least B memory banks, where B is equal to a largest radix of the R radix stages. Each input data sample to each radix-r(i) butterfly comes from r(i) different memory banks and the output data samples are written to the same memory locations in the r(i) memory banks. Determining from which memory bank the input data samples and output data samples of the butterflies are stored is done based on the radix size and sequential position of the radix stage. Determining the address of the input data samples and the output data samples within each memory bank is based on the radix size and sequential position of the radix stage.

Abstract: An information processing system for performing a transform of a multidimensional matrix in a distributed memory network. The method includes storing a multidimensional matrix of side N in a distributed memory network with a plurality of nodes and distributing work associated with a calculation of a transform of the matrix among N2 of the plurality of nodes. The system further includes a receiver for receiving results of the calculation of the transform of the matrix by the nodes.

Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.

Abstract: A series generator divides a data series having an autocorrelation property equally into a certain number to generate subdata series. A modulator multiplies a predetermined amplitude coefficient and a unique number by each element of the subdata series, respectively, and rearranges the subdata series and synthesizes the rearranged subdata series to generate the modulation data. An IFFT unit performs an IFFT on the modulation data. The calculator divides the calculation result equally into the certain number to generate the sub calculation results, and multiplies an equalization coefficient by each element of the sub calculation results. A synthesizer generates a baseband signal by arranging the sub calculation results, so that an arranged position corresponds to a position at the time of being divided equally, and synthesizing the arranged result. A transmitter generates the transmission signal and transmits it to another apparatus via an antenna.

Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

Abstract: An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals.

Abstract: The present invention relates to an apparatus and method for variable fast Fourier transform. According to an embodiment of the present invention, two n-point fast Fourier transform (FFT) processors are used to generate two n-point FFT output data or one 2n-point FFT output data. The one 2n-point input data is alternately input to the two n-point FFT processors. Each of the two n-point FFT processors selects a twiddle factor for the n-point input data or the 2n-point input data and performs fast Fourier transform. A butterfly operation is performed on signals obtained by performing fast Fourier transform on the 2n-point input data signal, and the processed signals are aligned in an output order. According to this structure, it is possible to realize a fast Fourier transform hardware engine that selectively performs multi-frequency allocation in a base station system that supports the multi-frequency allocation.

Abstract: There is provided a method for generating a table for reordering the output of a Fourier transform, the Fourier transform being performed on a predefined number of input samples, the method comprising performing one or more decomposition stages on a sequence corresponding in number to the predefined number of input samples to form a representation of the output of the Fourier transform; wherein at least one of the decomposition stages comprises a composite operation that is equivalent to two or more operations; and rearranging the representation of the output of the Fourier transform to generate a reordering table.

Abstract: A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [AN(?), BN(?)] of an Lp-norm harmonic regression of the signal with 0<p?? and p?2, squaring the coefficients, summing the squared coefficients, and scaling the summed, squared coefficients with a constant c to realize a periodogram of X(t) as LN(?)=c{[AN(?)]2+[BN(?)]2}. The method may include receiving the signal X(t), storing the received signal X(t), and outputting the periodogram LN(?). The method may still further include scanning to maximize the periodogram LN(?) by identifying its largest peak(s) and comparing the amplitude of the identified largest peak(s) with a threshold to determine if the largest peak(s) is(are) attributable to a presence of a periodic signal.

Abstract: The present invention relates to a memory address generating method and a twiddle factor generator using the memory address generating method in a fast Fourier transform (FFT) system. In the memory address generating method for generating a memory address of a twiddle factor in a fast Fourier transform (FFT) system according to an embodiment of the present invention: a) a temporary address value of a second twiddle factor is induced and generated based on a first twiddle factor; b) a control signal for controlling the system is generated based on the generated temporary address value; and c) a memory address value of the second twiddle factor is generated from the temporary address value.

Abstract: The ability to examine the frequency content of a signal is critical in a variety of fields, and many techniques have been proposed to fill this need, including the Fourier and wavelet family of transforms. One of these, the S-transform, is a Fourier based transform that provides simultaneous time and frequency information similar to the wavelet transform but uses sinusoidal basis functions to produce true frequency and globally referenced phase measurements. It has been shown to be useful in several medical imaging applications but its use is limited due to high computational requirements of the original, continuous form. The described embodiments include a general framework for describing linear time-frequency transforms, using the Fourier, wavelet and S-transforms as examples. As an illustration of the utility of this formalism, a fast discrete S-transform algorithm is developed that has the same computational complexity as the fast Fourier transform.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A pipelined FFT circuit used for processing a sequential input data with a set of N samples comprises a data division unit, a data-preprocessing unit and M sets of data computation unit. The data division unit is used for dividing the sequential input data into a first input data stream and a second input data stream. The data-preprocessing unit receives the first and second input data streams and orders the first input data stream to an odd number-index data stream, the second input data stream to an even number-index data stream respectively. Each of the data computation units has a data switch and a butterfly computator connected with the data switch, where M=log2N, the data switch of the first data computation unit is connected with the data-preprocessing unit.

Abstract: A processor for processing digital data includes at least one butterfly operator for execution of a fast Fourier transform computation, the butterfly operator having a pipeline architecture for synchronized receiving and processing of input data according to a clock signal. This pipeline architecture includes a plurality of elements including addition, subtraction, and multiplication hardware modules and links for synchronized transmission of data between the modules. At least one element of this pipeline architecture is configurable by at least one programmable parameter, between a first configuration wherein the butterfly operator performs the fast Fourier transform computation and a second configuration wherein the butterfly operator performs a metric computation of an implementation of a channel decoding algorithm.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.

Abstract: In a data processing system, having a twiddle factor unit, a method for performing a mixed-radix discrete Fourier transform (DFT) having a block size, N, and a maximum block size, Nmax, wherein the maximum block size includes a radix that is not a power of 2 is provided. The method includes receiving a delta value at an input of the twiddle factor unit, the delta value representing a ratio of a modified maximum bock size to the block size, wherein the modified maximum block size is a power of 2. The method further includes using the delta value to obtain a step size for generating indices of a look-up table stored within the twiddle factor unit, wherein the look-up table stores real and imaginary components of twiddle factors corresponding to a set of block sizes of the DFT.