Abstract: Systems, methods and devices for reducing noise in health monitoring including monitoring systems, methods and/or devices receiving a health signal and/or having at least one electrode or sensor for health monitoring.

Abstract: A FFT/IFFT method, comprises converting a set of reversal-order or a set of natural-order addresses of FFT/IFFT data to a set of addresses in a radix-based numeral representation; calculating sequence numbers of a plurality of memory locations for buffering a set of data for a parallel calculation, by accumulating or subtracting all digits of the set of addresses in the radix-based numeral representation and then performing a modulo operation on the accumulation or subtraction results, wherein the radix represents a length of short DFT sequence for the parallel calculation in a FFT/IFFT calculation; storing the FFT/IFFT data simultaneously and respectively into corresponding memory locations indicated by the calculated sequence numbers; and performing FFT/IFFT calculation, comprising: performing short DFT sequence calculation; repeating the short DFT sequence calculation, until the whole FFT/IFFT calculation completes.

Abstract: A telecommunication receiver is arranged for receiving related data originating from multiple antennas, which data have different times of arrival due to, for example, different delays. The receiver comprises an input buffer for buffering data, a transform unit for Fourier transforming the data received from the input buffer into transformed data, and an output buffer for buffering the transformed data received from the transform unit. The input buffer is arranged for passing each set of data items to the transform unit when the relevant data item has been received in the input buffer, while the transform unit is arranged for removing redundant parts of the data. In addition, the output buffer is arranged for synchronizing the transformed data. Thus the buffering for delay compensation is carried out in the output buffer.

Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.

Abstract: Provided is a fully parallel fast Fourier transformer of N-point, where N is a natural number, including a bit-reversal arranging block configured to rearrange an order of N input complex number samples, a plurality of first processors configured to perform, in a plurality of group units, a 16-point FFT on the rearranged complex number samples, a twiddle factor multiplier configured to multiply outputs of the plurality of first processors by twiddle factors, a first group rearranging block configured to rearrange outputs of the twiddle factor multiplier in the plurality of group units, a plurality of second processors configured to perform, in the plurality of group units, 16-point FFT on the complex number samples grouped by the first group rearranging block, and a second group rearranging block configured to rearrange outputs of the plurality of second processors to output under a same arrangement criterion as the first group rearranging block.

Abstract: A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a plurality of vector register files and a scratch state memory provide input data to at the at least one set of add operations.

Abstract: A method, apparatus, and computer program product for performing an FFT computation. The method includes: providing first and second input data elements in multiple memory areas of a memory unit; in each of a number of consecutive computation stages, performing multiple butterfly operations based on a first and second input data element to obtain two output data elements, wherein first and second input data elements for a plurality of multiple butterfly operations are simultaneously retrieved from predetermined memory locations of a first and second of memory areas; for each stage, storing two output data elements in the memory unit as input data elements for a next stage according to a mapping scheme configured to store output data elements at memory locations in first and second memory areas so that they are simultaneously retrievable as input data elements for a plurality of butterfly operations of subsequent computation stage.

Abstract: An audio coding device includes a memory; and a processor configured to execute a plurality of instructions stored in the memory, the instructions comprising: selecting a main lobe among a plurality of lobes detected from a frequency signal configuring an audio signal on a basis of bandwidth and power of the lobes; and coding the audio signal in such a manner that a first amount of bits per a unit frequency domain allocated to coding of the frequency signal of the main lobe is larger than a second amount of bits per the unit frequency domain allocated to the coding of the frequency signal of a side lobe as a lobe other than the main lobe.

Abstract: Methods, devices and systems for determining whether an object is detected by a scanner are disclosed. Fast-Fourier-Transforms (“FFT”) are determined, modified and evaluated. Each FFT may be determined with regard to a subset of gain-compensated pixel-values corresponding to pixel-values of an acquired image.

Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract: In one embodiment, an FFT circuit (1) includes a pipeline in which L number of butterfly operational elements each having Single-path Delay Feedback, SDF, architecture are connected with each other. Each of LHF number of butterfly PEs (10), corresponding to a first stage to an LHFth stage, is configured to rearrange output data order such that, in units of N/(2S?1) pieces of output data starting from head output data whose Data Flow Graph, DFG, index i is “0”, intermediate result data GS(i) whose bS(i) is 1 is output after intermediate result data GS(i) whose bS(i) is 0 in the N/(2S?1) pieces of the output data, where N represents the number of FFT points, S represents an integer indicating a stage number, and bS(i) represents the Sth bit from the least significant bit in binary representation of the DFG index i.

Abstract: Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed.

Abstract: The present invention, herein is a method and apparatus that significantly limits the effect of high frequency (“HF”) interferences on acquired electro-physiological signals, such as the EEG and EMG. Preferably, this method comprises of two separate electronic circuitries and steps or electronics for processing the signals. One circuit is used to block the transmission of HF interferences to the instrumentation amplifiers. It is comprised of a front-end active filter, a low frequency electromagnetic interference (“EMI”) shield, and an isolation barrier interface which isolates the patient from earth ground. The second circuit is used to measure the difference in potential between the two isolated sides of the isolation barrier. This so-called “cross-barrier” voltage is directly representative of the interference level that the instrumentation amplifier is subjected to. This circuit is used to confirm that the acquired signals are not corrupted by the interference.

Abstract: A method for convolving an input signal with an impulse response function, the impulse response function being partitioned into a plurality of time segments of equal size, the method including transforming a segment of an input signal into the frequency domain to generate a frequency spectrum of the segment of the input signal; multiplying the frequency spectrum of the segment of the input signal with a frequency spectrum of each of the segments of the impulse response function; scaling the results from the multiplication of frequency spectra; accumulating the scaled results; and performing an inverse transform on the accumulated signals to generate a desired convolved signal in the time domain. The scaling includes performing a bitwise shift operation on the multiplication results, and performing the bitwise shift operation includes adding a bit to the multiplication results before the bitwise shift operation.

Abstract: An anomalous effect detector responsive to an influence of mind comprises a source of non-deterministic random numbers, SNDRN, a phase-sensitive filter and a results interface. In some embodiments, the phase-sensitive filter comprises a complex filter. An artificial sensory neuron comprises a SNDRN. Preferably, several artificial sensory neurons are grouped in a small volume. An analog artificial sensory detector comprises a plurality of analog artificial sensory neurons, an abstracting processor and a control or feedback unit. Some embodiments include an artificial neural network. An artificial consciousness network contains a plurality of artificial neural networks. One of the artificial neural networks comprises an activation pattern meta-analyzer. An artificial consciousness device comprises a cluster of artificial consciousness networks, a sensory input device to provide sensory input signals to the input of one or more ANNs in ACD, and an output device.

Abstract: The present disclosure relates to a turbo decoder and decoding method thereof. The turbo decoder has a plurality of decoder cores. The decoding method includes: computing remaining decoding times for the multiple decoder cores; selecting a decoder core with the shortest remaining decoding time among the multiple decoder cores; and allocating a packet to the selected decoder core. The decoder cores of the turbo decoder are monitored in real time and resources are distributed through efficient decoder core selection enhancing decoding throughput.

Abstract: Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the shared register file is adapted to serve as a shared resource among the selected processor cores.

Abstract: Described is a technology for use with general discrete Fourier transforms (DFTs) performed on a graphics processing unit (GPU). The technology is implemented in a general library accessed through GPU-independent APIs. The library handles complex and real data of any size, including for non-power-of-two data sizes. In one implementation, the radix-2 Stockham formulation of the fast Fourier transform (FFT) is used to avoid computationally expensive bit reversals. For non-power of two data sizes, a Bluestein z-chirp algorithm may be used.

Abstract: A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data. Further, the method and device can flexibly define the parallel granularity according to particular applications.

Abstract: The present invention generally relates to a method for computing a Fast Fourier Transform (FFT). In one embodiment, the present invention relates to an interleaved method for computing a Fast Fourier Transform (FFT).

Abstract: A method and device for multi-granularity parallel FFT butterfly computation. The method and device read data and twiddle factors for computation in one butterfly group from the input buffers and the twiddle factor buffer at a time, perform multi-stage butterfly computation in parallel using uniform butterfly representations, and write the results back to the input buffers. The method and device greatly reduce the frequency for accessing the memory, improve speed for butterfly computation, and reduce power consumption. The method and device achieve multi-granularity butterfly computation of various data formats in a parallel and efficient manner. The method and device can specify the parallel granularity and data format for butterfly computation according to particular applications, and are applicable to FFT butterfly computation of balanced and unbalanced groups.

Abstract: A minimum resource FFT design may calculate the FFT for an input data series using minimal logic resources to implement the FFT. In one implementation, the FFT design may include a butterfly component for performing one or more complex addition and multiplication operations and outputting a plurality of results; a first memory coupled to the butterfly component, the first memory including a number of memory banks equal in number to the number of the plurality of the results; a second memory coupled to the butterfly component, the second memory including a number of memory banks equal in number to a number of the plurality of the results; and a control component to control reading and writing from the first and second memories and the butterfly component using a ping-pong access technique that reads and writes intermediate values to the first and second memories to implement the FFT.

Abstract: A signal-analysis portion executes a signal-analysis process to signal data that corresponds to an ultrasonic echo received from a subject. A determining portion determines whether image data regarding the subject, which is created based on the signal data upon which said signal-analysis process has been executed, includes a diagnostic target. A parameter-setting portion, based on the determination result, changes to a different value the value of a specific parameter that has an effect on the resolution of the signal-analysis process, among processing parameters to be employed in the signal-analysis process. A display portion displays image data regarding the subject based on the signal data that has been signal-analysis processed according to the specific parameter.

Abstract: A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.

Abstract: Methods and systems for performing Fast Fourier Transform (FFT) operations are disclosed. A plurality of cascaded stages compute a selectable one of a forward decimation-in-frequency (DFT) FFT operation in a forward direction from an ith stage to a jth stage, and a reverse DFT FFT operation in a reverse direction from the jth stage to the ith stage. The reduction in time and resource usage from employing the disclosed bidirectional DIF FFT architectures may significantly increase performance of DIF applications, for example, ones that involve streaming FFTs.

Abstract: A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.

Abstract: A modulator and modulation method are provided, which output an OQAM multi-carrier signal. The method implements a step of transforming, from the frequency domain to the time domain, a set of M symbols of real data so as to output M transformed symbols. The complete transformation includes the following sub-steps: applying a partial Fourier transform to the set of M symbols of real data, outputting a first subset of C transformed symbols, where C is strictly less than M; and obtaining, from the first subset, a second subset of (M-C) transformed symbols that is complementary to the first subset.

Abstract: A processor for processing digital data includes at least one butterfly operator for execution of a fast Fourier transform computation, the butterfly operator having a pipeline architecture for synchronized receiving and processing of input data according to a clock signal. This pipeline architecture includes a plurality of elements including addition, subtraction, and multiplication hardware modules and links for synchronized transmission of data between the modules. At least one element of this pipeline architecture is configurable by at least one programmable parameter, between a first configuration wherein the butterfly operator performs the fast Fourier transform computation and a second configuration wherein the butterfly operator performs a metric computation of an implementation of a channel decoding algorithm.

Abstract: Techniques for implementing mixed-radix FFT on SIMD vector processors efficiently for the latest standard in wireless communication technology by dynamically reordering stages are provided. In one aspect, a mixed-radix FFT implementation method for vector processors is provided which includes the following steps. Input data is decomposed into segments of factors based on a size of the input data, wherein the decomposing is performed in one or more stages, and wherein at each of the stages the input data is processed in blocks using one or more FFT butterfly computations for each of the blocks. The stages in which the decomposing is performed are reordered to insure complete utilization of the vector processors. The butterfly computations for one or more of the blocks are reordered to insure that the input data have memory addresses which are next to each other and contiguous.

Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2 N)×(10×log2 N) times.

Abstract: A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

Abstract: Techniques for implementing mixed-radix FFT on SIMD vector processors efficiently for the latest standard in wireless communication technology by dynamically reordering stages are provided. In one aspect, a mixed-radix FFT implementation method for vector processors is provided which includes the following steps. Input data is decomposed into segments of factors based on a size of the input data, wherein the decomposing is performed in one or more stages, and wherein at each of the stages the input data is processed in blocks using one or more FFT butterfly computations for each of the blocks. The stages in which the decomposing is performed are reordered to insure complete utilization of the vector processors. The butterfly computations for one or more of the blocks are reordered to insure that the input data have memory addresses which are next to each other and contiguous.

Abstract: Methods and systems for amplitude modulation in a parametric speaker system are provided that perform truncated double sideband (TDSB) frequency modulation of audio signal in which most of the processing is performed in the frequency domain, thus permitting use of fast processing techniques for amplitude modulation (AM) and filtering and reducing computation cost over time domain processing. A maximum envelope value of the time domain audio signal may be to the carrier signal in the frequency domain that avoids emitting the carrier signal when the input signal level is low or mute. The application of the envelope value may be smoothed to reduce discontinuity at input block boundaries.

Abstract: A series generator divides a data series having an autocorrelation property equally into a certain number to generate subdata series. A modulator multiplies a predetermined amplitude coefficient and a unique number by each element of the subdata series, respectively, and rearranges the subdata series and synthesizes the rearranged subdata series to generate the modulation data. An IFFT unit performs an IFFT on the modulation data. The calculator divides the calculation result equally into the certain number to generate the sub calculation results, and multiplies an equalization coefficient by each element of the sub calculation results. A synthesizer generates a baseband signal by arranging the sub calculation results, so that an arranged position corresponds to a position at the time of being divided equally, and synthesizing the arranged result. A transmitter generates the transmission signal and transmits it to another apparatus via an antenna.

Abstract: Generation of standardized noise signals that provide mathematically correct noise with no errors and no loss of data, and can generate the noise of specific environments based on the transfer function of that environment are discussed. Various embodiments can generate synthetic data sets based on natural data sets that have similar scaling behavior. Fractional scaling digital filters, containing the fractional scaling characteristics of one or more of the eleven fundamental forms of basic building block transfer functions which incorporate the scaling exponent, can be encoded on FPGA devices or DSP chips for use in digital signal processing. Fractional Scaling Digital Filters allow fractional calculus, and thus fractional filtering (e.g.

Abstract: A method, apparatus, and computer program product for performing an FFT computation. The method includes: providing first and second input data elements in multiple memory areas of a memory unit; in each of a number of consecutive computation stages, performing multiple butterfly operations based on a first and second input data element to obtain two output data elements, wherein first and second input data elements for a plurality of multiple butterfly operations are simultaneously retrieved from predetermined memory locations of a first and second of memory areas; for each stage, storing two output data elements in the memory unit as input data elements for a next stage according to a mapping scheme configured to store output data elements at memory locations in first and second memory areas so that they are simultaneously retrievable as input data elements for a plurality of butterfly operations of subsequent computation stage.

Abstract: An FFT/IFFT operating core capable of minimizing a required memory depth during operation is disclosed. The FFT/IFFT operating core includes an inputting buffer, a first multiplexer, an operating module, and a controlling module. The inputting buffer stores and outputs a first FFT input sequence. The first multiplexer is utilized to multiplex the first FFT input sequence and a third input sequence. The controlling module generates a process indicating signal and a bypass indicating signal. The operating module has a plurality of operating stages in series. The operating module transforms the first and third FFT input sequences into a first and third FFT output sequences, respectively, and it transforms a second IFFT input sequence into a second IFFT output sequence.

Abstract: Disclosed herein are a mixed-radix pipelined Fast Fourier Transform (FFT) processor and an FFT processing method using the same. The mixed-radix pipelined Fast Fourier Transform (FFT) processor includes a first radix chain, a second radix chain, an input buffer, and an output buffer. The first radix chain includes first radix processors that are connected in series to each other. The second radix chain includes second radix processors that are connected in series to each other, and is connected in series to the first radix chain. The input buffer performs index mapping on a sequence input to the first radix chain. The output buffer generates a final FFT output by performing index mapping on a sequence generated using outputs of one or more of the first and second radix chains.

Abstract: A data reordering system for determining addresses associated with a vector of transformed data and corresponding method of reordering transformed data, where the data reordering system includes: a first transform function coupled to a data vector and operable to provide the vector of transformed data; a reordering function, including a plurality of counters, that is operable to determine a plurality of offset addresses, with a, respective, offset address for each element in the vector of transformed data; and an adder operable to add a base address that corresponds to the first address to the each, respective, offset address to provide a sequence of addresses suitable for accessing the vector of transformed data to provide a re-sequenced vector of transformed data.

Abstract: The present disclosure provides A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data.

Abstract: A method and device for multi-granularity parallel FFT butterfly computation. The method and device read data and twiddle factors for computation in one butterfly group from the input buffers and the twiddle factor buffer at a time, perform multi-stage butterfly computation in parallel using uniform butterfly representations, and write the results back to the input buffers. The method and device greatly reduce the frequency for accessing the memory, improve speed for butterfly computation, and reduce power consumption. The method and device achieve multi-granularity butterfly computation of various data formats in a parallel and efficient manner. The method and device can specify the parallel granularity and data format for butterfly computation according to particular applications, and are applicable to FFT butterfly computation of balanced and unbalanced groups.

Abstract: An approach is provided for correlation of a signal over time and frequency. The signal is correlated with a bit sequence over time instances and certain frequency offsets, wherein sub-segments of the signal are correlated with sub-segments of the bit sequence to generate a correlation factor associated with each signal sub-segment. The correlation factors are coherently combined to generate a final correlation factor, wherein a respective phase shift (for each frequency offset) is applied to each correlation factor to generate a set of frequency adjusted correlation factors, and the frequency adjusted correlation factors of a respective set are combined to generate the final correlation factor over the signal sub-segments, resulting in the matrix of final correlation factors over time and frequency. A signal parameter estimation is performed, based on the matrix of final correlation factors, to determine a highest correlation value for the signal over the frequency offsets.

Abstract: The present invention provides technologies for implementing a high-speed Fast Fourier Transform (FFT) algorithm with a small memory. An information processing apparatus for performing a radix-2 FFT on a data sequence comprises storage means, reading means, a plurality of butterfly operation means, writing means, and control means, wherein each stage of the FFT operation includes a plurality of operation steps, and at every operation step the control means controls each of the means so that: the reading means reads from the storage means sets of data elements referred by storage addresses A, A+1, A+2m, and A+2m+1, the plurality of butterfly operation means perform radix-2 butterfly operation on the data elements in the sets, and the writing means writes the sets of the result data into the storage area referred by the storage addresses A, A+1, A+2m, and A+2m+1.

Abstract: Processors and methods for solving mathematical equations are disclosed herein. An embodiment of the processor includes a hardware device that calculates coefficients based on a mathematical operation that is to be performed. An indexing device transmits the coefficients to and from a look up table. A hardware multiplier multiplies certain coefficients by the derivative of a function related to the mathematical operation. A hardware adder adds a first coefficient to the product of a second coefficient and the first order derivative of the function.

Abstract: The invention relates to a method for processing a signal, in particular a digital audio signal, suitable for being implemented by a digital signal processor (DSP) having libraries for calculating Fourier transforms from the complex number space to the complex number space, for digitally processing P input signals, P being an integer at least equal to 2, more particularly for filtering said P input signals by the convolution of sampled fast Fourier transforms (FFT), thus obtaining Q output signals, Q being an integer at least equal to 2.

Abstract: Implementations related to power reduction in physical layer wireless communications are disclosed.

Abstract: A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided.

Abstract: An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

Abstract: Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2X butterfly vector operations as well as other arithmetic logic vector operations.

Abstract: A method, apparatus, and computer program product for calculating a sampled signal are disclosed. A method in accordance with the disclosure may include determining discrete samples of a continuous signal having a finite spectrum and using a function series expansion to calculate at least a portion of the continuous signal over the discrete samples. In accordance with some embodiments, an original signal may be calculated over discrete samples with arbitrary accuracy. Polyphase filtering is not used in some embodiments. Some embodiments can be used for arbitrary, including irrational, variation of the sampling rate of the signal with a bounded spectrum. Some embodiments provide for much faster calculation than direct application of the Kotelnikov (Nyquist-Shannon) theorem. In some embodiments, the calculation may be performed according to the disclosed theorem but, instead of discrete signal convolutions with kernels having different phases, a function series expansion may be used.