Abstract: Provided is a method for digital image representation based upon Discrete Projective Fourier Transform (DPFT) constructed in the noncompact (DNPFT) and compact (DCPFT) realizations of geometric Fourier analysis on SL(2,C) groups. Novel characteristics are that the model is well adapted to perspective image transformations and well adapted to the retinotopic (conformal) mapping of the biological visual system. To compute the DPFT of a digital image by Fast Fourier transform (FFT), an image is re-sampled with a non-uniform log-polar sampling geometry. A “deconformalization” procedure corrects the “conformal lens optics” of the conformal camera to render image perspective transformations.

Abstract: Provided are methods of using electromagnetic waves for detecting metal and/or dielectric objects. Methods include directing microwave and/or mm wave radiation in a predetermined direction using a transmission apparatus, including a transmission element; receiving radiation from an entity resulting from the transmitted radiation using a detection apparatus; and generating one or more detection signals in the frequency domain using the detection apparatus. Methods may include operating a controller, wherein operating the controller includes causing the transmitted radiation to be swept over a predetermined range of frequencies, performing a transform operation on the detection signal(s) to generate one or more transformed signals in the time domain, and determining, from one or more features of the transformed signal, one or more dimensions of a metallic or dielectric object upon which the transmitted radiation is incident.

Abstract: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.

Abstract: Method and apparatus for a complimentary discrete Fourier transform processor. An input signal is sampled, samples then being sequentially delayed, channelized, and processed. Synthesized outputs are provided in complimentary form. Channels are independent so as to allow for the application of gain, equalization and interference cancellation on a channel-by-channel basis. Both real and complex valued input signals may be processed. The invention optimizes computational efficiency.

Abstract: A method and apparatus is disclosed for performing blind source separation using convolutive signal decorrelation. For a first embodiment, the method accumulates a length of input signal (mixed signal) that comprises a plurality of independent signals from independent signal sources. The invention then divides the length of input signal into a plurality of T-length periods (windows) and performs a discrete Fourier transform (DFT) on the signal within each T-length period. Thereafter, estimated cross-correlation values are computed using a plurality of the averaged DFT values. A total number of K cross-correlation values are computed, where each of the K values is averaged over N of the T-length periods. Using the cross-correlation values, a gradient descent process computes the coefficients of a FIR filter that will effectively separate the source signals within the input signal. A second embodiment of the invention is directed to on-line processing of the input signal—i.e.

Abstract: A method of processing a set of input data values comprises the steps of providing said input data values serially to circuitry comprising a number of memory elements; and performing in said circuitry a transform function to obtain a set of transformed data values. The method further comprises the steps of delaying a subset of said set of input data values under use of said memory elements; providing a modified set of data values by adding individual delayed data values to individual non-delayed data values from said set of input data values; and performing said transform function on said modified set of data values. In this way a transform function can be evaluated at fewer output data values than available input data values without increasing the memory requirements considerably.

Abstract: Processing of information signals separated according to modulation and carrier components in a more controlled way is made possible by a device for processing an information signal including a unit for converting the information signal to a time/spectral representation by block-wise transforming of the information signal and a unit for converting the information signal from the time/spectral representation to a spectral/modulation spectral representation, wherein the unit for converting is designed such that the spectral/modulation spectral representation depends on both a magnitude component and a phase component of the time/spectral representation of the information signal. A unit then performs a manipulation and/or modification of the information signal in the spectral/modulation spectral representation to obtain a modified spectral/modulation spectral representation.

Abstract: The coupling circuit described herein comprises passive analog components for coupling a transceiver to an antenna, such as an antenna array. The coupling circuit transforms an input signal into an appropriate format for each element of the antenna array. The coupling circuit comprises a coupling network having a plurality of inputs and a plurality of outputs. The inputs provide quadriphase versions of at least one input signal. In one embodiment, the coupling circuit performs a Discrete Fourier Transform (DFT) on the input signal. In another embodiment, the coupling circuit performs a Fast Fourier Transform (FFT) on the input signal. In still another embodiment, the FFT performed by the coupling circuit implements a Butler matrix.

Abstract: A data encryption method using discrete fractional Hadamard transformation includes the steps of: providing a set of data; processing the data with discrete fractional Hadamard transformation to generate at least one Hadamard matrix, the Hadamard matrix having eigen vectors corresponding to eigen values; selecting order parameters from order vectors of the Hadamard matrix; designating the order parameters as a private key in data encryption. In an embodiment, a set of integers is designated to define numerators and denominators of fractions which represent the eigen values of the Hadamard matrix.

Abstract: Methods and apparatus arc provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a discrete Fourier Transform (DFT), such as a power-of-two DFT, on the extended input sequence to obtain an interpolated sequence; and applying a conversion matrix to the interpolated sequence to obtain a DFT output for the input sequence of length N. The input sequence of length N can be extended to an extended input sequence of length M, for example, by employing a zero padding technique, a cyclic extension technique, a windowing of a cyclic extended sequence technique or a resampling-based interpolation technique to extend the input sequence The conversion matrix is substantially a spar se matrix.

Abstract: First and second coefficients are fed into a Fast Fourier Transform unit through real number input and imaginary number input portions thereof, respectively, to perform the Fast Fourier Transform of the entered first and second coefficients, thereby producing a frequency-domain coefficient vector. The Fast Fourier Transform of an input signal is performed to transform the input signal into a frequency-domain signal vector. Thereafter, the transformed signal vector is multiplied by the coefficient vector for each element, thereby providing a multiplication result. The Inverse Fast Fourier Transform of the multiplication result renders real number output and imaginary number output portions of the inverse transformation result as first and second series of output signals, respectively.

Abstract: Time delay and frequency offset calculation systems and related methods. System implementations include modules coupled together configured to calculate a time delay and a corresponding frequency offset of a second signal delayed in time relative to a first signal with the maximum value of a magnitude of a delay optimization function. Implementations of a method for calculating a time delay and frequency offset calculate the maximum value of the delay optimization function by generating the cross-correlation of one or more adjacent discrete Fourier transformed blocks corresponding to the first signal and second signal, respectively, of two or more discrete Fourier transformed blocks. The maximum value of the delay optimization function is then identified. Implementations of the method may compare the identified maximum value of the magnitude of the delay optimization function with a threshold to determine whether to continue processing for additional adjacent discrete Fourier transformed blocks.

Abstract: Disclosed is a European digital audio broadcast receiver having a simply implementable fast Fourier transform processor and an operation method therefor. A digital audio broadcast receiver having diverse fast Fourier transform (FFT) modes based on sizes of transmitted data has an address generator for generating a predetermined number of write addresses and read addresses, a fast Fourier transform (FFT) processor for repeating data of FFT modes to generate a predetermined number of data and implementing a fast Fourier transform (FFT) by using the predetermined number of data, and a controller for controlling the address generator to the write addresses and the read addresses according to operations of the FFT processor.

Abstract: A Fourier transform apparatus whose pipeline width is independent of transform point number of individual pipeline FFT circuits in each stage and composed of a preceding stage and a succeeding stage. Each of the stages includes M(power of 2)-point radix 2 pipeline FFT circuits each having two-parallel inputs/outputs in a number of a (divisor of M) which are equal in respect to the transform point number and data permutating means for data supply to the transform means of each stage so that the pipeline width of the Fourier transform apparatus is made independent of the transform point numbers of the individual pipeline FFT circuits in each stage.

Abstract: In one embodiment, the present invention includes a method for receiving vertex data corresponding to a surface of an image, performing a discrete Fourier transform (DFT) on the vertex data to obtain a frequency response, zero padding the frequency response to obtain zero padded frequency response data, and performing an inverse DFT (IDFT) on the zero padded frequency response data to obtain modified vertex data including the vertex data and additional vertex data corresponding to the surface. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.

Abstract: An apparatus for reducing a digital filter delay includes means for determining the magnitude response of a desired filter. Means form the real cepstrum of this magnitude response. Means transform the real cepstrum into a complex cepstrum of a corresponding minimum-phase filter having the same magnitude response as the desired filter. A filter applies a smoothly decaying shaping window to the complex cepstrum. Means transform the shaped complex cepstrum into an estimated minimum-phase filter.

Abstract: A technique for interpolating a series of samples includes constructing a mathematical model of the series that describes its large signal behavior. The model is subtracted from the original series to yield a residue. A discrete Fourier transform (DFT) is taken of the residue, and the DFT is zero-padded. An inverse DFT of the padded result yields an interpolated residue, which is then added back to the mathematical model to construct an interpolated version of the series of samples. Using this technique, accurate interpolation can generally be attained even when the series of samples is not coherently sampled.

Abstract: An apparatus for calculating an N-point Discrete Fourier Transforms (DFTs) and/or Inverse DFTs (IDFTs) using the Cooley-Tukey algorithm is provided. The N-point DFT/IDFT is achieved by calculating a plurality of N1-point and N2-point DFTs. The apparatus comprises a storing unit, a calculating unit, and a controlling unit. The storing unit comprises a first memory for storing a plurality of first data and a second memory for storing a plurality of second data. The calculating unit comprises a one-dimensional systolic array for calculating the N1-point and N2-point DFT.

Abstract: Disclosed is a method and an apparatus for efficient ACKnowledgment/NonACKnowledgement (ACK/NACK) transmission in order to transmit forward data for multiple layers and support Hybrid Automatic Retransmission reQuest (HARQ) for each layer in a mobile communication system. The method includes determining whether transmission of the ACK/NACK is for a first layer or for layers higher than the first layer; and when the transmission of the ACK/NACK is for layers higher than the first layer, transmitting the reverse ACK/NACK by allocating resources to the higher layers with a quantity different from that of the first layer.

Abstract: The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one enhanced DFT module is provided by using at least one type of DFT module including multiplication by first and second types of twiddle factors in respective different multiplication stages separated by an intermediate integration stage, and generating the enhanced DFT module by combining the at least one type of DFT module with a recursive stage configured to multiply by a third type of twiddle factor and to selectively switch between a bypass function and a butterfly function in said recursive stage. Thereby, an implementation of non 2x-radix Fourier transformation can be achieved with moderate hardware complexity.

Abstract: A method encodes a sequence of blocks of input bits to be transmitted over a wireless channel. Each block of input bits is converted to a codeword, and each codeword is mapped to multiple sub-blocks of complex numbers. Each sub-block is multiplied by a disambiguating spreading transform to obtain a sub-block of transformed symbols, which can be modulated and transmitted to a receiver, where each received block is demodulated to a block of complex numbers, which are partitioned into sub-blocks. The sub-block of complex numbers are converted to a set of likelihood ratios that correspond to decoded codewords. The input bits can be decoded unambiguously even if only one of the blocks of symbols corresponding to the block of input bits is received correctly.

Abstract: Herein described is at least a method for implementing an adaptive digital filter of reduced implementation complexity. The method comprises computing at least one complex discrete Fourier transform of a complex data sequence using approximately one-half the number of points used in computing said discrete Fourier transform of a real valued sequence. Further, herein described is an adaptive digital filter of reduced implementation complexity. The adaptive digital filter comprises at least one circuitry for computing a complex discrete Fourier transform of a complex data sequence using approximately one-half the number of points used in computing the discrete Fourier transform of a real valued sequence. The adaptive digital filter may be employed in a 10 Gbit/sec Ethernet transceiver.

Abstract: A modulated laser light detector that converts laser light energy into electrical signals which exhibit a frequency that is substantially the same as the laser light modulation frequency, in which these signals allow the detector unit to determine a position where the laser light is impacting upon a photodiode array. A superheterodyne receiver circuit is used to provide high gain at an improved signal-to-noise ratio to improve the range at which the modulated laser light signal can be reliably detected. Various types of signal detection circuits are available. Various processing algorithms are disclosed, including a Discrete Fourier Transform with a simplified computational algorithm for use with a low-power processor device.

Abstract: The present invention relates generally to the problem of filtering, decimation or interpolation and frequency conversion in the digital domain, and more particularly to its use in wideband multichannel receiver, channelization, and transmitter, de-channelization, structures. The invention combines a stand-alone fast convolution algorithm which is further modified and then combined with additional signal processing. By intelligently splitting the filtering effort between the modified fast convolution algorithm block and an additional signal processing block a synergy is created between the two blocks which provides for decreased costs, reduced delay and a reduction in the size of the Fast Fourier Transforms (FFTs). The resulting advantages are especially useful in any system handling multiple channels simultaneously, but especially where there exist strict requirements on both delay and on input Fast Fourier Transform (FFT) size.

Abstract: A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed.

Abstract: An improved method and arrangement for detecting a watermark in an information (e.g. image or video) signal are disclosed. The detection is more reliable and less vulnerable to image processing by partitioning the image into a sequence of blocks having a predetermined size, accumulating the blocks, computing a value indicative of the correlation of the accumulated blocks and the watermark having the predetermined size, and detecting whether the correlation value is larger than a predetermined threshold.

Abstract: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that.

Abstract: A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodiment, the design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the Fourier transform coefficient matrix and the radix-4 butterfly. The resulting design provides an array comprised of a plurality of smaller base-4 matrices that can simply be added or removed to provide scalability of the design for applications involving different transform lengths to be calculated. In this embodiment, the systolic array size provides greater flexibility because it can be applied for use with any transform length which is an integer multiple of sixteen.

Abstract: A multi-pass frequency hop timing acquisition correlator that produces a more accurate time estimate from the fast acquisition frequency hop signal is disclosed. The time estimate produced by the multi-pass acquisition correlator is more accurate than the ¼ hop estimate produced by single-pass fast acquisition correlators. The multi-pass frequency hop timing acquisition correlator uses a time estimate generated by a previous pass through the multi-pass frequency hop timing acquisition correlator as a starting point for computing a new, more accurate, time estimate. Thus, the second pass through the multi-pass frequency hop timing acquisition correlator produces a time estimate that is relatively more accurate than the time estimate produced by the first pass. The more accurate time estimate produced by the multi-pass acquisition correlator reduces the hardware and time needed by the direct acquisition process to acquire the M-code.

Abstract: A system for identifying files can use fingerprints to compare various files and determine redundant files. Frequency representations of portions of files can be used, such as Fast Fourier Transforms, as the fingerprints.

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract: Methods and systems for determining characteristics of a Finite Impulse Response system that can include applying a number of identical sets of probe signals to the system and averaging the observed outputs. A discrete Fourier transform (DFT) of the averaged outputs can be obtained and the DFT components can be multiplied by corresponding transformed companion components related to the probe components. The system characteristics can be selected based on computing the inverse DFT of the resulting product components. The probe components can be taken from a circulant matrix of size S×S, or from an inverse DFT of a set of transform components consisting of arbitrary, non-zero, real numbers for first and last components of a partial set and arbitrary, non-zero, complex numbers for other components of the partial set to which the non-zero, complex number components of the partial set are added in reverse order and in complex conjugate.

Abstract: A method and apparatus is disclosed for performing blind source separation using convolutive signal decorrelation. For a first embodiment, the method accumulates a length of input signal (mixed signal) that includes a plurality of independent signals from independent signal sources. The invention then divides the length of input signal into a plurality of T-length periods (windows) and performs a discrete Fourier transform (DFT) on the, signal within each T-length period. Thereafter, estimated cross-correlation values are computed using a plurality of the averaged DFT values. A total number of K cross-correlation values are computed, where each of the K values is averaged over N of the T-length periods. Using the cross-correlation values, a gradient descent process computes the coefficients of a finite impulse response (FIR) filter that will effectively separate the source signals within the input signal. A second embodiment of the invention is directed to on-line processing of the input signal—i.e.

Abstract: An improved method and arrangement for detecting a watermark in an information (e.g. image or video) signal are disclosed. The detection is more reliable and less vulnerable to image processing by partitioning the image into a sequence of blocks having a predetermined size, accumulating the blocks, computing a value indicative of the correlation of the accumulated blocks and the watermark having the predetermined size, and detecting whether the correlation value is larger than a predetermined threshold.

Abstract: Computation of the Extended Discrete Fourier Transform (XDFT) for N×N input data (corresponding to an N×N image) gives additional information about each point in the image. This additional information can be presented in the form of a polar plot of magnitude vs. phase. Parameters derived from this plot allow novel parametric images to be obtained, giving additional information beyond that obtained by a conventional Discrete Fourier Transform. The plots can be manipulated (e.g. smoothed), corresponding to a new method of image processing for this kind of data. Applications of this new method are as widespread as the use of conventional Fourier transform analysis. The analysis is more computationally intensive than the well-known Fast Fourier Transform algorithm, but the extra information obtained and image processing capabilities can more than compensate for this.

Abstract: A general purpose network tone detection method and apparatus that allows the precise and accurate recognition of North American tones (MF, DTMF (Dual-Tone Multifrequency), and CPT (Call Progress Tones)) and international MF-R2 tones as well as taking into consideration other common tones such as Calling Card Service Prompt and Recall Dial. Through the use of the Discrete Fourier Transform (DFT) on small time windows and by providing phase continuity between these windows, the results of the successive DFTs may be combined and processed by a second DFT computation. This second DFT allows higher frequency resolution without requiring the re-computation of the DFT from the time samples. The resulting effect is a tone receiver with both high time and frequency resolution which consequently leads to robust and accurate tone recognition systems conforming even to the most stringent specification while maintaining low computational requirements.

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract: Discrete Fourier transformation is applied to an analog system so that a signal be transfering, the analog data can be corrected before being quantized and after being transferred and received. In the DFT cyclic decoder and the method of the same, a cyclic property of DFT code is used to induce a decoding way in the receiving end of a communication system. This way is used to design a basic decoding circuit and a fast decoding circuit structure. Since the decoding process is quick and the structure is simple so that the analog error correcting code is used widely.

Abstract: A time domain data converter with output frequency domain conversion. A data conversion circuit is operable to receive a signal in the time domain and provide an output in the frequency domain. It includes a data converter for converting data from an analog format to a digital format in the time domain. It also includes a processor for processing the data in the digital format output from the data converter through a time domain/frequency domain transform to provide data in the digital format in the frequency domain.

Abstract: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that.

Abstract: The present invention provides a method and apparatus for performing an inverse modified discrete cosine transform (IMDCT) on at least one block of spectral coefficients representing an information signal in the frequency domain. The IMDCT provides an IMDCT output including at least one block of processed samples in the time domain. The new and novel method of the present invention includes converting spectral coefficients in the block of spectral coefficients to provide a block of frequency domain processed complex samples and processing the block of frequency domain processed complex samples into the block of processed samples in the time domain.

Abstract: A method for time reference compensation in a power metering system, the method comprising monitoring a time-dependent characteristic of incoming AC power over a predetermined local time interval, comparing the monitored characteristic over the predetermined local time interval with the expected value of the characteristic based upon the nominal frequency of the AC power, and calculating a correction to one or more of local real-time and time-based measurements of the power metering system, based on the comparing.

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract: A digital channelizer/de-channelizer architecture that, with a minimum amount of hardware, is capable of dynamically adapting to changing system requirements. Preferably, the digital channelizer/de-channelizer, which is applied with a modified fast convolution algorithm, includes a plurality of dedicated, optimized, pipeline modules that may be dynamically adjusted for allocating and handling different bandwidths, a flexible number of channels, and simultaneous multiple standards.

Abstract: A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a communication symbol. The FFT/IFFT unit applies an FFT operation to the input data to generate intermediate data. The FFT/IFFT unit stores the intermediate data in a random access memory (RAM). The intermediate data stored in the RAM may override data used as input to the FFT operation. The FFT/IFFT unit selectively addresses the RAM to retrieve the intermediate data in a desired output order. For example, the FFT/IFFT unit may output the intermediate data in the same sequential order as the FFT/IFFT unit received the input data.

Abstract: A method for characterizing a dual frequency (DF) signal including the steps of sampling the signal at a sampling frequency vs so as to obtain a sequence of signal samples, and obtaining an &agr;-constant and a &bgr;-constant of the DF signal meeting a predetermined criterion.

Abstract: A Fast Chirp Transform (FCT) for the digital processing of chirp signals and exemplary applications. The FCT is a generalization of a multidimensional Fast Fourier Transform. Phase coefficients for boundary intervals are calculated using phase functions describing the time dependent frequency characteristics of an input signal in the time domain. A multidimensional FFT is performed on the dot product of the phase coefficients and the input signal resulting in a multidimensional representation of the input signal in the frequency domain. The FCT and its inverse can be used to enhance the signal to noise ratio in applications involving chirp signals.

Abstract: An improved method and arrangement for detecting a watermark in an information (e.g. image or video) signal are disclosed. The detection is more reliable and less vulnerable to image processing by subjecting the suspect image (q) and the watermark to be detected (w) to Symmetrical Phase Only Matched Filtering (24-28,16) prior to detecting (29) the amount of correlation (d) between said signals.