Abstract: A method for sampling a signal for signal processing, such as calculating the coefficients of a Fourier or other transform of the signal. The sampling occurs at sampling points which are the union of sets of points, each set being points separated by regular intervals of 1/pn where pn is a prime number. Where the signal is not accurately reconstructed from the sampled values the method recurses and increases the set of distinct primes. The invention relies upon the incommensurate nature of different primes to prevent the invention from degenerating into an inefficient sampling technique such as using regular intervals would provide. The scale, termed a D scale, is applicable to problems in diverse domains such as signal processing, including digital signal processing (DSP), image processing, scientific and engineering computational applications, data acquisition and statistical data analysis.

Abstract: The present invention increases the flexibility of the modified fast convolution algorithm. In a first exemplary embodiment of the present invention, a block compensator is inserted into the channelizer/de-channelizer processing chain for multiplying data in the processing chain with compensation constants. The block compensator corrects the phase continuity problem associated with the modified fast convolution algorithm to thereby allow unrestricted filter placement. In a second exemplary embodiment, the phase continuity problem is corrected by combining a frequency translation in the frequency domain with a compensatory frequency translation in the time domain. Both techniques increase the flexibility of the modified fast convolution algorithm whilst only marginally increasing computational requirements.

Abstract: The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14); a demultiplexer (16), coupled to the analog to digital converter, a window presum (102) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift (24′), coupled to I output groups of data words.

Abstract: Systems and methods for performing intelligent image processing. Image processing systems and methods in accordance with the present invention may select algorithms for processing collections of images by comparing algorithmic region of interest (aROI) data to stored human visual region of interest (hROI) data to select from a database of available transformation algorithms an optimal algorithm or group of algorithms to be used in transforming data comprising the collection or collections of images. The selected algorithm(s) may then be used, for example, in data compression, image enhancement or database query functions.

Abstract: First, at step Si, i=0 is set. At step S2, data comprising M samples is fetched. At step S3, an M-point DFT is applied to the data fetched at step S2 above. At step S4, an obtained y(k) is multiplied by a twist coefficient w(i, k). The result is placed in y(k). At step S5, the value in y(k) is overwritten to an array x which contains original data. The above processing is repeated N/M times through steps S6 and S7 until all the input data is processed. At step S9, an FFT with N/M (=2n) points is performed within the range of 0≦k<M. Finally, at step S12, a sort is performed.

Abstract: A digital channelizer employs a polyphase filter element in which a shift register is used to commutate time series data to a bank of polyphase filters at the inputs of an FFT module. The filter bank and FFT module are updated at a frequency that is independent of the rate that the data is fed into the buffer and filter/FFT cycle rates of less than the ratio of the input data rate to the number of input channels may be accommodated by the shift register commutation. The output of the FFT module is interpolation filtered by inserting interpolated points between adjacent data points in the channelized output stream to increase the output frequency by an integral multiple of the update rate of the polyphase filter/FFT update rate.

Abstract: This invention relates to a Fourier transformation device, in which when storing successively supplied data temporarily by deleting old data while obtaining the newest N data, a difference between a data value supplied just before and a data value to be deleted is supplied by a data updating portion, this supplied data value and a result of FFT operation just before, stored temporarily in a memory portion are supplied to a recursive DFT operating portion and these values are computed according to a predetermined method so as to output a result of the FFT operation with respect to the newest N data values.

Abstract: The invention is an apparatus and process for performing a discrete Fourier transform and a digital channelizer which divides an input bandwidth into at least some of N channels. An apparatus for performing a discrete Fourier transform in accordance with the invention includes at least one discrete Fourier transform computation stage (304, 305′, 402, 410, 412, 414, 419), the at least one discrete Fourier transform computation stage having N inputs representing preselected frequency bands with each input containing an input signal containing real data and P actual outputs each containing an output signal, P being less than N, at least one of the P actual output signals containing a conjugate of one of the N input frequency bands; and a processing device (602, 702), coupled to at least one P actual output containing a signal which is a conjugate, which processes the conjugate as representative of one of the N input frequency bands.

Abstract: The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24′), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26′) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.

Abstract: When obtaining the newest N data of successively supplied data while deleting old data to store them temporarily, a difference between a data value supplied just before and a data value to be deleted is supplied from a data updating portion. The difference value and a result of preceding FFT operation just before stored in a memory portion temporarily are supplied to a recursive DFT operating portion. These values are subjected to arithmetic operation according to a predetermined method so as to output the result of FFT operation on the newest N data values.

Abstract: A digital channelizer and a process for dividing input bandwidth into at least some of N channels are disclosed. The digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14), a demodulator (16) coupled to the analog to digital converter, a window presum (102) coupled to the parallel streams of data words and a discrete Fourier transform apparatus (26′), coupled to the N outputs of the window presum, having N inputs and which performs a discrete Fourier transform on the N inputs to output at least some of the N channels.

Abstract: A digital channelizer and a process for dividing an input bandwidth into at least some of N channels are disclosed.

Abstract: The present invention increases the flexibility of the modified fast convolution algorithm. In a first exemplary embodiment of the present invention, a block compensator is inserted into the channelizer/de-channelizer processing chain for multiplying data in the processing chain with compensation constants. The block compensator corrects the phase continuity problem associated with the modified fast convolution algorithm to thereby allow unrestricted filter placement. In a second exemplary embodiment, the phase continuity problem is corrected by combining a frequency translation in the frequency domain with a compensatory frequency translation in the time domain. Both techniques increase the flexibility of the modified fast convolution algorithm whilst only marginally increasing computational requirements.

Abstract: A modified fast convolution algorithm may be enhanced in order to increase the flexibility of the algorithm. In an exemplary embodiment of the present invention, a folding unit is introduced as a pre-processing stage prior to the Inverse Discrete Fourier Transform (IDFT) in the receiver. The folding unit adds outer frequency components onto inner frequency components in the frequency domain in order to produce a reduced set of frequency components. In an alternative embodiment, an unfolding unit is introduced as a post-processing stage after the Discrete Fourier Transform (DFT) in the transmitter. The unfolding unit expands the set of the set of frequency components by adding translated original components outside the original set. The folding and unfolding processes increase the flexibility of the modified fast convolution algorithm by reducing the number of operations per second that have to be performed for the channel-specific parts of the algorithm.

Abstract: A system for wireless communication between a base station 30 and one or more remote stations 32 and 34 wherein a desired signal has associated therewith an identifier tone (a SAT in the vernacular of the AMPS system) and wherein interfering signals may have associated therewith identifier tones at different frequencies. A superresolution technique is used in the system to process the received data and to determine the relative magnitudes of any identifier tones which may be present in the received data. In the disclosed embodiment, the superresolution technique utilized is a least square error process. The resulting estimates are used by the system to facilitate the communication function.

Abstract: An orthogonal transform apparatus has: orthogonal transform circuit for performing n-dimensional s-order (n and s are natural numbers) orthogonal transform, modified-information control circuit for performing control in accordance with modified information for outputting n-dimensional m-order data as n-dimensional p-order data (m and p are natural numbers), and rearrangement circuit for performing the following in accordance with the control by said modified-information control circuit: (1) m-p data values from the high-order side out of m-order input data values are set to 0 when m is equal to s and m is larger than p, p-m data values are added to the high-order side among m-order input data values to rearrange the data values when m is smaller than p, or data values are left as they are when m is equal to p; (2) the data values in said Item (1) are rearranged after discarding m-s data values from the high-order side of said m-order input data values before rearranging the data values in said Item (1) whe

Abstract: A high-speed discrete Fourier transform (DFT) apparatus utilizes a processor operating in parallel with data acquisition to calculate terms of a Fourier transform corresponding to the incoming data. Since the processor calculates the Fourier terms in real-time, overall transformation time is substantially reduced and is limited by only the data acquisition time. In another aspect, substantial reduction of the number of computations are achieved by transforming the plurality of terms in Fourier equations at the same time. In a further aspect, the high-speed DFT is advantageously applied to a network analyzer which obtains a transfer function of a device in a frequency domain and converts the transfer function to a time domain response to a simulated test signal.

Abstract: Supervisory audio tone (SAT) in a receive signal in a wireless communications system is detected using a discrete Fourier transform (DFT) supplied with samples of a filtered and decimated signal derived from the receive signal. The DFT can comprise M 2-input butterfly computation stages for computing an N-point DFT where N=2M. Each of the stages m from 1 to M−1 determines and stores, for each current sample at the input, at most 2m intermediate results forming only a subset of intermediate results required for computation by the next stage. Each of up to 2m other intermediate results required for computation by the next stage is produced by shifting of a respective stored intermediate result of the respective subset determined in respect of an input sample preceding the current sample by 2M−m−1 samples. For example there are M=5 stages for a 32-point DFT having 18 outputs, 6 outputs for each of three SAT frequencies.

Abstract: A method and apparatus that performs blind source separation using convolutive signal decorrelation. More specifically, the method accumulates a length of input signal (mixed signal) that includes a plurality of independent signals from independent signal sources. The invention then divides the length of input signal into a plurality of T-length periods (windows) and performs a discrete Fourier transform (DFT) on the signal within each T-length period. Thereafter, estimated cross-correlation values are computed using a plurality of the averaged DFT values. A total number of K cross-correlation values are computed, where each of the K values is averaged over N of the T-length periods. Using the cross-correlation values, a gradient descent process computes the coefficients of a finite impulse response (FIR) filter that will effectively separate the source signals within the input signal.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: With reference to FIG. 1 signal processor (10) for performing transformations of sets of input data points comprises a memory for storing a first half input data points and a second half input data points, an adder unit for pairwise adding one real part of each one first half input data point and a second half input data point and providing adder output data, and a computing unit for performing transformations upon the adder output data. Addition for data reduction and data transformation are carried out simultaneously by different units.

Abstract: A receiver and channelizer for processing a wideband signal is disclosed. The channelizer consists of a receiver for receiving a wideband signal. The received wideband signal is processed by a subsampled DFT-channelizer to extract a selected number of regularly spaced channels from a plurality of channels within the received wideband signal. These extracted regularly spaced channels are then output for further processing by a receiver.

Abstract: An apparatus and a method perform an N-point Fast Fourier Transform (FFT) on first and second arrays having real and imaginary input values using a processor with a multimedia extension unit (MEU), wherein N is a power of two. The invention repetitively sub-divides the N-point Fourier Transform into N/2-point Fourier Transforms until only a 2-point Fourier Transform remains. Next, it vector processes the 2-point Fourier Transform using the MEU and cumulates the results of the 2-point Fourier Transforms from each of the sub-divided N/2 Fourier Transforms to generate the result of the N-point Fourier Transform.

Abstract: A channelizer for processing a wideband signal to extract a plurality of narrowband signals is disclosed. The channelizer is capable of processing a received wideband signal to extract a plurality of regularly spaced narrowband signals therefrom. The wideband signal is processed in such a manner that the extracted narrowband signals have a sampling frequency that is not limited to an integer multiple of the channel spacing and is valid for any combination of downsampling factors and number of channels.

Abstract: Parallel signal processor (10) (FIG. 2) performs a Fourier Transformation of an input signal; The transformation coefficients are converted once to logarithmic form and stored in a cache memory. The input data is converted serially to logarithmic form, and fed to all processing units in parallel. The processing units compute their respective products as additions in the logarithmic domain. Then, the products are converted back to the normal domain. The products with the correct sign are summed by an accumulator of the respective processing element. After the last signal data point has run through the processing elements and the last products are added to their respective sums, all complex output signal data points are complete simultaneously.