Discrete Fourier Transform (i.e., Dft) Patents (Class 708/405)
  • Patent number: 8484275
    Abstract: There is provided a method for generating a table for reordering the output of a Fourier transform, the Fourier transform being performed on a predefined number of input samples, the method comprising performing one or more decomposition stages on a sequence corresponding in number to the predefined number of input samples to form a representation of the output of the Fourier transform; wherein at least one of the decomposition stages comprises a composite operation that is equivalent to two or more operations; and rearranging the representation of the output of the Fourier transform to generate a reordering table.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: July 9, 2013
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Neil Kenneth Thorne
  • Publication number: 20130173680
    Abstract: A fixed-coefficient variable prime length recursive discrete Fourier transform system includes a pre-processing device, a real-part computation device, an imaginary-part computation device and a post-processing device. The pre-processing device receives N digital input signals and performs order permutation operation to generate first and second temporal signals, wherein N is a prime number. The real-part computation device receives the real part of the first and second temporal signals and performs discrete cosine/sine transform to generate third and fourth temporal signals. The imaginary-part computation device receives the imaginary part of the first and second temporal signals and performs discrete cosine/sine transform to generate fifth and sixth temporal signals.
    Type: Application
    Filed: July 25, 2012
    Publication date: July 4, 2013
    Inventors: Sheau Fang LEI, Shin Chi LAI, Chuan An CHANG
  • Publication number: 20130159369
    Abstract: A Discrete Fourier Transform (DFT) apparatus is provided. The DFT apparatus includes a first delay, a second delay, an operator, and a multiplier. The first delay delays one sampling data by N-sample in a time axis when the one sampling data is input. The second delay delays an output value of a frequency component for a previous sampling data by 1-sample. The operator performs an operation based on the input one sampling data, the one sampling data delayed by the N-sample in the time axis, and the 1-sample delayed output value of the frequency component for the previous sampling data. The multiplier multiplies an output value from the operator by a twiddle factor ? j ? 2 ? ? ? ? ? kn N . Therefore, a complexity of a stream DFT operation can be reduced.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 20, 2013
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Patent number: 8438204
    Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 7, 2013
    Assignee: LSI Corporation
    Inventor: David Noeldner
  • Patent number: 8386552
    Abstract: In a data processing system, having a twiddle factor unit, a method for performing a mixed-radix discrete Fourier transform (DFT) having a block size, N, and a maximum block size, Nmax, wherein the maximum block size includes a radix that is not a power of 2 is provided. The method includes receiving a delta value at an input of the twiddle factor unit, the delta value representing a ratio of a modified maximum bock size to the block size, wherein the modified maximum block size is a power of 2. The method further includes using the delta value to obtain a step size for generating indices of a look-up table stored within the twiddle factor unit, wherein the look-up table stores real and imaginary components of twiddle factors corresponding to a set of block sizes of the DFT.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: February 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ning Chen, Jayakrishnan C. Mundarath, Pornchai Pawawongsak
  • Patent number: 8380331
    Abstract: Methods and apparatus for relative pitch tracking of multiple arbitrary sounds. A probabilistic method for pitch tracking may be implemented as or in a pitch tracking module. A constant-Q transform of an input signal may be decomposed to estimate one or more kernel distributions and one or more impulse distributions. Each kernel distribution represents a spectrum of a particular source, and each impulse distribution represents a relative pitch track for a particular source. The decomposition of the constant-Q transform may be performed according to shift-invariant probabilistic latent component analysis, and may include applying an expectation maximization algorithm to estimate the kernel distributions and the impulse distributions. When decomposing, a prior, e.g. a sliding-Gaussian Dirichlet prior or an entropic prior, and/or a temporal continuity constraint may be imposed on each impulse distribution.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: February 19, 2013
    Assignee: Adobe Systems Incorporated
    Inventors: Paris Smaragdis, Gautham J. Mysore
  • Publication number: 20130039165
    Abstract: A discrete Fourier calculation device includes a twiddle factor table storage unit that stores therein a twiddle factor table that associates twiddle factors with phases of the corresponding twiddle factors; a correction value specifying unit that specifies first and second correction values for correcting a phase of an input signal in accordance with an amplitude of the input signal; a generating unit that corrects the phase of the input signal by using the specified first and second correction values to generate first and second phases; an addition unit that adds an arbitrary phase corresponding to an arbitrary twiddle factor stored in the twiddle factor table, to each of the generated first and second phases; and a rotation calculation unit that acquires, from the twiddle factor table, first and second twiddle factors corresponding to the first and second phases and sums the acquired first and second twiddle factors.
    Type: Application
    Filed: June 27, 2012
    Publication date: February 14, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Jun KAMEYA
  • Patent number: 8375075
    Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyung Jin Kim, Seong Chul Cho, Dae Ho Kim, Yeong Jin Kim
  • Patent number: 8351525
    Abstract: An orthogonal frequency division multiplexing (OFDM) receiving apparatus, including a receiving unit, a subcarrier demodulation unit and a signal output processing unit, is provided. The receiving unit is for receiving an RF signal to generate a set of discrete signals. The subcarrier demodulation unit is coupled to the receiving unit, and used for demodulating a set of discrete signals to obtain a complex signal. The signal output processing unit is coupled to the subcarrier demodulation unit, and used for capturing and outputting real parts of the complex signal.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 8, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Huan-Chun Wang, De-Jhen Huang, Chang-Lan Tsai
  • Patent number: 8346836
    Abstract: An apparatus and method for area and speed efficient fast Fourier transform (FFT) processing comprising mapping a one-dimensional DFT to a multi-dimensional representation; re-indexing the multi-dimensional representation as a radix 23 decimation architecture; simplifying the radix 23 decimation architecture to obtain a nested butterfly architecture; acquiring N samples of a finite duration time-sampled signal; and inputting the acquired N samples into the nested butterfly architecture to obtain a N-point fast Fourier transform (FFT) output.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: January 1, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Vincent Loncke
  • Publication number: 20120254274
    Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: SAANKHYA LABS PVT. LTD.
    Inventors: Gururaj Padaki, Saurabh Mishra, Suman Sanisetty
  • Patent number: 8279978
    Abstract: A method for receiving a pilot symbol in a receiver is disclosed. In one embodiment, the method includes removing a cyclic prefix from a received sequence to produce a modified sequence, transforming the modified sequence to a first frequency domain sequence according to a first transform, demapping a plurality of distributed subcarriers in the transformed modified sequence to extract a plurality of received symbols, deriving an intermediate channel estimate for each of the plurality of received symbols, and interpolating a final channel estimate based on the plurality of derived intermediate channel estimates. In one exemplary embodiment, the received symbols have one or more predefined characteristics such as a constant amplitude, and zero autocorrelation (CAZAC sequence).
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 2, 2012
    Assignee: Apple Inc.
    Inventor: James W. McCoy
  • Patent number: 8274726
    Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for simulating propagation of an electromagnetic field, performing phase retrieval, or sampling a band-limited function. A system practicing the method generates transformed data using a discrete Fourier transform which samples a band-limited function f(x) without interpolating or modifying received data associated with the function f(x), wherein an interval between repeated copies in a periodic extension of the function f(x) obtained from the discrete Fourier transform is associated with a sampling ratio Q, defined as a ratio of a sampling frequency to a band-limited frequency, and wherein Q is assigned a value between 1 and 2 such that substantially no aliasing occurs in the transformed data, and retrieves a phase in the received data based on the transformed data, wherein the phase is used as feedback to an optical system.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: September 25, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Bruce H. Dean, Jeffrey Scott Smith, David L. Aronstein
  • Patent number: 8271569
    Abstract: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: September 18, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayakrishnan C. Mundarath, Leo G. Dehner, Kevin B. Traylor
  • Patent number: 8145695
    Abstract: The present invention discloses a signal processing method and a data processing method and apparatus. A time-domain to frequency-domain signal processing method includes: pre-processing time-domain data; pre-rotating the pre-processed data by using a rotation factor a·WNn+0.5; performing a discrete Fourier transform (DFT) of N/4 points on the pre-rotated data; and post-rotating the data transformed by the DFT by using a rotation factor b·WNk+0.5 to obtain frequency-domain data. A frequency-domain to time-domain signal processing method includes: twiddling frequency-domain data; pre-rotating the twiddled data by using a rotation factor c·WNk+0.5; performing a DFT of N/4 points on the pre-rotated data; and post-rotating the data transformed by the DFT by using a rotation factor d·WNn+0.5; and post-processing the post-rotated data to obtain time-domain data. The present invention increases the efficiency of signal processing.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 27, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Deming Zhang, Haiting Li
  • Publication number: 20120066162
    Abstract: The adaptive filtering techniques described herein allow a filter that is operating in a target domain to be trained in another domain, possibly with constraints, using the same adaptation framework used in a standard adaptive filter. As a result, the adaptation engine may be configured to run in a transform domain that is more desirable than the target domain. For example, the transform domain may be less susceptible to noise or may have more impact on the trained filter's desired results. The filter is trained in the transform domain and then the filter hardware is updated in the target domain.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Milind Anil Borkar, Fernando Alberto Mujica
  • Publication number: 20120013965
    Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for simulating propagation of an electromagnetic field, performing phase retrieval, or sampling a band-limited function. A system practicing the method generates transformed data using a discrete Fourier transform which samples a band-limited function f(x) without interpolating or modifying received data associated with the function f(x), wherein an interval between repeated copies in a periodic extension of the function f(x) obtained from the discrete Fourier transform is associated with a sampling ratio Q, defined as a ratio of a sampling frequency to a band-limited frequency, and wherein Q is assigned a value between 1 and 2 such that substantially no aliasing occurs in the transformed data, and retrieves a phase in the received data based on the transformed data, wherein the phase is used as feedback to an optical system.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 19, 2012
    Inventors: BRUCE H. DEAN, Jeffrey Scott Smith, David L. Aronstein
  • Publication number: 20110283099
    Abstract: Techniques are described herein for privately aggregating distributed time-series data. A requestor provides a query sequence to users. Each user evaluates the query sequence on the user's time-series data to determine an answer sequence. Each user transforms its answer sequence to another domain, adds noise, and encrypts it for further processing by the requestor. The requestor combines these encrypted sequences in accordance with a homomorphic encryption technique to provide an encrypted summation sequence. The requestor provides the encrypted summation sequence to at least some of the users, who may in turn provide respective decryption shares to the requestor. The requestor combines the decryption shares in an effort to decrypt the encrypted summation sequence. Decrypting the encrypted summation sequence provides a summation of the encrypted sequences from the users, which may be transformed back to the original domain to estimate a summation of the answer sequences of the users.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Suman Nath, Vibhor Rastogi
  • Publication number: 20110219052
    Abstract: Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 8, 2011
    Applicant: ALTERA CORPORATION
    Inventor: Martin Langhammer
  • Patent number: 8015226
    Abstract: Methods and apparatus are provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a discrete Fourier Transform (DFT), such as a power-of-two DFT, on the extended input sequence to obtain an interpolated sequence; and applying a conversion matrix to the interpolated sequence to obtain a DFT output for the input sequence of length N. The input sequence of length N can be extended to an extended input sequence of length M, for example, by employing a zero padding technique, a cyclic extension technique, a windowing of a cyclic extended sequence technique or a resampling-based interpolation technique to extend the input sequence. The conversion matrix is substantially a sparse matrix.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: September 6, 2011
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Patent number: 8010588
    Abstract: The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one enhanced DFT module is provided by using at least one type of DFT module including multiplication by first and second types of twiddle factors in respective different multiplication stages separated by an intermediate integration stage, and generating the enhanced DFT module by combining the at least one type of DFT module with a recursive stage configured to multiply by a third type of twiddle factor and to selectively switch between a bypass function and a butterfly function in said recursive stage. Thereby, an implementation of non 2x-radix Fourier transformation can be achieved with moderate hardware complexity.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 30, 2011
    Assignee: Nokia Corporation
    Inventors: Yuhuan Xu, Ludwig Schwoerer
  • Patent number: 8005883
    Abstract: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: August 23, 2011
    Inventor: Walter E. Pelton
  • Publication number: 20110185001
    Abstract: The present invention discloses a signal processing method and a data processing method and apparatus. A time-domain to frequency-domain signal processing method includes: pre-processing time-domain data; pre-rotating the pre-processed data by using a rotation factor a·WNn+0.5; performing a discrete Fourier transform (DFT) of N/4 points on the pre-rotated data; and post-rotating the data transformed by the DFT by using a rotation factor b·WNn+0.5 to obtain frequency-domain data. A frequency-domain to time-domain signal processing method includes: twiddling frequency-domain data; pre-rotating the twiddled data by using a rotation factor c·WNn+0.5; performing a DFT of N/4 points on the pre-rotated data; and post-rotating the data transformed by the DFT by using a rotation factor d·WNn+0.5; and post-processing the post-rotated data to obtain time-domain data. The present invention increases the efficiency of signal processing.
    Type: Application
    Filed: April 13, 2011
    Publication date: July 28, 2011
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Deming ZHANG, Haiting Li
  • Publication number: 20110054693
    Abstract: According to various embodiments, a method is provided for determining aberration data for an optical system. The method comprises collecting a data signal, and generating a pre-transformation algorithm. The data is pre-transformed by multiplying the data with the pre-transformation algorithm. A discrete Fourier transform of the pre-transformed data is performed in an iterative loop. The method further comprises back-transforming the data to generate aberration data.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Applicants: Space Admi
    Inventor: BRUCE H. DEAN
  • Patent number: 7895420
    Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Anup Hosangadi, Ryan C. Kastner
  • Patent number: 7852955
    Abstract: An orthogonal frequency division multiplexing (OFDM) transmitting apparatus including a signal processing unit, a subcarrier orthogonalization processing unit, and a transmitting unit is provided. The signal processing unit divides a received signal into several real parts and several corresponding imaginary parts. The subcarrier orthogonalization processing unit is coupled to the signal processing unit for receiving the real and the imaginary parts of the signal, and for making the real and the imaginary parts respectively carried by a plurality of different and orthogonal subcarriers. The transmitting unit is coupled to the subcarrier orthogonalization processing unit to transmit the subcarriers.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 14, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Huan-Chun Wang, De-Jhen Huang, Chang-Lan Tsai
  • Publication number: 20100305729
    Abstract: An audio channel of a time-based media presentation provides a basis for synchronizing to the presentation across a variety of platforms independent of when and where the presentation is being viewed. By pre-processing the media into a series of non-unique hashes, and similarly processing an audio stream of the media captured at a client device, a comparison can be made that yields an accurate time offset within the presentation. The comparison may usefully be performed over a data network using a server that hosts data from the pre-processed media, and a variety of applications may be deployed on the client device based on the resulting synchronization.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Inventors: Hans M. Glitsch, Ajay Shah
  • Publication number: 20100306298
    Abstract: A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appropriate multipliers to obtain the desired DFT terms. Unused multipliers are tied to constant input values, in order to minimize dynamic power.
    Type: Application
    Filed: May 15, 2008
    Publication date: December 2, 2010
    Applicant: Qualcomm Incorporated
    Inventors: Andrea Cenciotti, Nestor Lucas Barriola, Philip John Young
  • Publication number: 20100293214
    Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 18, 2010
    Inventor: Lester Anderson Longley
  • Patent number: 7817733
    Abstract: A system (100) and method (400) for peak limiting suitable for use in a communication system is provided. The method can include modulating (402) a symbol vector to produce a modulated waveform (500), wherein the symbol vector contains at least one symbol in at least one subcarrier (130), computing (404) at least one symbol adjustment that is based on at least one peak overshoot (512) of the modulated waveform, and applying (406) the at least one symbol adjustment to the symbol vector in accordance with an assigned weighting for reducing a peak power of the modulated waveform. The method limits an energy in the at least one subcarrier to a prespecified level of distortion.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 19, 2010
    Assignee: Motorola Mobility, Inc.
    Inventor: Stephen R. Carsello
  • Patent number: 7808886
    Abstract: Methods (500, 800) and corresponding systems (100, 200, 300, 400, 900) for generating a pilot symbol (330) include providing an M-point parallel transform sequence that is a discrete Fourier transform of a CAZAC sequence (312, 504-508). The M-point parallel transform sequence (312) is distributed (316, 510) to a set of M subcarriers among N subcarriers to form an N-point frequency-domain sequence (318) wherein the M subcarriers are evenly spaced apart. An N-point inverse fast Fourier transform (320, 512) is performed to convert the N-point frequency-domain sequence to an N-point time-domain sequence (322). The N-point time-domain sequence is converted (324, 514) to a serial sequence (326), and a cyclic prefix is added (328, 516) to the serial sequence to form a pilot symbol (330).
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: October 5, 2010
    Assignee: FreeScale Semiconductor, Inc.
    Inventor: James W. McCoy
  • Patent number: 7792894
    Abstract: A computer system is configured to create a product matrix of data from two matrices of data through the use of a representation in a group algebra. The matrices are represented in a group algebra based on a mathematical group adhering to certain criteria. Then the representations are mapped to vectors in a multidimensional vector space where their product can be obtained by reduction into a block-diagonal matrix multiplication which can be recursively computed by the same process. Multiple matrix multiplications can also be performed simultaneously though selection of a group which satisfies certain properties. Through this process, computational time improvements are obtained.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: September 7, 2010
    Assignees: Microsoft Corporation, California Institute of Technology
    Inventors: Henry L. Cohn, Balázs Szegedy, Christopher M. Umans
  • Patent number: 7787546
    Abstract: A subscriber station for use in a wireless network capable of communicating according to a multi-carrier protocol, such as OFDM or OFDMA. The subscriber station comprises a size M Fourier Transform (FFT or DFT) block for receiving input symbols and generating M FT pre-coded outputs and a size N inverse Fourier Transform (IFFT or IDFT) block capable of receiving N inputs, where the N inputs include the M FT pre-coded outputs from the size M FT block. The size N IFT block generates N outputs to be transmitted to a base station of the wireless network. The input symbols comprise user data traffic to be transmitted to the base station. The size N IFT block also receives signaling and control information on at least some of N-M inputs. The FT pre-coding generates a time-domain signal that has a relatively lower peak-to-average power ratio (PAPR).
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 31, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Farooq Khan
  • Publication number: 20100191791
    Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 29, 2010
    Inventors: Arun Mohanlal Patel, Paul Chow
  • Publication number: 20100190198
    Abstract: Among other things, a combination comprises interaction with a system that has a perturbation. In such perturbed system, a non-directional input is applied to a first variable of the system. Based on an asymmetry of the perturbed system, a directional effect is achieved in a second variable of the system, the first and second variables comprising a conjugate pair of variables. At least one of the following pertains: the interaction occurs other than by an apparatus and other than in a way that actually achieves the directional effect, or the conjugate pair is other than position and momentum, or the input or the asymmetry are in a dimension other than spatial coordinates, or the directional effect is other than translational motion and other than rotary motion.
    Type: Application
    Filed: August 18, 2009
    Publication date: July 29, 2010
    Inventors: Osman Kibar, Mirianas Chachisvilis, Eugene Tu
  • Publication number: 20100177906
    Abstract: Certain aspects of the present disclosure provide methods for distributed sensing and centralized reconstruction of two correlated signals, modeled as the input and output of an unknown sparse filtering operation.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 15, 2010
    Applicant: QUALCOMM Incorporated
    Inventors: Martin Vetterli, Ali Hormati, Olivier Roy, Yue M. Lu
  • Patent number: 7752249
    Abstract: A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is therefore reduced. In order to enhance the access efficiency of the memory and the use efficiency of a processor, the transformer adopts a modified in-place conflict-free addressing to achieve similar performance of a traditional Fast Fourier Transform device.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: July 6, 2010
    Assignee: Industrial Technology Research Institute
    Inventor: Chi-Li Yu
  • Publication number: 20100166106
    Abstract: An arithmetic processing apparatus includes a shift section configured to shift, by (N+1)/2 bit data, a data signal x(n) (n=0, . . . , N?1), which has a data length of N, where N is an odd number, and which has left-right symmetry with respect to ((N?1)/2)th bit data, so as to obtain a data signal x?(n), and an arithmetic operation section configured to obtain a data signal X(k) (k=0, . . . , N?1) by performing a discrete Fourier transform operation on the data signal x?(n).
    Type: Application
    Filed: December 23, 2009
    Publication date: July 1, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Jun KAMEYA
  • Publication number: 20100161699
    Abstract: Provided are a high-speed Discrete Fourier Transform (DFT) apparatus and a method thereof. The high-speed DFT apparatus includes a zero padding unit, a Fast Fourier Transform (FFT) unit, and a preamble index decision unit. The zero padding unit receives a first input signal having a length of a prime number and changes the first input signal into a second input signal having a length of an exponentiation of 2. The FFT unit performs a FFT on the second input signal outputted from the zero padding unit. The preamble index decision unit detects a preamble index from an output signal from the FFT unit.
    Type: Application
    Filed: September 30, 2009
    Publication date: June 24, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyung Jin KIM, Seong Chul CHO, Dae Ho KIM, Yeong Jin KIM
  • Publication number: 20100161700
    Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Applicant: LSI Corporation
    Inventor: David Noeldner
  • Publication number: 20100150365
    Abstract: If K=4N, wherein K is a number of subbands and N is a decimation ratio, an analysis filter process unit 21 is used to perform an analysis filter process for every N samples of real-valued input data and output K samples of real-valued data. A GDFT/SSB modulation batch process unit (81) performs a GDFT process and an SSB modulation process on the outputted data by using a real-valued matrix calculation using a (K/2)×K real-valued matrix to output 1 sample×(K/2) channel of real-valued subbands data. Moreover, an SSB demodulation/inverse GDFT batch process unit (82) performs an SSB demodulation process and an inverse GDFT process on 1 sample×(K/2) channel of real-valued subbands data by a real-valued matrix calculation using a K×(K/2) real-valued matrix and outputs K samples of real-valued data. The outputted data is subjected to a synthesis filter process by a synthesis filter process unit (24) to output N samples of real-valued data.
    Type: Application
    Filed: March 26, 2008
    Publication date: June 17, 2010
    Inventor: Sakae Fujimaki
  • Patent number: 7734673
    Abstract: An automatic control device having an input for inputting measured values of cyclic voltage and/or current; computing device for computing a parameter based on said values of voltage and/or current, and for comparing the computed parameter against a predefined condition; and initiating device for initiating a control function in response to the parameter meeting the predefined condition. The input of the control device is arranged to input a predefined number of samples per one cycle; and the computing device is arranged to compute the parameter with a discrete Fourier transform algorithm optimized based on fixed coefficients related to the predefined number of samples per cycle. An exemplary control device and corresponding control method can provide a significantly faster response time than the earlier general programmed solutions without increasing the related costs as much as the known digital signal processors.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: June 8, 2010
    Assignee: ABB Oy
    Inventor: Markus Lönn
  • Patent number: 7720897
    Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: May 18, 2010
    Assignee: InterDigital Technology Corporation
    Inventors: Ryan Samuel Buchert, Sharif M. Shahrier, Peter Edward Becker
  • Patent number: 7720162
    Abstract: Techniques for efficiently performing partial FFT for subcarriers of interest are described. The N total subcarriers may be arranged into M sets. Each set may contain K subcarriers uniformly distributed across the N total subcarriers, where M·K=N. For the partial FFT, pre-processing is initially performed on time-domain samples to obtain intermediate samples. The pre-processing may include performing M-point FFTs on the time-domain samples and multiplying the FFT outputs with unit complex values. For each set of subcarriers of interest, a K-point FFT is performed on a set of intermediate samples to obtain a set of frequency-domain symbols for that set of subcarriers. Since K is typically much smaller than N, substantial savings in computation and power may be realized when only one or few sets of subcarriers are of interest.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: May 18, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: Raghuraman Krishnamoorthi
  • Publication number: 20100121617
    Abstract: An apparatus for simulating a signal composed of a plurality of individual signals from respective signal locations at a simulation location, having a provider for providing the plurality of individual signals in the time domain, a transformer for transforming the individual signals to the frequency domain, a processor for processing the individual signals transformed to the frequency domain each depending on a signal channel existing between the simulation location and the respective signal location, a combiner for combining the processed individual signals transformed to the frequency domain to a combined signal, and a transformer for transforming the combined signal to the time domain for generating the simulated combined signal at the simulation location.
    Type: Application
    Filed: August 30, 2007
    Publication date: May 13, 2010
    Inventors: Uwe Gruener, Anreas Klose, Rainer Perthold, Roland Zimmermann
  • Publication number: 20100106760
    Abstract: To implement processing for plural orthogonal transforms having different transform bases and implement a response to processing in new coding standards, using one orthogonal transform unit, with regard to orthogonal transform which is a basic process in still picture and moving picture coding.
    Type: Application
    Filed: July 23, 2008
    Publication date: April 29, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Hideki Kuroki
  • Publication number: 20100106758
    Abstract: A system described herein includes a selector component that receives input data that is desirably transformed by way of a Discrete Fourier Transform, wherein the selector component selects one of a plurality of algorithms for computing the Discrete Fourier Transform from a library based at least in part upon a size of the input function. An evaluator component executes the selected one of the plurality of algorithms to compute the Discrete Fourier Transform, wherein the evaluator component causes leverages shared memory of a processor to compute the Discrete Fourier Transform.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 29, 2010
    Applicant: Microsoft Corporation
    Inventors: Naga K. Govindaraju, David Brandon Lloyd, Yuri Dotsenko, Burton Jordan Smith, Jon L. Manferdelli
  • Patent number: 7693034
    Abstract: A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: April 6, 2010
    Assignee: Sasken Communication Technologies Ltd.
    Inventors: Balvinder Singh, Suyog Moogi
  • Patent number: 7676336
    Abstract: According to an inventive scheme for introducing a watermark into an information signal, the information signal is at first transferred from a time representation to a spectral/modulation spectral representation). The information signal is then manipulated in the spectral/modulation spectral representation in dependence on the watermark to be introduced to obtain a modified spectral/modulation spectral representation, and subsequently an information signal provided with a watermark is formed based on the modified spectral/modulation spectral representation. An advantage is that, due to the fact that the watermark is embedded and/or derived in the spectral/modulation spectral representation or range, traditional correlation attacks as are used in watermark methods based on a spread-band modulation cannot succeed easily.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: March 9, 2010
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Juergen Herre, Ralph Kulessa, Sascha Disch, Karsten Linzmeier, Christian Neubauer, Frank Siebenhaar
  • Patent number: RE44105
    Abstract: A subscriber station for use in a wireless network capable of communicating according to a multi-carrier protocol, such as OFDM or OFDMA. The subscriber station comprises a size M Fourier Transform (FFT or DFT) block for receiving input symbols and generating M FT pre-coded outputs and a size N inverse Fourier Transform (IFFT or IDFT) block capable of receiving N inputs, where the N inputs include the M FT pre-coded outputs from the size M FT block. The size N IFT block generates N outputs to be transmitted to a base station of the wireless network. The input symbols comprise user data traffic to be transmitted to the base station. The size N IFT block also receives signaling and control information on at least some of N-M inputs. The FT pre-coding generates a time-domain signal that has a relatively lower peak-to-average power ratio (PAPR).
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Farooq Khan