Abstract: Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Abstract: In a data processing method, a remainder R that is produced during the division of an integer A by a prescribed integer B is calculated recursively. For this purpose, a data symbol word representing the integer A is decomposed into K data symbol part-words W0, W1, WK−1 of word length L, and in each recursion step a function F determined by the numbers B and L is applied to an argument that depends on the function value Fi−1 obtained in the preceding recursion step, and on a data symbol part-word WK−i.

Abstract: A Sweeney, Robertson, Tocher (SRT) divider for use in a computer system has recoding circuitry to recode the three most significant bits of the dividend into one-hot form as the dividend is loaded into a quotient/partial remainder register. With each clock, a partial remainder is generated also having its most significant three bits in one-hot form and the remaining bits in binary encoded form. The divider has several stages permitting it to generate several bits of quotient in each clock cycle. Each stage has circuitry for estimating a quotient digit, and for computing a partial remainder by subtracting the product of the quotient digit times the divisor from either the dividend or a previous partial remainder. This subtraction is performed upon a one-hot code in the most significant bits and in binary code on the least significant bits. The divider also has circuitry for assembling a plurality of quotient digits into a quotient.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: In accordance with the preferred embodiment of the present invention a gain (A) is determined and utilized to cyclically converge upon a quotient (Q). More particularly, once A is determined, an estimate of QN is multiplied by Y to estimate {circumflex over (X)}N, where Q=X/Y. The value of {circumflex over (X)}N is then subtracted from X to determine an error (eN), which is multiplied by A. The value of AeN(n) is added to AeN(n−1) to produce an estimate of Q. Once convergence has occurred, the value for Q is output from the circuitry.

Abstract: A quantization circuit includes a set of prime number dividers that can be implemented as look-up tables and a shifter. A shifter implements divisions by prime number (two) and by powers of two. Multiplexing circuitry interconnects the prime number dividers to permit performance of a series of prime number divisions in a single clock cycle. The quantization circuit can thus implement one-cycle divisions by divisors that are products of the prime numbers and powers of two in the series that the multiplexing circuitry selects. For divisors that are longer series of the prime numbers implemented in the quantization circuit, the quantization circuit can implement multi-cycle divisions by feeding an output signal back through further series of the prime number dividers.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

Abstract: A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respective bit blocks, table reference means finds solutions z(1) to z(4) obtained by dividing, by a divisor x, values expressed by replacing the bits other than the bits in each bit block with 0, while referring to tables (1) to (4) stored in storage means. Addition means adds all the solutions z(1) to z(4) to find the solution z.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

Abstract: A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first data element by a most significant word of the second data element. A test is performed to determine if the result of the division performed corresponds to a word of the final result sought. The first data element is modified by subtracting from it a data element produced by multiplying the second data element by the word of the final result sought that has been previously produced.

Abstract: One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is initialized with a value M; and a register V that is initialized with a value 0. The system also includes a counter CA that indicates an upper bound for the most-significant non-zero bit of register A. It also includes a counter CB that indicates an upper bound for the most-significant non-zero bit of register B. The system additionally includes a temporary register H, and a temporary register L. An updating mechanism is configured to iteratively reduce the contents of registers A and B to a value of one by applying a plurality of operations to registers A, B, U and V. During operation, this updating mechanism temporarily stores A+B in the temporary register H, and temporarily stores U+V in the temporary register L.

Abstract: One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is initialized with a value M; and a register V that is initialized with a value 0. The system also includes a temporary register H, and a temporary register L. An updating mechanism is configured to iteratively reduce the contents of registers A and B to a value of one by applying a plurality of operations to registers A, B, U and V. During operation, this updating mechanism temporarily stores A+B in the temporary register H, and temporarily stores U+V in the temporary register L.

Abstract: A system for accurately and efficiently determining the result of an integer multiple-divide operation having the form of (A*B)/C is disclosed. If the values of A, B, and C provide for an easy solution (e.g., A, B, or C are zero, A equals C or B equals C, or A or B equals one), the result is directly computed. Otherwise, if the product of A and B would produce an overflow condition, A and/or B are scaled by a tracked number of bits so that the product of scaled A and B would fit in an integer variable of the current computing system. Then, the product of scaled or unscaled A and B is computed. If C is large compared to the calculated product of A*B, C is scaled to minimize the likelihood of a false zero as a result. Then, the result is scaled if required. Thus, the result of an integer multiple-divide operation having the form of (A*B)/C is efficiently determined according to the system for accurately and efficiently performing an integer multiply-divide operation.

Abstract: Apparatus for determining a remainder of a modulo division of a binary number made up of a string of bits, including a first plurality of substantially similar cells coupled in a linear sequence, the first plurality of cells including at least a first cell and a last cell. Each cell of the first plurality includes a second plurality of binary input terminals, the input terminals of the first cell being coupled to receive a pre-determined input, and a second plurality of binary output terminals, each coupled, except for the output terminals of the last cell, to a respective one of the input terminals of a subsequent cell in the sequence. Each cell of the first plurality further includes a control input terminal, coupled to receive one of the bits in the string corresponding to a position of the cell in the sequence. The remainder is generated at the output terminals of the last cell in the sequence.

Abstract: A calculation circuit for the division of a fixed-point input signal comprising a sequence of digital data values having a width of n bits by an adjustable division factor 2a for the purpose of generating a divided fixed-point output signal, having a signal input (2) for applying the data value sequence of the fixed-point input signal, a first addition circuit (6), which adds the digital data value present at the signal input (2) to a data value buffer—stored in a register (33) to form a digital first summation data value having a width of max (n, a+1) +1 bits, a shift circuit (11) which shifts the first summation data value present by a data bits toward the right, with the result that the max (n, a+1)−a+1 more significant data bits of the first summation data value are output at an output of the shift circuit (11), a logic circuit (16), which, as a function of the sign of the first summation data value, logically ANDs the a less significant data bits of the first summation dat

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A method for calculating greatest common divisors uses an approximate division in its reduction step. The result of this approximate division is then compared to determine if it is valid. If not, then the method applies a correction to the first approximate division to determine corrected values that have a reduced number of bits. If, during this correction step, the result is again not valid, then another method is applied to reduce the number of bits in the values. The approximate division is applied only when the number of significant bits in the two values differ by at least a predetermined number. When the number of bits in the two values differ by less than this number, an alternative GCD algorithm is applied but only to reduce the number of bits in the intermediate values.

Abstract: A new method and apparatus for speeding up cryptographic calculations relies on faster methods for automatically calculating the solutions of certain equations. This includes a faster method for modular division, and a faster method for solving quadratic equations in characteristic 2 fields. The improvement speeds up key exchange, encryption, and digital signatures.

Abstract: The invention provides a method for performing modular division adapted for division in integer fields. Integer modular divisions are used in the computation of Elliptic Curve digital signature generation and verification. The algorithm can be implemented to provide division in integer fields completed in 2(m−1) steps. This method provides a solution to the elliptical curve cryptosystems based on prime integer fields.

Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Abstract: The present invention discloses a method and a system for performing fast division using non linear interpolation. A storage stores x-axis and y-axis coordinates (X0, Y0) of a plurality of non uniform interpolation points, and x-axis and y-axis coordinates (&Dgr;X, &Dgr;Y) representing the differences between two successive points of the plurality of non uniform interpolation points is used. The plurality of non uniform interpolation points is selected such that the x-axis difference (&Dgr;X) is a power n of 2 in the form of (&Dgr;X=2n), with n being an integer. Upon reception of an input operand X, the storage selects and outputs a set of coordinates (X0, &Dgr;Y, n, Y0) associated to the input operand.

Abstract: A higher-radix type divider is provided which is capable of obtaining a quotient at a high speed by performing a scaling on a divisor and by representing a partial remainder in a redundant binary notation.

Abstract: The integers involved in the computation are embedded into a modular system whose index (i.e., its modulus) is an integer M that is bigger than all of these integers involved. In other words, these integers are treated not as belonging to ordinary integers anymore, but as “modular integers” belonging to the modular system indexed by M. Having completed the embedding, CRT provides the bridge which connects the single modular system indexed by M (ZM) with a collection of k modular systems indexed by m1,m2, . . . , mk respectively (Zm1, Zm2, . . . , Zmk), where M factorizes as m1*m2*m3* . . . *mk, and where each mi is slightly smaller than single precision. Then, after numbers are manipulated within modular arithmetic, the answer is reconstructed via the algorithm of CRT, also known as CRA. Finally, the present invention introduces the process of dinking that overcomes the major weakness of implementing division with modular arithmetic.

Abstract: A scheme for carrying out modular calculations which is capable of carrying out modular calculations using redundant binary calculation even when a number of bits of the mantissa (dividend) is larger than a number of bits of the modulus (divisor). In this scheme, the divisor c in the divisor register is left shifted by (i−j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, and the modular reduction a mod c is calculated up to (i−j)-th decimal place using the dividend a and the left shifted divisor c.

Abstract: A data processing apparatus iteratively forms quotient, includes data registers (200) for storing various initial and intermediate quantities, a multiplexer (215) for selecting data from one of two data registers, a barrel rotator (235) and an arithmetic logic unit (230). A first register (200a) stores the numerator, which is left shifted each iteration. A second register (200c) stores the difference formed by the prior trial subtractions. A status register (210) set by the prior arithmetic logic unit (230) result controls the selection made by the multiplexer (215). A barrel rotator (235) rotates the data selected by multiplexer (215). The arithmetic logic unit (230) subtracts the divisor from the rotated quantity this result controls the iterative division process. If the difference is less than zero, then the rotated data is selected and the quotient bit is “0”. Otherwise, the prior difference is selected and the quotient bit is “1”.

Abstract: The present invention relates to arithmetical computing devices, and especially to a division operation in three-dimensional (3D) graphics. A division f(a,b)=a/b is calculated by an integrated division circuit. In order to decrease the chip area and calculation time needed, the bit width of the divider and the dividend is reduced by preprocessing. Firstly, the scaling factor is searched in basis of the divider. Then both the divider and divident are scaled by the single scaling factor. Division is then done with these shrunk bit vectors.

Abstract: In a multiple determination apparatus for determining whether or not a dividend is a multiple of a divisor which is represented by D=.alpha..multidot.2.sup.r where .alpha. is an odd number and r is 0, 1, 2, . . . , a non-zero determination circuit determines whether or not a remainder of a division of the dividend by 2.sup.r is zero. A selector circuit replaces a first number with a quotient of the division. An operational circuit determines whether or not a greatest common measure between .alpha. and the first number coincides with .alpha., when the remainder is zero. Thus, it is determined that the dividend is a multiple of the divisor when the greatest common measure coincides with .alpha..

Abstract: A method for dividing a dividend by a divisor and finding a dividing quotient and a dividing remainder is provided. The dividend has a low byte part and a high byte part and the divisor has a low byte part and a maximum digital value whose most significant bit is "1" and other bits are "0". At first, the low byte part of the dividend is divided by the divisor to obtain a low-byte quotient and a low-byte remainder. Secondly, the high byte part of the dividend is divided by the divisor to obtain a high-byte quotient and a high-byte remainder. Then the high-byte remainder is shift-divided by the divisor to update the low-byte quotient, the high-byte quotient, and the high-byte remainder. Then the high-byte remainder is added to the low-byte remainder to obtain a sum. The sum is divided by the divisor to obtain a quotient and the dividing remainder. Finally, the quotient is added to the low-byte quotient to find the dividing quotient.

Abstract: A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first adder stage are coupled to input ports of the second adder stage. Rounding logic and an accumulator are included in the second stage. By varying the inputs to the first and second stages a variety of complex arithmetic functions suitable for video encoding can be implemented. Examples of the operations include completion of multiply and multiply-and-accumulate operations, averages of two values, averages of four values, and merged difference and absolute value calculation.

Abstract: An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Abstract: A divider circuit provides a divide operation with a multiplier, counter and comparator. The divide operation of two values, x and y, to produce the value of x divided by y, x/y, is provided by sequentially multiplying y in the multiplier with values from the counter until the product of y and a current counter value is determined to cross a unity level, or "1," as determined by a comparator. Therefore, the current value in the counter is approximately equal to 1/y. Then, the determined value of 1/y is multiplied by x to provide x/y. A preferred embodiment of the divider circuit employs a single multiplier, and the divide circuit includes a mux, a multiplier, a counter, a comparator, and an optional buffer. The mux receives two values x and y and a selection signal provided by the comparator. The counter is loaded with an initial value, which may be a zero dataword.

Abstract: A method and apparatus to divide a signed integer by a constant power of two using conditionally-executed instructions to choose between a first result in the event that the dividend is a negative signed integer and a second result in the event that the dividend is a positive signed integer, wherein values associated with the first result and the second result are generated simultaneously.

Abstract: A clamping divider has a bit shifter, a multiple accumulator (MAC), and an output circuit. When executing a division with the use of a clamp value of 2.sup.m, the bit shifter shifts one of the divisor and dividend of the division, and the MAC subtracts the shifted one from the other to determine, before calculating a quotient of the division, whether or not a result of the division must be clamped.

Abstract: A circuit calculates the exact biased resultant exponent before calculating the resultant mantissa of a division operation. The circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder receives the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias. The conditional-sum adder receives the sum and carry resultants of the carry-save adder, outputting {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The comparator controls the multiplexer to respectively select as the resultant exponent either er0 or er1 when the fraction of the dividend is less than or greater than or equal to the fraction of the divisor. A circuit for determining the resultant exponent of a squareroot operation includes a conditional-sum adder, a multiplexer and a selection logic circuit.