Abstract: A data processing apparatus uses numeric processing. A corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism to a suitable approximate division method, a numeric processing mechanism performs the integer division operation efficiently. An approximate division method that uses rapid operations for fast integer division, and thus has a small possible range of errors, is used to enable the correction method to be completed rapidly.

Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q?1q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj?1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

Abstract: The invention discloses a method for adjusting a reference frequency. First, a training signal is received based on the reference frequency. Then, a target region of the training signal is divided by an original training sequence so that a quotient polynomial is generated. Afterward, the quotient polynomial is divided by a predetermined polynomial so that a remainder polynomial is generated. Finally, the reference frequency is adjusted based on the remainder polynomial.

Abstract: A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the same power supply to reduce loss of external sampling.

Abstract: Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each qualifying visitor is thereafter associated with a qualification profile and a corresponding value. In another aspect of the invention, visitors arriving as a result of an advertisement on a remote web-site are tracked. The web-site proprietor is consequently able to determine a return on advertising investment based on the value of visitors brought to the site by the tracked advertisement.

Abstract: A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a given estimate to the number. The current estimate is updated based on this comparison and the inverse function of the current estimate is stored. The next estimate is an incremental change from the previous estimate and there is a corresponding incremental change in the inverse function from the current estimate to the next estimate. Rather than calculating the whole inverse function, which would typically require a multiplier, only the incremental change in the inverse function is provided simply. The incremental change in the inverse function is then added to the inverse function of the current estimate and compared to the number for determining the utility of the next estimate.

Abstract: A method executed in a computing device for dividing by the integer number 48, the method includes receiving a number, and using the number in a combination of four additions and four bit-level shifts to produce a quotient representing the number divided by the integer number 48.

Abstract: The present invention relates to a divider for dividing a dividend by a divisor. The divider includes a subtractor for subtracting the divisor from the dividend to produce a result, storage space with a preliminary answer, and a processor for revising the dividend and preliminary answer based on the result. Each interation the divider is adapted to reiterate the subtraction and revision multiple times, based on a revised dividend and revised preliminary answer.

Abstract: A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one or more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: Described herein is a method that includes storing partial quotients of a continued fraction in a first set of counters, initializing a second sets of counters with counter values, decrementing a target counter in the second set of counters to obtain a decremented counter value, and outputting a value that corresponds to a partial quotient in a first counter in the first set of counters. The value is based on the decremented counter value.

Abstract: Embodiments disclosed herein provide sparse adder circuits comprising Ling type propagate and generate circuits and sparse carry circuits to efficiently add first and second operands to one another.

Abstract: The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one DFT module is configured to perform DFTs of a first predetermined number and of a vector size corresponding to a second predetermined number, to multiply by twiddle factors, and to perform DFTs of said second predetermined number and of a vector size corresponding to said first predetermined number. At least two of the at least one DFT module are combined to obtain the predetermined vector size. Thereby, an implementation of non 2x-radix Fourier transformation can be achieved with moderate hardware complexity.

Abstract: A division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale are provided. The shift-add type of division unit includes a plurality of shift units for shifting an input signal by a different number of bits, an adder for totaling the shifted result in the shift units and producing an addition result, and a most-significant-bit (MSB) shift unit for extracting the MSB (contains a plurality of bits) of the addition result to serve as a division result.

Abstract: Provided are methods, computer programs and data processing apparatus using numeric processing. Firstly, a corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism to a suitable approximate division method, a numeric processor or software-implemented numeric processing mechanism implementing the invention can perform the integer division operation efficiently. Secondly, an approximate division method which uses only rapid operations for fast integer division, and which has only a small possible range of errors, is used to enable the correction method to be completed rapidly.

Abstract: A method of automatic calculation of several integer divisions by a same integer divider, of several successive integer dividends, separated from one another by a constant iteration step, smaller than or equal to the divider, including selecting, from a table of increments, according to an iteration index, a 0 or a 1 to be added to the operation result of the preceding iteration, the number of 0s in the table of increments being equal to the divider minus 1.

Abstract: A Sweeney Robertson Tocher (SRT) divider and a square root extractor of floating point double-precision bit width, including a selector of single-precision and double-precision, a carry propagation adder (CPA) for conducting carry propagation of a partial remainder, a quotient digit selector circuit for making selection on a quotient digit, and a selector of a divisor or a partial square root extractor circuit, in a lower side thereof. A selector for selecting the propagation of carry between a carry save adder (CSA) in the upper side and the lower side thereof is provided, and a selector of a starting position within a quotient production circuit is provided, thereby enabling the execution of two (2) calculations, such as, division or square root extraction of the floating point single-precision, at the same time, but without increasing the bit width of a computing unit.

Abstract: Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions. A table of mantissa and exponent values is created for a sufficient range of values for 1/a. During quantization, the mantissa and exponent values are found in the table 1/a for associated with a given quantization division operation given by b/a which is found according to the formula b/a=(b×A)>>n. Aspects are described for application to processors that do not support non-uniform shift operations, and for reducing the necessary bit-width of the operations to increase efficiency. The quantization method may be applied to protocols such as MPEG-2 and other similar formats.

Abstract: A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of representing the integral number as a binary vector; initializing an intermediate element to the group identity element; selecting successive bits, beginning with a left most bit, of the vector. For each of the selected bits; performing the group operation on the intermediate element to derive a new intermediate element; replacing the intermediate element with the new intermediate element; performing the group operation on the intermediate element and an element, selected from the group consisting of: the group element if the selected bit is a one; and an inverse element of the group element if the selected bit is a zero; replacing the intermediate element with the new intermediate element.

Abstract: The present invention provides an apparatus and method for performing an operation on an operand or operands in order to generate a result, in which the operation is implemented by iterative execution of a recurrence equation. In each iteration, execution of the recurrence equation causes a predetermined number of bits of the result and a residual to be generated, the residual generated in a previous iteration being used as an input for the current iteration, and in the first iteration the residual comprising the operand.

Abstract: A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a plurality of possible composite divisors (DEG). Each composite divisor is indicative of a minimum time interval by which adjacent pulses of the baud clock are to be separated, and further indicates that at least one pair of adjacent pulses within each symbol interval of the baud clock are to be separated by an extended time interval which is longer than the minimum time interval.

Abstract: One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is initialized with a value M; and a register V that is initialized with a value 0. The system also includes a temporary register H, and a temporary register L. An updating mechanism is configured to iteratively reduce the contents of registers A and B to a value of one by applying a plurality of operations to registers A, B, U and V. During operation, this updating mechanism temporarily stores A+B in the temporary register H, and temporarily stores U+V in the temporary register L.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: Disclosed is a division unit for use in a three-dimensional (3D) computer graphics system. The division unit can reduce an area and power consumption thereof by removing more significant bits from homogeneous texture addresses u and v by the number of leading zeros included in a homogeneous texture address w and approximately carrying out a division operation for decreased data in texture mapping of the 3D computer graphics system. Therefore, the performance of real-time texture mapping is enhanced in a portable device operating at low power and hence 3D computer graphics can be realistically implemented.

Abstract: A method and system for performing integer divisions using subtraction-based division processes in a hardware divide processor primarily dedicated for floating-point division processes. In particular, the method and system involve calculating a quotient of a dividend and a divisor, the dividend and divisor being binary coded integer values, by normalizing the divisor and the dividend, determining a number of binary digits (nV) needed to represent the divisor and a number of binary digits (nD) needed to represent the dividend, determining a number of effective binary digits (nQ) needed to represent the quotient, determining a start bit position to start a subtraction-based divide process, and performing the subtraction-based divide process only for bit positions beginning at the start bit position and at a least significant bit position. In preferred embodiments, the subtraction-based divide process is an SRT (Sweeney, Robinson, Tocher) Divide process.

Abstract: In a digital processor performing division, quotient accumulation apparatus is formed of a set of muxes and a single carry save adder. Partial quotients are accumulated in carry-save form with proper sign extension. Delay of partial quotient bit fragments from one iteration to a following iteration enables the apparatus to limit use to one carry save adder. By enlarging minimal logic, the quotient accumulation apparatus operates at a rate fast enough to support the rate of fast dividers.

Abstract: Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.

Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication.

Abstract: Apparatus and method for performing IEEE-rounded floating-point division utilizing Goldschmidt's algorithm. The use of Newton's method in computing quotients requires two multiplication operations, which must be performed sequentially, and therefore incurs waiting delays and decreases throughput. Goldschmidt's algorithm uses two multiplication operations which are independent and therefore may be performed simultaneously via pipelining. Unfortunately, current error estimates for Goldschmidt's algorithm are imprecise, requiring high-precision multiplication operations for stability, thereby reducing the advantages of the pipelining. A new error analysis provides improved methods for estimating the error in the Goldschmidt algorithm iterations, resulting in reductions in the hardware, improved pipeline organization, reducing the number and length of clock cycles, reducing latency, and increasing throughput.

Abstract: A method for an extended precision integer divide algorithm. The method of one embodiment comprises separating a first L bits wide integer dividend into two equal width portions, wherein a first integer format portion comprises lower M bits of the first integer dividend and a second integer format portion comprises upper M bits of the first integer dividend, wherein M is equal to ½ L. The first integer format portion is converted into a first floating point format portion. An N bits wide integer divisor is converted from an integer format into a floating point format divisor. The first floating point format portion is divided by the floating point format divisor to obtain a first floating point format quotient. The first floating point format quotient is converted into a first integer format quotient. The second integer format portion is converted into a second floating point format portion.

Abstract: Methods and apparatus for performing a long division within a processor system are disclosed. The methods and apparatus include a memory and instructions stored in the memory to be executed by the processor system. When executed, the instructions cause the processor system to calculate a first value associated with an absolute value of a dividend and to multiply the first value by a second value to generate a third value. The second value is an absolute value of a fourth value associated with a reciprocal of a divisor. The processor system calculates a quotient based on the third value.

Abstract: An SRT division unit for performing a novel SRT division algorithm is presented. The novel SRT division algorithm comprises a method for performing SRT division using a radix r. As one skilled in the art will appreciate, the radix r dictates the number of quotient-bits k generated during a single iteration. The relationship between radix r and the number of quotient-bits k generated in a single iteration is r=2k. The number of iterations needed to determine all quotient-digits is N, such that N=54/k for a 64 bit floating point value. In accordance with one embodiment of the present invention, the SRT division unit generates a scaling factor M, which comprises scaling sub-factors M1 and M2 according to the relationship M=r*M1+M2. Next, the division unit generates a scaled divisor Y by multiplying a divisor DR by scaling factor M, such that said scaled divisor Y=DR*M=r(DR*M1)+DR*M2.

Abstract: The present invention provides an apparatus and method for performing an operation on an operand or operands in order to generate a result, in which the operation is implemented by iterative execution of a recurrence equation. In each iteration, execution of the recurrence equation causes a predetermined number of bits of the result and a residual to be generated, the residual generated in a previous iteration being used as an input for the current iteration, and in the first iteration the residual comprising the operand.

Abstract: An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.

Abstract: A fractional arithmetic unit for performing fractional arithmetic operations of different numerators and a common denominator with different precisions as required, the fractional arithmetic unit, including a reciprocal number arithmetic logic unit; and a multiply arithmetic circuit configured to multiply a numerator and a reciprocal number of the denominator as obtained by the reciprocal number arithmetic logic unit. A precision of a calculation performed by the reciprocal number arithmetic logic unit is changed in accordance with a precision as required for each of the fractional arithmetic operations. The multiply arithmetic circuit outputs a result of multiplication as a result of the fractional arithmetic operation, and the results of the fractional arithmetic operations are output with different precisions.

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

Abstract: One embodiment of the present invention provides a system for performing a division operation between arithmetic intervals within a computer system. The system operates by receiving interval operands, including a first interval and a second interval, wherein the first interval is to be divided by the second interval to produce a resulting interval. Next, the system uses the operand values to create a mask. The system uses this mask to perform a multi-way branch, so that an execution flow of a program performing the division operation is directed to code that is tailored to compute the resulting interval for specific relationships between the interval operands and zero. In one embodiment of the present invention, creating the mask additionally involves, determining whether the first and/or second intervals are empty, and modifying the mask so that the multi-way branch directs the execution flow of the program to the appropriate code for this case.

Abstract: A method of dividing, in a micro computer unit (MCU), a first binary number (N), having a first number of significant bits, by a second binary number (D), having a second number of significant bits, produces an integer result (Y). The method includes: determining the difference (K) between the first and second numbers of significant bits; aligning the most significant bits (MSBs) of N and D by shifting the bits of D, by K bit positions, such that its MSB occupies the same relative bit position as the MSB of N; repeating K times: multiplying Y by 2; dividing D by 2; and, if N is greater than or equal to D: increasing Y by 1; setting N equal to N−D.

Abstract: In a method for permuting and dividing 16 pieces of k-bit data held in 4 k-bit long registers T0. T1, T2 and T3, k being an integer, the data of each register Ti is ANDed with a desired one of mask data (00ffff00), (ff0000ff), (0000ffff) and (ffff0000), and such ANDs are ORed to obtain desired permuted data.

Abstract: Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions. A table of mantissa and exponent values is created for a sufficient range of values for 1/a. During quantization, the mantissa and exponent values are found in the table 1/a for associated with a given quantization division operation given by b/a which is found according to the formula b/a=(b×A)>>n. Aspects are described for application to processors that do not support non-uniform shift operations, and for reducing the necessary bit-width of the operations to increase efficiency. The quantization method may be applied to protocols such as MPEG-2 and other similar formats.

Abstract: A method of automatic calculation of several integer divisions by a same integer divider, of several successive integer dividends, separated from one another by a constant iteration step, smaller than or equal to the divider, including selecting, from a table of increments, according to an iteration index, a 0 or a 1 to be added to the operation result of the preceding iteration, the number of 0s in the table of increments being equal to the divider minus 1.

Abstract: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

Abstract: A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B with a remainder R in parallel in two-input comparators and a three-input comparator and performing radix 4 division by finding a quotient 2 bits at a time. At this time, using a three-input comparator 313 in the comparison of 3B=(B+2B)≦R to realize comparison without the addition (B+2B), also, finding a new remainder Re in a three-input adder/subtractor for the simultaneous complex addition/subtraction R−(x+y) by a single ripple carry.

Abstract: The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract: Devices and methods are provided for estimating a high-precision quotient using a smaller-than-conventional lookup table. The devices include a numerator register feeding a numerator value (as a succession of bits or words) into a forward signal path. The forward path includes a partial quotient generator, an accumulator, and a latch. The devices further include a feedback signal path emerging from the latch output, undergoing division by bit-shifting, and terminating as an input to the accumulator. A multiple divide implementation for use in a particular servo control system is also presented.