Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g.

Abstract: An amplifier may include multiple transistors with two transistors having their gates tied together via a common connection. The amplifier may utilize a local common mode feedback resistor as part of the amplifier. The local common mode feedback resistor may be coupled between the common connection and respective terminals of two transistors of multiple transistors. The local common mode feedback resistor may include a group of resistors coupled in series. The local common mode feedback resistor may also include a metal oxide semiconductor (MOS) resistor coupled in parallel with one or more of the first group of resistors. In the local common mode feedback, the first MOS resistor provides different levels of resistance to different process corners to reduce overshoot when the amplifier is enabled.

Abstract: An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

Abstract: Disclosed are various embodiments of memristive devices comprising a number of nodes. Memristive fibers are used to form conductive and memristive paths in the devices. Each memristive fiber may couple one or more nodes to one or more other nodes. In one case, a memristive device includes a first node, a second node, and a memristive fiber. The memristive fiber includes a conductive core and a memristive shell surrounding at least a portion of the conductive core along at least a portion of the memristive fiber. The memristive fiber couples the first node to the second node through a portion of the memristive shell and at least a portion of the conductive core.

Abstract: An optical phased array comprising a row-column driving mechanism is disclosed that reduces the number of digital to analog converter (DAC) channels to the number of rows N and the total number of interface pin counts down to the number of columns plus the number of rows M+N. Disclosed herein are systems and architecture for thermal waveguide-based phase shifters which improve thermal efficiency by having multi-pass waveguides arranged proximate a heating element in a serpentine fashion, which enables an increase in phase shift without increasing the length or the power consumption of the heating element by increasing the total length of waveguide being heated by a singular heating element.

Abstract: A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2? radians, the photonic processor performs addition modulo 2?. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g.

Abstract: A semiconductor device including a multiplier circuit is provided. A first cell, a second cell, and a first circuit are included. The first cell includes a first transistor. The second cell includes a second transistor. The first circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a first switch.

Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.

Abstract: To reduce the reliance on software for complex computations used in machine sensory perception, a sensory perception accelerator may include a neural network accelerator a linear algebra accelerator. The neural network accelerator may include systolic arrays to perform neural network computation circuits concurrently on image data and audio data. The linear algebra accelerator may include matrix computation circuits operable to perform matrix operations on image data and motion data.

Abstract: The analog multiplier includes a first signal input module, and a second signal input module or a third signal input module. The first signal input module is configured to output a frequency modulation signal. The second signal input module includes a first energy storage unit, a first switch unit, and a second switch unit. The first switch unit and the second switch unit are alternately turned on or turned off based on a frequency of the frequency modulation signal. The third signal input module includes a second energy storage unit, two third switch units, and two fourth switch units. The third switch unit and the fourth switch unit are alternately turned on or turned off based on the frequency of the frequency modulation signal.

Abstract: A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.

Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: A signal generator includes a data source, a power source, and a modulator. The modulator is configured to modulate a power signal from the power source with a data signal from the data source to generate a modulated power signal. Data values of the data signal correspond to variations in a voltage level of the modulated power signal over time. The modulator is coupled to output the modulated data signal to a one-wire interface.

Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.

Abstract: A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

Abstract: Provided is a neuromorphic arithmetic device. The neuromorphic arithmetic device may include a synapse circuit, a metal line having an inherent capacitance component, an oscillator, a comparator, and a capacitance calibrator. The synapse circuit may be configured to perform a multiplication operation on a PWM signal and a weight to generate a current. The metal line may include a metal line capacitor in which a charge of the current is stored. The oscillator generates a plurality of pulses on the basis of the charge stored in the metal line capacitor. The comparator may compare a frequency of the plurality of pulses and a target frequency, and may generate a control signal on the basis of a result of the comparison. The capacitance calibrator may adjust a capacitance value of the metal line capacitor on the basis of the control signal.

Abstract: A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix. An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Abstract: An apparatus and methods for generating multi-level output signals for use by an optical modulator are provided. The apparatus comprises a plurality of input signal lines each configured to receive a binary input signal, an output signal line and a plurality of amplifier stages. The amplifier stages are each connected between one of the input signal lines and the output signal line so as to each produce an output voltage on the output signal line of either a first level or a second level. The level of the output voltage is based on the binary signal at the respective input signal line, and the output voltages of the respective plurality of amplifier stages collectively produce a summed analog output voltage on the output signal line at two or more different levels each configured to drive an optical modulator.

Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables;

Abstract: A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers.

Abstract: Methods implementable in a computer system for simulating the transmission of signals are disclosed. The disclosed techniques simulate the effect of the transmitter as well as the channel on a positive and negative pulse, which assures that asymmetry in the transmitter is captured. The resulting positive and negative pulse responses are then used to generate two separate PDFs: one indicative of received logic ‘1’s and another indicative of received logic ‘0’s at a point in time. Generating a plurality of such PDFs at different times allows the reliability of data reception to be assessed, and appropriate sensing margins to be set at a receiver, without the need to simulate the transmission of a very long random stream of data bits.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a first input voltage. The current passing through the voltage controlled resistance circuit is based upon a second input voltage. The first transistor and the second transistor form a current mirror to mirror the current passing through the voltage controlled resistance circuit to provide a power supply control current to a wideband code division multiple access radio frequency power amplifier.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a difference between a supply voltage and a first input voltage and a constant current supply. The current passing through the voltage controlled resistance circuit is based upon a difference between the voltage supply and a second input voltage. The first transistor may be configured to mirror the current passing through the voltage controlled resistance circuit.

Abstract: A current-mode analog computational circuit can be controlled to produce multiplying, squaring, divider and inverse functions and corresponding current outputs. The current-mode analog computational circuit is based on an implementation using MOSFETs operating in a sub-threshold region as can provide relatively ultra-low power dissipation. Furthermore, the current-mode analog computational circuit can be operated from a ±0.75 V DC supply. Tanner simulation results conducted using a 0.35-?m TSMC CMOS process confirmed the functionality of the multiplying, squaring, divider and inverse functions of the circuit. The current-mode analog computational circuit advantageously can have a total power consumption of 2.3 ?W, a total harmonic distortion is 1.1%, a maximum linearity error of 0.3% and a bandwidth of 2.3 MHz.

Abstract: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

Abstract: A windowed optical calculation architecture and process that efficiently performs high speed multi-element multiply and accumulates on a digital data stream. A data point from a digital data stream is impressed onto an optical source to create an optical value. The optical value is split into a number of branches equaling the number of elements used in the calculation. In each branch, the optical value is modulated to reflect the coefficients in the calculation. Then, depending upon the branch, the optical value is delayed depending on its position in the calculation, with optical values at the beginning of the calculation being delayed longer than optical values at the end of the calculation. The outputs from the branches are coupled together to perform an optical sum, and passed to detection/analog-digital conversion circuitry to convert the optical result to a digital result.

Abstract: An analog optical adder system that achieves high precision results. The system uses an analog optical carry function to provide a result having a precision higher than the precision of the individual elements of the system. The optical carry function is created by optical carry determinators that are configured to add an optical carry, if any, to an optical signal associated with a next adjacent byte of the digital signals being added. The use of optical carry enables greater overall addition precision.

Abstract: An optical processor that incorporates optical computing in a monolithic, i.e. single unit, structure that can take the place of, or operate as a coprocessor with, traditional processor devices such as vector processors, digital signal processors, RISCs, CISCs, ASICs, FPGAs among others. The optical processor incorporates photonic devices that perform algorithmic functions on optical signals. The optical processor takes one or more incoming digital signals, converts the digital signal into an optical signal, performs the algorithmic function(s) in the optical domain, and then converts the result back into a digital signal, all in a monolithic or single unit structure.

Abstract: A mix mode wide range multiplier and method are provided for multiplying a first signal by a second signal to generate an output signal. A reference signal is generated according to a first gain and a reference value, the output signal is generated according to a second gain and the first signal, a target value is generated according to the second signal, the first gain is adjusted to make the reference signal equal to the target value, and the second gain is adjusted to maintain a ratio of the second gain to the first gain.

Abstract: A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Abstract: An RF squarer circuit comprises a first RF multiplier and a first variable gain transimpedance amplifier (TIA). The first RF multiplier receives an RF input signal RFIN and provides a first output current. The first TIA receives the first output current as an input. The first TIA provides an output voltage VOUT.

Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number.

Abstract: An analogue multiplier circuit has an input coefficient voltage dependent adjustment of its frequency response. The multiplier contains a multiplier cell (MC) with an RF input (Vin+, Vin?) and a coefficient signal input (Vcoeff+, Vcoeff?), one or more capacitors (Cp1, Cp2) as peaking capacitors, which one contact connects to the multiplier cell (MC) and the other to a variable resistance (Mp1, Mp2), i.e. a MOS transistor, and a control circuit (CT) for controlling the variable resistance (Mp1, Mp2). The control circuit (CT) is connected to the coefficient signal input (Vcoeff+, Vcoeff?) of the multiplier. In the case of a four-quadrant multiplier a rectifier (RT) is connected between the coefficient input (Vcoeff+, Vcoeff?) of the multiplier and the control circuit (CT).

Abstract: A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.

Abstract: Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its respective second input signals. Dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals, and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals. The dummy multiplier modules reduce the overall voltage requirements of the circuit, thereby providing for low-voltage operation.

Abstract: The Impedance Multiplication-Division Operators are made up of non-reciprocal network elements, each of which produces an input impedance that is related to the multiplication-division of its load impedances. The Impedance Multiplication-Division Operator can be implemented in a number of embodiments, such as the Positive Impedance Multiplication-Division Operator which produces a new non-reciprocal (n+1)-port, n?4, network element which has the distinguishing property that if three 2-terminal impedances, Z2(s), Z3(s), and Z4(s) are connected at ports 2, 3 and 4 of a 1PIMDOR2,43, the input impedance offered by this loaded 4-port at port 1 is Z(1)(s)=Z2?1(s)Z3(s)Z4?1(s).

Abstract: A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q11, resistors R11 and R12 form a common-emitter circuit. One signal of differential signal v1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q12. The output current of the emitter follower is input through resistor R13 into the current mirror circuit composed of transistors Q13 and Q14. Output current I5 of said current mirror circuit is input to the transistor pair of transistor Q19 and npn transistor Q20. By selecting an appropriate gain for the common-emitter circuit, currents I5 and I6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.

Abstract: The Impedance Product Operator can be implemented in a number of embodiments to produce a new non-reciprocal (n+1)-port network element with the distinguishing property that if n 2-termial impedances, Z2, . . . Zn+1 are connected at ports 2, . . . , n+1 of an Impedance Product Operator, the input impedance offered by this loaded multi-port at port 1 is Z ( 1 ) = ? k = 2 n + 1 ? ? Z k . As a single network element, the Impedance Product Operator offers a direct yet general mechanism for multiplication of 2-terminal impedance functions. This network element allows simpler and more direct synthesis of driving point impedance functions.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.

Abstract: A linear multiplier circuit comprises a first, a second, a third and a fourth transistor, each having a drain, a source, a gate and substantially an identity threshold voltage. Each of these four transistors operates with a fixed drain-to-source voltage applied between the drain and source, a gate-to-source voltage applied between the gate and source. The sources of the first and second transistors, and the drains of the third and fourth transistors are coupled to form the output terminal.

Abstract: A multiplier arrangement (MUXER) is adapted to generate from analog phase information and from high-frequency local oscillator signals, components of a high-frequency phase vector (PV), and to synthesise said high-frequency phase vector (PV) from said components within a summing means is further adapted to provide said high-frequency phase vector (PV) as a vector which is making an excursion alongside the contours of a square within the complex plane during a first category of predetermined transitions of a phase signal (?) on which said analog phase information is dependent. A signal modulator including such a multiplier arrangement as well as a transmitter are described as well.

Abstract: A method of image sampling and an apparatus thereof. The apparatus comprises: an adder; a first register, the output of which is fed back to the adder; a first multiplexer, which outputs a ratio or a weighted parameter; a multiplier, which receives an input image value and the output of the first multiplexer; an adder/subtracter, which receives the output of the multiplier; a second multiplexer, which receives the output of the adder/subtracter and the multiplier; and a second register, which receives the output of the second multiplexer. By the method of approximation and recursion, the input image data can be processed in real time to produce the output image data.

Abstract: A sum of product circuit (20) which adds up two input voltages, each of which is multiplied by the prescribed coefficients. The sum of product circuit (20) has a &ngr; MOS transistor (50), a first and a second capacitance (C1, C2), and an output terminal (86). The &ngr; MOS transistor (50) includes a drain (70), source (72), and a floating gate (74). The first and a second capacitance (C1, C2) connects each of two input voltages to the floating gate (74) by capacity coupling. The output terminal (86) outputs a voltage realized between a resister element (R0) and the &ngr; MOS transistor (50). A constant voltage is applied between the drain (70) and the source (72) through the resister element (R0).

Abstract: The method serves to add at least two values by means of a circuit. Both input values and output values are represented in differential form, either as a pair of voltages or as a pair of currents. The circuit consists of four transistors; it has a pair of current inputs for one of the input values, a pair of voltage inputs for the other input value, and a pair of current outputs for the output value. The voltage between the two voltage inputs corresponds to the first input value; the quotient of the currents through the two current inputs corresponds to the exponential of the other input value; and the quotient of the currents through the two current outputs corresponds to the exponential of the sum of the two input values. Values represented by voltages are easily transformed into current representation, and vice versa. The method is suitable for a variety of applications and the circuit can be cascaded both with copies of itself and with other circuits.

Abstract: A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q11, resistors R11 and R12 form a common-emitter circuit. One signal of differential signal v1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q12. The output current of the emitter follower is input through resistor R13 into the current mirror circuit composed of transistors Q13 and Q14. Output current I5 of said current mirror circuit is input to the transistor pair of transistor Q19 and npn transistor Q20. By selecting an appropriate gain for the common-emitter circuit, currents I5 and I6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.

Abstract: An analog multiplication circuit for outputting an output multiplied by an input electric current with a predetermined number can be provided with a simple structure. The circuit comprises a gate voltage control portion 1 having a first operation amplifier 13 and a first MOSFET 14 operated in a MOS Ohmic region and at least one operation portion 3 having the second operation amplifier 32, a first resistance 31, an electric current mirror circuit 34 and a second MOSFET 33 operated in a MOS Ohmic region, wherein a first input electric current I1 is supplied to the first MOSFET 14 and a second input electric current I2 is supplied to the first resistance 31 so as to output an output electric current IOUT by multiplying I1 with I2 from an output-side transistor 36 of the electric mirror circuit 34.

Abstract: The invention relates to methods and apparatus that selectively multiply an analog signal by zero (0), one (1), and negative one (−1) at high speeds. In one embodiment, the analog signal corresponds to an integration result of a transition from a first data bit to a second data bit in a serial data bitstream. Advantageously, the multiplier circuit is well adapted to relatively high-frequency operation by providing a balanced load to a driver circuit such that the selected multipliers of the multiplier circuit can switch in a substantially symmetrical manner. In one embodiment, the driver circuit includes a data transition identifier circuit.