Abstract: A method and a device for controlling data transmission between IDE apparatuses allow an IDE controller of an IDE control device to send read control signal to an IDE apparatus via a set of IDE interfaces and a signal control transmission line and then to send write control signal to another IDE apparatus via another set of IDE interfaces and another signal control transmission line. Thus, the output data from the IDE apparatus through the data transmission line can be accelerated the transmission speed thereof between IDE apparatuses so as to save the time for transmitting data.

Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.

Abstract: A combined ATA and SATA controller is provided that comprises a control unit for controlling data transfer to and/or from an ATA compliant parallel storage device and a control unit for controlling data transfer to and/or from an SATA compliant serial storage device. The controller can concurrently perform the data transfer to and/or from the parallel and serial devices. By reusing a significant amount of controller hardware, the combined controller can be realized in a cost effective manner.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface so that multiple hard drives may be interfaced using the common pins of the integrated circuit.

Abstract: A system and method for managing a Fibre Channel adapter is disclosed. When a close request is received by the Fibre Channel adapter, the adapter is set to a quasi-open state. In a quasi-open state, the adapter keeps the link to the Fibre Channel network open, releases extended resources, and maintains minimal resources in order to keep the link open. When a request is received by the adapter while in a quasi-open state, the request is rejected thereby preventing other devices from logging into the quasi-opened device and informing other devices that the quasi-opened device is not currently communicating across the Fibre Channel network. An information handling system and a computer program product for implementing the Fibre Channel adapter quasi-open state are further disclosed.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

Abstract: A cabinet having a plurality of rack mountable chassis. One portion of such chassis has directors and electrically interconnected memory and another portion of such chassis has a plurality of disk drives. The plurality of chassis are electrically interconnected to provide a data storage system interface. A first one of such chassis includes a memory and a plurality of directors. A first plurality of the directors is adapted for coupling to a host computer/server. A second one of such chassis has a plurality of disk drives. Also includes are first electrical conductors for connecting the disk drives in the second chassis to a second plurality of directors in the first one of the chassis. A third one of such chassis includes a memory and a plurality of directors. The first plurality of the directors in the third one of the chassis are adapted for coupling to the host computer/server. A fourth one of such chassis has a plurality of disk drives.

Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

Abstract: A method of transferring at least two data streams in a medical device is provided. First data stream data is collected into a first intermediate register. Additional data stream data is collected into an additional intermediate register. First intermediate register contents are stored in at least one first output register. Systems and devices for using the method are also provided.

Abstract: An information processing system comprising a computer connected to an amplifier in an audio visual (AV) system through an IEEE 1394 serial bus connection. The amplifier has various different types of external terminals for connecting to other AV devices. The computer requests, receives and displays name information on the external terminals from the amplifier. A user of the system can select various AV devices from the name information displayed on the computer. The computer then commands the amplifier to switch to the selected AV device.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: Secondary pointer for the control of computers, which comprises a transceiver coupled with a decoder/encoder, at least one memory or memory address, an embedded controller, and hand-operable actuation means, such as keys or buttons, for placing the device in the receiving or transmitting mode. The pointer may also include a selector which attributes an identification to each command or program in the receiving mode, and uses the identification to retrieve the program which the operator desires when the device is placed in the transmitting mode.

Abstract: Disclosed are various systems and methods for printing documents. In one embodiment, a printing system is provided that comprises a host and a local printer coupled thereto, the local printer having a portable device communications port with which to establish a communications link a portable device. The local printer includes means for relaying a non-rendered document received via the portable device communications port to the host for rendering. The host includes means in the host for orchestrating a rendering of the non-rendered document into a rendered document with a printer format compatible with the local printer, the non-rendered document being rendered using one of a number of applications in the host, and, means in the host for transmitting a rendered document to the local printer to be printed.

Abstract: A real-time data acquisition and storage network for real-time acquisition and storage of analog and digital data from one or multiple network-connected data sources to one or multiple network-connected storage devices during a data recording session, and precise reconstruction of the acquired data from one or multiple of the network-connected storage devices during a playback session. The data source are connected to the network through one or multiple real-time data acquisition network (“R-T DAN”) modules which form one or multiple network-connected data acquisition nodes on the network. Each storage device forms a network-connected storage node on the network so that data acquired at any data acquisition node may be applied to the network and stored at any storage node during a data recording session. The stored data may be retrieved from the storage nodes through the network and routed to the data acquisition nodes for reconstruction of the data during a playback session.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the I/O subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: An apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system. The apparatus includes a data buffer and a control unit. The data buffer includes a first plurality of storage locations each corresponding to one of a plurality of tag values. The data buffer may receive a plurality of data packets associated with the graphics transactions. The data buffer may also store the data packets in the storage locations according to tag values. The control unit includes a storage unit having a second plurality of locations. Each of the locations in the storage unit corresponds to one of the tag values and may provide an indication of whether a given data packet has been stored in the data buffer. The control unit may further determine an order in which the plurality of data packets is read from the data buffer.

Abstract: Systems, methods, and computer products that improve the performance of computer-implemented I/O operations issued by complex applications that are directed to high-performance disk drives, and that may operate in conjunction with the product marketed under the trademark IBM S/390®. Such high-performance disk drives may include the IBM Shark® that supports the parallel access volumes feature.

Abstract: A display apparatus for displaying images based on signals received from a host. The apparatus includes a determining means for determining an interface type of the host, a plurality of storage means each storing specification information relating to display for one of interface types to be connected, and an output means for outputting, from one of the storage means to the host, the specification information corresponding to the interface type determined by the determining means.

Abstract: A dynamic address switching system for use in a data processing system with redundant data storage facilities. A validation routine or module assures that dynamic switching can occur between logical devices. A swapping routine exchanges information in unit control blocks for logical devices in the redundant system thereby to enable I/O requests from a host to be redirected over another channel to the other data storage facility.

Abstract: Data is moved between zones of a central processing complex via a data mover located within the central processing complex. The data mover moves the data without sending the data over a channel interface and without employing processor instructions to perform the move. Instead, the data mover employs fetch and store state machines and line buffers to move the data.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A system and method to facilitate communication between an associated bus, such as employs a standard bus protocol, and a connector to which a removable SFF device can be attached. A desired operating mode is selected based on the device attached at the connector, such as either to pass the protocol between the bus and device generally unchanged or to implement suitable protocol conversion for such communication. Thus, by configuring the SFF device to appear as device currently supported by the bus, the SFF device can operate at the connector with native operating system support.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Abstract: A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage un

Abstract: A computer comprises a medium drive configured to reproduce data recorded in a video recording medium and an audio recording medium. When a reproduction switch is turned on if the computer is not powered, it is determined whether the video recording medium or the audio recording medium is loaded. If the video recording medium is loaded, the operating system is activated and the reproduction application is also activated.

Abstract: According to the present invention, data for all or a part of the MFP devices connected to a network are obtained, and are rearranged as a list or are limited based on a variety of data obtained for each device, such as equipment data, apparatus data, network setup data, job states and employment statuses. As a result, data desired by a user can be provided in real time.

Abstract: A multiplexor is designed to receive data from a plurality of data sources. As the multiplexor receives data from data sources, its programmable logic device codes each stream of data with a header and a footer and a data stream segment between them having a prescribed number of characters. A message from any particular data source may be coded into a plurality of separate data stream segments. The multiplexor sequences to the next data source when a data stream having the prescribed number of bytes has been captured and returns to that data source only after data streams of the same prescribed number of characters have been captured from the other data sources in a sequential manner. Data so coded is forwarded to a storage device that may store the data on any suitable storage medium for later retrieval.

Abstract: The parallel electronic architecture comprises a plurality of processor units connected to a communication bus and each adapted to execute one or more predefined tasks automatically. Each processor unit is configured so that each of its tasks is associated with a header, each processor unit is adapted to communicate with the other processor units using the following protocol: sending on the bus a message including a header characterizing a function, and possibly a frame consisting of one or more words, and each processor unit is adapted to decode each header on the bus and, as a function of the value of said header, either to ignore the message on the bus or to execute the task associated with the header of said message.

Abstract: A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a plurality of media devices. A first multimedia program is routed from a first source device to a first destination device. The A/V server detects a conflict when a second source device attempts to route a second multimedia program to the first destination device. To resolve the conflict, the A/V server determines suitable media devices to process the second multimedia program. The A/V server may send the second program to a second destination device to process the second program in the same manner as the first destination device. Alternatively, the A/V server may send the second program to a destination device capable of recording the second program.

Abstract: Image data scanned by way of a scanner controller is transferred from a memory controller to a memory by way of a G bus. A CPU reduces the image data stored in the memory by thinning processing or the like, and displays the image data on an operation panel by way of a B bus and interface. In this manner, an image can be input using the first bus while data transferred by way of the first bus is output by way of the second bus. This enables processing using image data which is being input, such as processing of immediately displaying an input image.

Abstract: An automated teller machine (ATM) implements financial transactions over the Internet. The ATM includes a computer and at least one non-standard I/O device coupled to the computer. The computer of the ATM interprets extended open network protocol statements to control the non-standard I/O device for purposes of implementing a financial transaction.

Abstract: A decoding method for reducing a delay time which makes a decoder perform continuously by controlling a relief width according to the characteristic of an input image is provided. The decoding method includes the steps of: (a) sequentially storing an input image signal in a buffer which predetermines a relief width; (b) performing decoding if the amount of the stored image signal is larger than the predetermined relief width of the buffer; and (c) resetting the relief width of the buffer by combining the prescribed decoded information. The relief width of the decoding input buffer is controlled according to the characteristics of the input image to make the decoder perform continuously and reduce a delay time, so that it has an effect of cleaning up the discomfort which a user may feel in watching an image signal.

Abstract: A switch is presented including a host input/output (I/O) port adapted for coupling to a controller, multiple device I/O ports each adapted for coupling to at least one device, and logic coupled between the host I/O port and the device I/O ports configured to selectively form a communication channel between the host I/O port and one of the device I/O ports. The switch may operate in a connected mode and a disconnected mode. When in the switch is in the disconnected mode, the logic may not form a communication channel between the host I/O port and any of the device I/O ports. In an ATA embodiment, the switch may comply with an AT attachment (ATA) standard, and thus be an ATA switch. The host I/O port may be adapted for coupling to an ATA controller, the device I/O ports may be adapted for coupling to at least one ATA device, and the logic may selectively form an ATA communication channel between the host I/O port and one of the device I/O ports.

Abstract: A method and system for detecting viruses on handheld computers. The handheld computer is in communication with a computer system having a virus detection program. The method includes reading data from the handheld computer and writing the data at least temporarily to a database on the computer system. The data is scanned for viruses with the virus detection program. The method further includes updating data on the handheld computer based on results of the scanning.

Abstract: A technique for decreasing VLAN lookup times in hardware-based packet switches by emulating the functionality of a content addressable memory (CAM) with software and random access memories (RAM). The decrease in lookup time is achieved by using content from the data packet to index directly into a table that stores forwarding information. Since the forwarding information is addressed directly by content from the packet, the need to spend time and resources sorting through the table of forwarding information with a key search is eliminated.

Abstract: A method for verifying data in a storage system is disclosed. A host computer transmits area management data to a storage controller. The area management data specifies a range of a storage area in a storage device to be used by an application program having a mechanism for verifying data suitability. Upon receipt of an input/output request transmitted from the host computer, the storage controller performs verification, which is usually performed by the application program, of the data that is to be processed according to the data input/output request and to be input/output to/from the storage area, which is specified in accordance with the received area management data.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Abstract: A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a second circuit having first and second terminals. The first terminal is coupled to the first circuit and the second terminal is coupled to the interface port. A signal level at the first terminal corresponds to a first combination of the input and output signals, and a signal level at the second terminal corresponds to a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the first and second combinations of the input and output signal levels.

Abstract: An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.

Abstract: A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.

Abstract: A controller of a recording device issues a secure command to a storage device, and then waits the time estimated necessary for the storage device to execute the secure command before issuing the next secure command. When a controller of the storage device is executing the previous command, it notifies the recording device of being in process. When the previous command has been completed normally, the controller moves to the next process. Information for estimating the execution time of the command is obtained from the storage device in advance.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.

Abstract: An interface device allows communication between a 1394 device and an Ethernet via an 802.3 PHY. To the 1394 link, the device appears as a 1394 PHY, to the 802.3 PHY, the device appears as an 802.3 MAC. The interface device includes a 1394 PHY-link link interface, a Gigabyte Media Independent Interface (GMII), checksum padding and checksum stripping units, emulated 1394 PHY registers, and a clock generation unit. The interface device uses two clocks to supply timing clocks for the 1394 link and for the 802.3 PHY. For speed matching, the interface device matches the data rate of the link (S100, S200, S400, S800) with the PHY (nominally 1 Gbps) using a padding algorithm. The interface device provides the link with management information through a set of IEEE 1394 compatible registers that are accessed through the 1394 interface, emulating a single port 1394 PHY. The interface device also manages the IEEE 802.3 PHY as would a MAC through the MDC/MDIO interface.

Abstract: A data read/write apparatus records, in a root directory of a recording medium, a file “MEM*****.ind” indicating the type of the recording medium, a directory “DCIM” for storing still image files, a directory “VOICE” for storing voice files, a directory “HIFI” for storing audio files, and a directory “MS******” for storing information inherent to a vendor. The rules are defined as the method for recording data in the recording medium. Hence, an audio-visual apparatus can determine the type of data stored in the loaded recording medium, recognizes the format of data in a non-conforming format, and erases the data in the non-conforming format.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: A method of guaranteeing a minimum sustained data transfer rate to a chosen device connected to a USB bus. A set of filter drivers are inserted in the driver stacks for at least two USB devices. These filter drivers are controlled by a filter driver controller that provides and receives information from the filter drivers. When a particular device needs a minimum sustained bandwidth for a transaction, the filter driver for that device notifies the filter driver controller. The filter driver controller then instructs the filter drivers for at least one other device to start interfering with USB transactions. This interference prevents the interfered with devices from using any of the USB bus bandwidth thereby providing a minimum sustained bandwidth to the non-interfered with device.

Abstract: A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.