Bus Expansion Or Extension Patents (Class 710/300)
  • Patent number: 11514195
    Abstract: A method may include, in an information handling system having a backplane comprising a plurality of connectors, each connector configured to receive an input/output device, and a motherboard communicatively coupled to the backplane via a cable having a presence detection wire configured to transmit presence detection information associated with the plurality of connectors and further having a plurality of data transmission wires: during a discrete mode, monitoring for an indicator from the backplane via the presence detection wire to determine if the backplane is configured for communication of serial presence detection information regarding the plurality of connectors and enter a serial mode in response to receiving the indicator; during the serial mode, receiving via the presence detection wire serialized frames including serialized presence detection information regarding input/output devices received in the plurality of connectors; and deserializing the serialized presence detection information and commu
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventor: Jeffrey L. Kennedy
  • Patent number: 11432438
    Abstract: The disclosure relates to a communication technique and system after 4G systems for combining a 5G communication system with IoT technology to support higher data rates. Based on 5G communication and IoT-related technologies, the disclosure can be applied to intelligent services (e.g., smart home, smart building, smart city, smart or connected car, healthcare, digital education, retail, security, and safety).
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyoungsoo Yeo, Jeonggyu Park, Jaejin Lee, Seongu Kang
  • Patent number: 11424779
    Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 23, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala
  • Patent number: 11388054
    Abstract: Various approaches for deployment and use of configurable edge computing platforms are described. In an edge computing system, an edge computing device includes hardware resources that can be composed from a configuration of chiplets, as the chiplets are disaggregated for selective use and deployment (for compute, acceleration, memory, storage, or other resources). In an example, configuration operations are performed to: identify a condition for use of the hardware resource, based on an edge computing workload received at the edge computing device; obtain, determine, or identify properties of a configuration for the hardware resource that are available to be implemented with the chiplets, with the configuration enabling the hardware resource to satisfy the condition for use of the hardware resource; and compose the chiplets into the configuration, according to the properties of the configuration, to enable the use of the hardware resource for the edge computing workload.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Arun Doshi, Ned M. Smith, Timothy Verrall, Uzair Qureshi
  • Patent number: 11379400
    Abstract: An extension apparatus for a universal serial bus (USB) interface includes a transmitting device, a receiving device and an electrical signal network cable. The transmitting device includes the following elements: a first packet-processing unit to receive a first interface packet and generate an original data accordingly, a first buffering unit to temporarily store the original data, and a first data-converting unit to generate and output a network packet signal based on the original data. The receiving device includes the following elements: a second data-converting unit to receive the network packet signal and generate the original data accordingly, a second buffering unit to temporarily store the original data, and a second packet-processing unit to receive the original data and generate the first interface packet. The electrical signal network cable is electrically coupled between the transmitting device and the receiving device to transmit the network packet signal.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 5, 2022
    Assignee: AVER INFORMATION INC.
    Inventors: Ting-Ju Tsai, Fu-En Tsai, Hung-Heng Hsu, Ming-Kang Chuang, Yung-Chun Lin
  • Patent number: 11321091
    Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 3, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Nai-Wen Cheng, Tzu-Lan Shen
  • Patent number: 11277931
    Abstract: A control device includes a casing and a control circuit substrate arranged inside the casing. The control circuit substrate includes: a control circuit mounted on the control circuit substrate; an internal connector connectable to a communication cable inside the casing, the communication cable being connected to an expansion circuit substrate; and an external connector connectable to another communication cable outside the casing, the another communication cable being connected to another expansion circuit substrate. The control circuit is connected to the internal connector and the external connector in parallel.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 15, 2022
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventor: Tsuyoshi Tagashira
  • Patent number: 11249808
    Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Anil Rao, Debendra Das Sharma
  • Patent number: 11243593
    Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 8, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Alan Osamu Kobayashi
  • Patent number: 11239614
    Abstract: The present invention discloses a sofa USB socket including: a USB female socket including a tongue core, wherein the tongue core includes 5 pins, and the fifth pin is an ID pin; and a USB circuit including a power circuit, a filter circuit, a control chip and a buck chopper circuit, wherein the buck chopper circuit includes a transistor, and the ID pin is electrically connected with the transistor. When an external USB male plug is inserted into the USB female socket, the power circuit supplies power to the USB female socket; when the USB female socket is in an unloaded state, the fifth pin is suspended, the control chip enters a sleep state, and the USB female socket has no output voltage, which greatly reduces the no-load energy consumption, thereby being beneficial to extending the endurance time and the service life of a power supply battery.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 1, 2022
    Assignee: HUIZHOU UPSPRING INTELLIGENT TECHNOLOGY CO., LTD
    Inventors: Fayun Qi, Zuochao Peng, Dinglue Chen, Dazhuan Tang, Zeming Sun, Zilong Li
  • Patent number: 11163348
    Abstract: Host interface devices are provided. A host interface device includes a first pin connected to a first node and a second pin connected to a second node. The host interface device includes a switch connected between the second node and a first voltage terminal, and configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device includes a pull-up resistor connected between the first node and a second voltage terminal. Moreover, the host interface device is configured to receive a memory detection signal from a storage device via the first pin when the first pin is electrically connected to the storage device.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 2, 2021
    Inventor: Gwangman Lim
  • Patent number: 11119957
    Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Sumit Puri, Bryan Schramm
  • Patent number: 11121559
    Abstract: A method is provided comprising: detecting a connection between an electronic device and a battery charger; transmitting to the battery charger a first request for at least one of a first voltage level and a first current level; receiving from the battery charger a signal; and charging a battery of the electronic device with the signal.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 14, 2021
    Assignees: Samsung Electronics Co., Ltd., Fairchild Korea Semiconductor Ltd.
    Inventors: Ku-Chul Jung, Erik Wilson Maier, Oscar Freitas, Kisun Lee, Chul-Eun Yun, Kwang-Sub Lee
  • Patent number: 11122699
    Abstract: An input connection device for an electronic device is provided. The electronic device includes a mother circuit board and a cabinet having a first wall. The input connection device comprises an insulation housing, a conductive connection unit, a circuit board, a switch, a first power wire and a second power wire. The insulation housing is disposed on the first wall and comprises a main body comprising a hollow channel. The conductive connection unit is disposed in the hollow channel and is engaged with the insulation housing. The circuit board is connected with the conductive connection unit directly. The switch has an input part and an output part. The first power wire is connected with the circuit board and the input part of the switch. The second power wire is connected with the output part of the switch and the mother circuit board.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 14, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sheng-Kuo Lin, Chia-Hao Yeh, Xin-Hung Lin
  • Patent number: 10990549
    Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 27, 2021
    Assignee: Icron Technologies Corporation
    Inventors: Sukhdeep Singh Hundal, Mohsen Nahvi, Remco van Steeden
  • Patent number: 10983927
    Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 20, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Tomoyuki Ono, Masaki Nudejima, Takayuki Hashimoto, Suguru Oue
  • Patent number: 10983495
    Abstract: The present disclosure relates to a control module circuit having a circuit communication input port, a circuit communication output port, a first controllable unit that has a first controller module, and a second controllable unit having a second controller module. The first controller module has a first communication input port connected with the circuit communication input port and a first communication output port. The second controller module has a second communication input port connected with the first communication output port and a second communication output port connected with the circuit communication output port. The first and second controllable units are adapted to be identified with a permanent identity by way of a transmittable data signal receivable at the communication input port and sequentially received by the first and second controllable units.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 20, 2021
    Assignee: GE Aviation Systems Limited
    Inventors: David Alan Elliott, James Angelo Elder, Peter James Handy, Denis Vaughan Weale
  • Patent number: 10970004
    Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Synopsys, Inc.
    Inventors: Shaori Guo, Jun Cao, Jigang Yang, Subramaniam Aravindhan, Saleem Mohammad, Chandrashekar B U
  • Patent number: 10764212
    Abstract: A modular switching network node for a communications network, i.e., an industrial communications network, where the modular switching network node comprises a switching network node base unit and at least one port module, the at least one port module comprises at least one connection interface for coupling to the communications network, and where the modular switching network node is configured to forward communication data over one of the connection interfaces of the modular switching network node to at least one additional connection interface of the modular switching network node. The switching network node base unit is configured such that at least one of the port modules is swappable for a functional module to expand the functionality of the switching network node.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 1, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventors: Heiko Hack, Timo Kistner, Urs Schweizer, Andreas Schäffler, Michael Wagner
  • Patent number: 10747267
    Abstract: In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 18, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey Kevin Jeansonne, Rahul V. Lakdawala, Roger D. Benson
  • Patent number: 10664029
    Abstract: A power supply apparatus supports USB-PD (Universal Serial Bus-Power Delivery) specification. A bus voltage VBUS is transmitted via a bus line. A first power supply circuit generates a first bus voltage having a first voltage level. A second power supply circuit generates a second bus voltage having a second voltage level that is higher than the first voltage level. A first switch is arranged between the bus line and an output terminal of the first power supply circuit. A second switch is arranged between the bus line and an output terminal of the second power supply circuit. A control circuit receives a control signal S1 via the bus line from a power receiving apparatus, which is a power supply target. The control circuit is structured to control the first switch and the second switch based on the control signal S1.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 26, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Fuminori Koga
  • Patent number: 10635590
    Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Ren Wang, Joseph Nuzman, Samantika S. Sury, Andrew J. Herdrich, Namakkal N. Venkatesan, Anil Vasudevan, Tsung-Yuan C. Tai, Niall D. McDonnell
  • Patent number: 10565264
    Abstract: The present invention is a method, system and apparatus for dynamically binding principal services to activities in a business process in a cross-enterprise business process management system. In a preferred aspect of the invention, the system can include a business process specification document processing engine configured to process business process specification documents in which each of the documents defines a business process. A deployment service can be coupled to the engine and programmed to generate and deploy partner link instances for corresponding partner links specified in the documents. Finally, a link base authority can be configured to notify each partner link instance when an endpoint reference to a principal service has changed. Notably, the business process specification documents can include BPEL documents. As such, the business process specification document processing engine can include a BPEL4WS run-time engine.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek W. Carr, Peter P. Eacmen, Ronny A. Pena, Ajamu A. Wesley
  • Patent number: 10535322
    Abstract: Example implementations relate to a system for enabling compression of a video output. For example, the system can include a circuit board including a plurality of slots, each slot to receive a module, a multiplexor coupled between the plurality of slots, and a management controller, among other components. The management controller can detect a respective type of module coupled to each of the plurality of slots and instruct the multiplexor to transmit signals between a first slot among the plurality of slots and a second slot among the plurality of slots in response to detection of a graphics coprocessor module coupled to the first slot and an accelerator module coupled to the second slot. Similarly, the management controller can compress a video output from the first slot using the second slot.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 14, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Chanh V Hua, Mujeeb Ur Rehman, Yuchen Xu
  • Patent number: 10503228
    Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Alan Osamu Kobayashi
  • Patent number: 10482017
    Abstract: Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Karl I. Taht, Christopher B. Wilkerson, Ren Wang, James J. Greensky
  • Patent number: 10467173
    Abstract: Some examples can enable virtual bridges to be hot plugged into a virtual Peripheral Component Interconnect (vPCI) system. For example, a number of subordinate buses that are connected to a vPCI bridge in the vPCI system can be determined. The vPCI system can be for a virtual machine. A parameter value can then be generated by adding an integer to the number of subordinate buses that are connected to the vPCI bridge. The integer can be a predefined number of additional subordinate buses to enable to be connected to the vPCI bridge. The parameter value can then be assigned to the vPCI bridge. This may enable additional virtual bridges to be hot plugged into the vPCI system at a later time. For example, a new virtual bridge can be added to the vPCI system using the parameter value for the vPCI bridge.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 5, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Gal Hammer, Marcel Apfelbaum
  • Patent number: 10467178
    Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 5, 2019
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC.
    Inventors: Shahin Solki, Stephen Morein, Mark S. Grossman
  • Patent number: 10460772
    Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 29, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takayuki Mori, Tatsuya Tokue, Haruya Iwata, Sohei Kushida, Satoshi Kamiya
  • Patent number: 10452593
    Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 22, 2019
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Tushar P. Ringe, Ashok Kumar Tummala, Gurunath Ramagiri
  • Patent number: 10402105
    Abstract: Systems and methods for replicating data from a first site to a second site remote from said first site are described. An embodiment includes storing compressed data on a hard disk appliance, reading said data without decompressing said data, sending said data over a wide-area-network (WAN) in a compressed state, and storing said data on a second hard disk appliance remote from said first hard disk appliance in its compressed state without performing an additional compression operation.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Overland Storage, Inc.
    Inventors: Dennis Desimone, Michael H. Reider, Kenneth Geist, Victoria Gonzalez
  • Patent number: 10366023
    Abstract: An operation method performed at a nonvolatile memory device may include receiving a program command and an address from an external device through a data signal (DQ), receiving a specific pattern from the external device through the data signal and a data strobe signal (DQS) synchronized with the data signal in a pattern period, receiving user data from the external device through the data signal and the data strobe signal in a data period, and selectively performing a program operation on the user data or a recovery operation based on a determination of whether the specific pattern matches with a particular pattern. A rising edge or a falling edge of the data strobe signal may be aligned with a left edge or a right edge of a window of the data signal in the pattern period.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 30, 2019
    Inventors: YoungWook Kim, Hyung-jin Kim, Soong-Man Shin, Keun-Hwan Lee
  • Patent number: 10255210
    Abstract: A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device over a bus that is different than a communication channel that the transaction is transmitted over. The ordering message includes the transaction identifier. The target device adjusts an order of execution of the transaction by the target device based at least in part on receiving the ordering message.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 9, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Guy Nakibly, Adi Habusha
  • Patent number: 10250690
    Abstract: The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 2, 2019
    Assignee: Camgian Microsystems Corp.
    Inventors: Gary Butler, Derrick J. Savage, David Lindley, Muthukumar Nagarajan, Jeffery Hunt
  • Patent number: 10234894
    Abstract: A signal generation circuit for producing an identification signal at a defined frequency. A frequency calibration circuit is electrically coupled to the signal generation circuit and is configured to set the defined frequency. The frequency calibration circuit includes a first calibration portion positioned on a first electrical subsystem and a second calibration portion positioned on a second electrical subsystem. An identification circuit is configured to process the identification signal to generate an identification result.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Daniel Dufresne
  • Patent number: 10225290
    Abstract: Systems and methods are disclosed for extending digital signal processor (DSP) capability of existing media gateway devices. A system includes a media gateway device, which has a first plurality of voice server cards. Each voice server card comprises a first controller, a first communications interface, and at least one first DSP configured to implement at least one first coder/decoder (codec). The system further includes a communications switch and at least one external DSP server. The external DSP server comprises a second plurality of voice server cards, which each comprise a second controller, a second communications interface, and at least one second DSP configured to implement at least one second codec. The at least one external DSP server is in communication with the media gateway device via the communications switch.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: March 5, 2019
    Assignee: GENBAND US LLC
    Inventors: Weisheng Chen, Hao Hou, David Z. Lu
  • Patent number: 10198391
    Abstract: An active input/output connector includes a first printed circuit board and a second printed circuit board enclosed within a housing. A first plug is in electronic communication with the first printed circuit board. A second plug is in electronic communication with the second printed circuit board. The first and second printed circuit boards are connected for communication of sensor signals from the first plug to the second plug.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 5, 2019
    Assignee: Hamilton Sunstrand Corporation
    Inventors: Jason C. Duffy, Kenneth J. Trotman
  • Patent number: 10135263
    Abstract: A method is provided comprising: detecting a connection between an electronic device and a battery charger; transmitting to the battery charger a first request for at least one of a first voltage level and a first current level; receiving from the battery charger a signal; and charging a battery of the electronic device with the signal.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 20, 2018
    Assignees: Samsung Electronics Co., Ltd, Fairchild Korea Semiconductor Ltd.
    Inventors: Ku-Chul Jung, Erik Wilson Maier, Oscar Freitas, Kisun Lee, Chul-Eun Yun, Kwang-Sub Lee
  • Patent number: 10055298
    Abstract: A method, article of manufacture, and apparatus for accessing data during data recovery. In some embodiments, this includes sending an I/O request from an application to an object, wherein the object is being recovered, establishing an I/O intercept, intercepting the application's I/O request with the I/O intercept, and redirecting the I/O request based on the status of the object's sub-objects.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 21, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael John Dutch, Christopher Hercules Claudatos, Mandavilli Navneeth Rao
  • Patent number: 10021217
    Abstract: Universal serial bus (USB) mass storage devices may be redirected to a server to create USB virtual mass storage devices. For characteristics of the redirected device to be propagated to other users (accessing the redirected device via the virtual device) it is necessary to alter the Mode Sense data. In one embodiment, certain users may be given only read-only access to the redirected device. In another embodiment only some of the redirected devices are write-protected. By saving characteristics of a redirected device in the server registry or active directory, the USB virtual bus driver may impose, for example, write-protection on one or more devices connected by one or more users.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 10, 2018
    Assignee: Dell Products L.P.
    Inventor: Gokul Thiruchengode Vajravel
  • Patent number: 9991657
    Abstract: Connector adapters that may have a MagSafe connector receptacle and a Universal Serial Bus Type-C connector insert. This may allow MagSafe chargers to be used to charge devices having Universal Serial Bus Type-C connector receptacles. This also may provide the breakaway characteristic of a MagSafe connector system for a device that does not include a MagSafe connector receptacle. Other adapters may have other types of magnetic connector receptacles and connector inserts.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: June 5, 2018
    Assignee: APPLE INC.
    Inventors: Ronald G. Powers, Kevin M. Keeler
  • Patent number: 9965370
    Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Zuoguo Wu, Jeffrey Ou, Sitaraman Iyer
  • Patent number: 9952791
    Abstract: A memory card includes a first signal terminal configured to output a first signal; a second signal terminal configured to output a second signal, the first and second signals being complementary to each other; and a controller configured to drive the first and second signal terminals to have a negative state until a link connection is performed after power is supplied to the memory card. When a level of the first signal is greater than a level of the second signal, the first and second signal terminals are in a positive state, whereas when a level of the first signal is smaller than a level of the second signal, the first and second signal terminals are in the negative state.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soonbok Jang, Sungho Seo, Sang-Hoon Lee
  • Patent number: 9949047
    Abstract: An electronic device is provided including a housing, an opening formed on a side of the housing, a hole connected to the opening, a receptacle disposed inside the hole, having a structure for receiving an external connector, and comprising a plurality of pins, a memory, a processor electrically coupled to the memory, and a circuit electrically coupled to the processor and the receptacle. When the external connector is inserted into the receptacle, the circuit may receive at least one of a signal and a current through at least one of the pins, and selects one of a plurality of audio signal processing methods provided to the external connector through the receptacle based on at least one of the received signal and the current.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heejun Ryu
  • Patent number: 9910420
    Abstract: An expansion module for a PLC, used in such a manner that at least one expansion module is sequentially connected to a basic unit in order to exchange massive data at high speed by using USB communication, is provided. Each of the expansion module includes a USB hub and a USB device, and is allocated with an exchange number from a USB host of the basic unit by activating the USB device according to input of a trigger signal. In addition, whether the USB hub is to be used is determined by deciding whether the expansion through the USB hub is required according to the allocated exchange number. Thus, a user needs only to arrange each of the expansion modules by a designation.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: March 6, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Hyun Woo Jang
  • Patent number: 9870333
    Abstract: A peripheral component interconnect express (PCIe) eXtensions for instrumentation (PXIe) chassis includes a backplane, multiple peripheral slots, a mezzanine card and an integrated accelerator module. The peripheral slots are located on the backplane and configured to receive insertable PXIe peripheral modules, respectively. The mezzanine card is on the backplane and configured to accommodate at least one of connectors, integrated circuits (ICs) and signal lines incorporated in the PXIe chassis. The integrated accelerator module is on the mezzanine card within the PXIe chassis and configured to accelerate processing of signals received from the PXIe peripheral modules.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: January 16, 2018
    Assignee: Keysight Technologies, Inc.
    Inventors: Kuen Yew Lam, Jared Richard, Chris R. Jacobsen, James Benson
  • Patent number: 9858236
    Abstract: It is inter alia disclosed to determine a type of a second apparatus being connected to a data interface of the first apparatus based on a state of an identification pin of the data interface, the data interface further comprising at least one data pin, wherein the type of the second apparatus relates to a communication via the at least one data pin, to check whether the second apparatus is configured to perform a further communication via the identification pin, and if said checking yields a positive result, to enable the further communication via the identification pin.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 2, 2018
    Assignee: Nokia Technologies Oy
    Inventors: Timo Juhani Toivanen, Jarmo Ilkka Saari, Timo Tapani Toivola
  • Patent number: 9837136
    Abstract: A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 5, 2017
    Assignee: Lexmark International, Inc.
    Inventor: James Ronald Booth
  • Patent number: 9804883
    Abstract: Described herein is an apparatus and method for remote scoped synchronization, which is a new semantic that allows a work-item to order memory accesses with a scope instance outside of its scope hierarchy. More precisely, remote synchronization expands visibility at a particular scope to all scope-instances encompassed by that scope. Remote scoped synchronization operation allows smaller scopes to be used more frequently and defers added cost to only when larger scoped synchronization is required. This enables programmers to optimize the scope that memory operations are performed at for important communication patterns like work stealing. Executing memory operations at the optimum scope reduces both execution time and energy. In particular, remote synchronization allows a work-item to communicate with a scope that it otherwise would not be able to access. Specifically, work-items can pull valid data from and push updates to scopes that do not (hierarchically) contain them.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 31, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marc S. Orr, Bradford M. Beckmann, Ayse Yilmazer, Shuai Che, David A. Wood, Mark D. Hill
  • Patent number: 9792249
    Abstract: A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 17, 2017
    Assignee: III HOLDINGS 2, LLC
    Inventors: David Borland, Arnold Thomas Schnell, Mark Davis