Abstract: A method carried out in a user equipment, UE (10), for enabling transfer of application context from a first edge data network (140) to a second edge data network (150), comprising: storing (702), in the UE, a data object (60), said data object comprising: routing information to the first edge data network, and a context identifier (62), based on which the first edge data network uniquely can identify the application context of the UE on an application server in the first edge data network; uploading (708), upon connecting (706) to the second edge data network, the data object to the second edge data network to enable the second edge data network to obtain the application context in response to supplying the context identifier to the first data network.

Abstract: A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Abstract: Described herein are techniques for a system to track usage of a software application on a remote device, without having connectivity to the remote device. The system transmits an activation token to a computing device different from the remote device to activate the software application, and receives a deactivation token generated by the remote device from the computing device when the software application is deactivated. The system uses transmission of an activation token and receipt of a deactivation token as indicators of start and end times of use of the software application. For example, the system uses the indicated start and end times to determine a billing period for use of the software application.

Abstract: In general, techniques are described for signaling IP path tunnels for traffic engineering using constraints in an IP network. For example, network devices, e.g., routers, of an IP network may compute an IP path using constraint information and establish the IP path using, for example, Resource Reservation Protocol, to signal the IP path without using MPLS. As one example, the egress router generates a path reservation signaling message that includes an egress IP address that is assigned for use by the routers on the IP path to send traffic of the data flow by encapsulating the traffic with the egress IP address and forwarding toward the egress router. As each router in the IP path receives the path reservation signaling message, the router configures a forwarding state to forward traffic encapsulated with the egress IP address to a next hop along the IP path toward the egress router.

Abstract: An extension module for function extension of a network assembly is provided, wherein the network assembly has a communication bus for providing communication between a logic unit of a base module of the network assembly and one or more extension modules, in particular one or more function devices and/or communication modules, and wherein the extension module is designed to be connected to the communication bus of the network assembly for function extension or function provision of the network assembly in order to provide at least one additional function of an electrical load connected to the network assembly.

Abstract: Systems and methods for transparent high availability for multi-customer support with hypervisor based bond implementation. The method can include creating a network path bond between a plurality of compute instances and a plurality of Network Virtualization Devices (“NVD”), the network path bond comprising a plurality of network paths, identifying a monitoring bond coupling the plurality of NVDs to a monitoring agent, creating a number of monitoring VNICs, each of the number of monitoring VNICs residing in one of the plurality of NVDs, overlaying a unique IP address to each of the monitoring VNICs, determining with the monitoring agent a health of at least one of network paths, the network paths including an active network path and an inactive network path, and activating the inactive network path when the active network path fails.

Abstract: A system and method for selecting audio capture sensors of wearable devices in obtaining voice data. The method provides obtaining signals associated with the user's voice at first and second wearable devices, comparing energy levels of the first and second signals, and selecting one or more audio capture sensors based on the energy levels of each signal. Due to the symmetry of the acoustic energy produced by the user's voice to a first and second wearable device, any difference in energy level between the total energy obtained by the first wearable device and the total energy obtained by the second wearable device can be attributed solely to ambient noise. Thus, the device with the higher total energy has a lower signal-to-noise ratio and selection of an audio capture sensor of the other wearable device with a higher signal-to-noise ratio is provided to obtain voice data moving forward.

Abstract: In general, techniques are described for signaling IP path tunnels for traffic engineering using constraints in an IP network. For example, network devices, e.g., routers, of an IP network may compute an IP path using constraint information and establish the IP path using, for example, Resource Reservation Protocol, to signal the IP path without using MPLS. As one example, the egress router generates a path reservation signaling message that includes an egress IP address that is assigned for use by the routers on the IP path to send traffic of the data flow by encapsulating the traffic with the egress IP address and forwarding toward the egress router. As each router in the IP path receives the path reservation signaling message, the router configures a forwarding state to forward traffic encapsulated with the egress IP address to a next hop along the IP path toward the egress router.

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

Abstract: In general, techniques are described for signaling IP path tunnels for traffic engineering using constraints in an IP network. For example, network devices, e.g., routers, of an IP network may compute an IP path using constraint information and establish the IP path using, for example, Resource Reservation Protocol, to signal the IP path without using MPLS. As one example, the egress router generates a path reservation signaling message that includes an egress IP address that is assigned for use by the routers on the IP path to send traffic of the data flow by encapsulating the traffic with the egress IP address and forwarding toward the egress router. As each router in the IP path receives the path reservation signaling message, the router configures a forwarding state to forward traffic encapsulated with the egress IP address to a next hop along the IP path toward the egress router.

Abstract: An example system to schedule service requests in a network computing system using hardware queue managers includes: a gateway-level hardware queue manager in an edge gateway to schedule the service requests received from client devices in a queue; a rack-level hardware queue manager in a physical rack in communication with the edge gateway, the rack-level hardware queue manager to send a pull request to the gateway-level hardware queue manager for a first one of the service requests; and a drawer-level hardware queue manager in a drawer of the physical rack, the drawer-level hardware queue manager to send a second pull request to the rack-level hardware queue manager for the first one of the service requests, the drawer including a resource to provide a function as a service specified in the first one of the service requests.

Abstract: A method may include, in an information handling system having a backplane comprising a plurality of connectors, each connector configured to receive an input/output device, and a motherboard communicatively coupled to the backplane via a cable having a presence detection wire configured to transmit presence detection information associated with the plurality of connectors and further having a plurality of data transmission wires: during a discrete mode, monitoring for an indicator from the backplane via the presence detection wire to determine if the backplane is configured for communication of serial presence detection information regarding the plurality of connectors and enter a serial mode in response to receiving the indicator; during the serial mode, receiving via the presence detection wire serialized frames including serialized presence detection information regarding input/output devices received in the plurality of connectors; and deserializing the serialized presence detection information and commu

Abstract: The disclosure relates to a communication technique and system after 4G systems for combining a 5G communication system with IoT technology to support higher data rates. Based on 5G communication and IoT-related technologies, the disclosure can be applied to intelligent services (e.g., smart home, smart building, smart city, smart or connected car, healthcare, digital education, retail, security, and safety).

Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: Various approaches for deployment and use of configurable edge computing platforms are described. In an edge computing system, an edge computing device includes hardware resources that can be composed from a configuration of chiplets, as the chiplets are disaggregated for selective use and deployment (for compute, acceleration, memory, storage, or other resources). In an example, configuration operations are performed to: identify a condition for use of the hardware resource, based on an edge computing workload received at the edge computing device; obtain, determine, or identify properties of a configuration for the hardware resource that are available to be implemented with the chiplets, with the configuration enabling the hardware resource to satisfy the condition for use of the hardware resource; and compose the chiplets into the configuration, according to the properties of the configuration, to enable the use of the hardware resource for the edge computing workload.

Abstract: An extension apparatus for a universal serial bus (USB) interface includes a transmitting device, a receiving device and an electrical signal network cable. The transmitting device includes the following elements: a first packet-processing unit to receive a first interface packet and generate an original data accordingly, a first buffering unit to temporarily store the original data, and a first data-converting unit to generate and output a network packet signal based on the original data. The receiving device includes the following elements: a second data-converting unit to receive the network packet signal and generate the original data accordingly, a second buffering unit to temporarily store the original data, and a second packet-processing unit to receive the original data and generate the first interface packet. The electrical signal network cable is electrically coupled between the transmitting device and the receiving device to transmit the network packet signal.

Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.

Abstract: A control device includes a casing and a control circuit substrate arranged inside the casing. The control circuit substrate includes: a control circuit mounted on the control circuit substrate; an internal connector connectable to a communication cable inside the casing, the communication cable being connected to an expansion circuit substrate; and an external connector connectable to another communication cable outside the casing, the another communication cable being connected to another expansion circuit substrate. The control circuit is connected to the internal connector and the external connector in parallel.

Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: The present invention discloses a sofa USB socket including: a USB female socket including a tongue core, wherein the tongue core includes 5 pins, and the fifth pin is an ID pin; and a USB circuit including a power circuit, a filter circuit, a control chip and a buck chopper circuit, wherein the buck chopper circuit includes a transistor, and the ID pin is electrically connected with the transistor. When an external USB male plug is inserted into the USB female socket, the power circuit supplies power to the USB female socket; when the USB female socket is in an unloaded state, the fifth pin is suspended, the control chip enters a sleep state, and the USB female socket has no output voltage, which greatly reduces the no-load energy consumption, thereby being beneficial to extending the endurance time and the service life of a power supply battery.

Abstract: Host interface devices are provided. A host interface device includes a first pin connected to a first node and a second pin connected to a second node. The host interface device includes a switch connected between the second node and a first voltage terminal, and configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device includes a pull-up resistor connected between the first node and a second voltage terminal. Moreover, the host interface device is configured to receive a memory detection signal from a storage device via the first pin when the first pin is electrically connected to the storage device.

Abstract: A method is provided comprising: detecting a connection between an electronic device and a battery charger; transmitting to the battery charger a first request for at least one of a first voltage level and a first current level; receiving from the battery charger a signal; and charging a battery of the electronic device with the signal.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

Abstract: An input connection device for an electronic device is provided. The electronic device includes a mother circuit board and a cabinet having a first wall. The input connection device comprises an insulation housing, a conductive connection unit, a circuit board, a switch, a first power wire and a second power wire. The insulation housing is disposed on the first wall and comprises a main body comprising a hollow channel. The conductive connection unit is disposed in the hollow channel and is engaged with the insulation housing. The circuit board is connected with the conductive connection unit directly. The switch has an input part and an output part. The first power wire is connected with the circuit board and the input part of the switch. The second power wire is connected with the output part of the switch and the mother circuit board.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: The present disclosure relates to a control module circuit having a circuit communication input port, a circuit communication output port, a first controllable unit that has a first controller module, and a second controllable unit having a second controller module. The first controller module has a first communication input port connected with the circuit communication input port and a first communication output port. The second controller module has a second communication input port connected with the first communication output port and a second communication output port connected with the circuit communication output port. The first and second controllable units are adapted to be identified with a permanent identity by way of a transmittable data signal receivable at the communication input port and sequentially received by the first and second controllable units.

Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.

Abstract: A modular switching network node for a communications network, i.e., an industrial communications network, where the modular switching network node comprises a switching network node base unit and at least one port module, the at least one port module comprises at least one connection interface for coupling to the communications network, and where the modular switching network node is configured to forward communication data over one of the connection interfaces of the modular switching network node to at least one additional connection interface of the modular switching network node. The switching network node base unit is configured such that at least one of the port modules is swappable for a functional module to expand the functionality of the switching network node.

Abstract: In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.

Abstract: A power supply apparatus supports USB-PD (Universal Serial Bus-Power Delivery) specification. A bus voltage VBUS is transmitted via a bus line. A first power supply circuit generates a first bus voltage having a first voltage level. A second power supply circuit generates a second bus voltage having a second voltage level that is higher than the first voltage level. A first switch is arranged between the bus line and an output terminal of the first power supply circuit. A second switch is arranged between the bus line and an output terminal of the second power supply circuit. A control circuit receives a control signal S1 via the bus line from a power receiving apparatus, which is a power supply target. The control circuit is structured to control the first switch and the second switch based on the control signal S1.

Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

Abstract: The present invention is a method, system and apparatus for dynamically binding principal services to activities in a business process in a cross-enterprise business process management system. In a preferred aspect of the invention, the system can include a business process specification document processing engine configured to process business process specification documents in which each of the documents defines a business process. A deployment service can be coupled to the engine and programmed to generate and deploy partner link instances for corresponding partner links specified in the documents. Finally, a link base authority can be configured to notify each partner link instance when an endpoint reference to a principal service has changed. Notably, the business process specification documents can include BPEL documents. As such, the business process specification document processing engine can include a BPEL4WS run-time engine.

Abstract: Example implementations relate to a system for enabling compression of a video output. For example, the system can include a circuit board including a plurality of slots, each slot to receive a module, a multiplexor coupled between the plurality of slots, and a management controller, among other components. The management controller can detect a respective type of module coupled to each of the plurality of slots and instruct the multiplexor to transmit signals between a first slot among the plurality of slots and a second slot among the plurality of slots in response to detection of a graphics coprocessor module coupled to the first slot and an accelerator module coupled to the second slot. Similarly, the management controller can compress a video output from the first slot using the second slot.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: Some examples can enable virtual bridges to be hot plugged into a virtual Peripheral Component Interconnect (vPCI) system. For example, a number of subordinate buses that are connected to a vPCI bridge in the vPCI system can be determined. The vPCI system can be for a virtual machine. A parameter value can then be generated by adding an integer to the number of subordinate buses that are connected to the vPCI bridge. The integer can be a predefined number of additional subordinate buses to enable to be connected to the vPCI bridge. The parameter value can then be assigned to the vPCI bridge. This may enable additional virtual bridges to be hot plugged into the vPCI system at a later time. For example, a new virtual bridge can be added to the vPCI system using the parameter value for the vPCI bridge.

Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

Abstract: Systems and methods for replicating data from a first site to a second site remote from said first site are described. An embodiment includes storing compressed data on a hard disk appliance, reading said data without decompressing said data, sending said data over a wide-area-network (WAN) in a compressed state, and storing said data on a second hard disk appliance remote from said first hard disk appliance in its compressed state without performing an additional compression operation.

Abstract: An operation method performed at a nonvolatile memory device may include receiving a program command and an address from an external device through a data signal (DQ), receiving a specific pattern from the external device through the data signal and a data strobe signal (DQS) synchronized with the data signal in a pattern period, receiving user data from the external device through the data signal and the data strobe signal in a data period, and selectively performing a program operation on the user data or a recovery operation based on a determination of whether the specific pattern matches with a particular pattern. A rising edge or a falling edge of the data strobe signal may be aligned with a left edge or a right edge of a window of the data signal in the pattern period.

Abstract: A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device over a bus that is different than a communication channel that the transaction is transmitted over. The ordering message includes the transaction identifier. The target device adjusts an order of execution of the transaction by the target device based at least in part on receiving the ordering message.

Abstract: The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Abstract: A signal generation circuit for producing an identification signal at a defined frequency. A frequency calibration circuit is electrically coupled to the signal generation circuit and is configured to set the defined frequency. The frequency calibration circuit includes a first calibration portion positioned on a first electrical subsystem and a second calibration portion positioned on a second electrical subsystem. An identification circuit is configured to process the identification signal to generate an identification result.

Abstract: Systems and methods are disclosed for extending digital signal processor (DSP) capability of existing media gateway devices. A system includes a media gateway device, which has a first plurality of voice server cards. Each voice server card comprises a first controller, a first communications interface, and at least one first DSP configured to implement at least one first coder/decoder (codec). The system further includes a communications switch and at least one external DSP server. The external DSP server comprises a second plurality of voice server cards, which each comprise a second controller, a second communications interface, and at least one second DSP configured to implement at least one second codec. The at least one external DSP server is in communication with the media gateway device via the communications switch.

Abstract: An active input/output connector includes a first printed circuit board and a second printed circuit board enclosed within a housing. A first plug is in electronic communication with the first printed circuit board. A second plug is in electronic communication with the second printed circuit board. The first and second printed circuit boards are connected for communication of sensor signals from the first plug to the second plug.

Abstract: A method is provided comprising: detecting a connection between an electronic device and a battery charger; transmitting to the battery charger a first request for at least one of a first voltage level and a first current level; receiving from the battery charger a signal; and charging a battery of the electronic device with the signal.

Abstract: A method, article of manufacture, and apparatus for accessing data during data recovery. In some embodiments, this includes sending an I/O request from an application to an object, wherein the object is being recovered, establishing an I/O intercept, intercepting the application's I/O request with the I/O intercept, and redirecting the I/O request based on the status of the object's sub-objects.