Abstract: A zone manager to provide a host with a list of storage drives that are not zoned to the host. The zone manager, in response to receipt of a command from the host to perform zone storage configuration for the host, to zone to host storage drives that were selected by the host from the list of storage drives.

Abstract: A mobile phone includes an earphone and a main body. The earphone includes a first universal serial bus (USB) interface, a first USB audio module connected to the first USB interface, a battery module connected to the first USB interface, a speaker module connected to the first USB audio module, a first BLUETOOTH module connected to the speaker module and the battery module, a microphone module connected to the first BLUETOOTH module, and a first antenna module connected to the first BLUETOOTH module. The main body includes a second USB interface, a second USB audio module connected to the USB interface, a control module connected to the second USB audio module, a detecting module connected to the second USB interface and the control module, a second BLUETOOTH module connected to the control module, and a second antenna module connected to the second BLUETOOTH module.

Abstract: Embodiments of the invention relate to a (e.g., hybrid) redundant array of independent disks (RAID)-based storage control board. Specifically, the present invention relates to a storage control board having a RAID controller with a peripheral component interconnect express (PCI-e) interface. In one embodiment, the RAID controller is coupled to an input/output (I/O) hub and a set (at least one) of PCI-e slots, which themselves can receive cards such as a fiber channel (FC) add-on card, a serial attached small component system interface (SAS) add-on card, or a PCI-e bridge add-on card. The I/O hub can be coupled to a set (at least one) of processors, each of which can be coupled to a main memory module or the like.

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract: A system and method for reserving resources of a host computer for use by an external device configured to be coupled to an expansion bus of the host computer are described. The host computer may be configured to execute device resource software that operates at a startup of the host computer to reserve one or more resources for the external device. The external device may not be available during the startup of the host computer, e.g., because the external device is not powered on or is not physically connected to the host computer. The device resource software may subsequently detect that the external device becomes available after the startup of the host computer. In response, the device resource software may enable the external device to use the one or more resources that were previously reserved at the startup of the host computer.

Abstract: Methods and systems are described for transmitting and displaying video data after a hot plug event during a start-up dead period. In particular, hot plug events occurring when a toggleable hot plug detection mechanism is use.

Abstract: A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.

Abstract: An electronic device is capable of connecting different expanding devices. The electronic device includes a Serial Attached Small Computer System interface (SAS) Expander, which includes a storage unit for storing a firmware of the SAS Expander, the firmware accommodating a physical layer attribute of any expanding device to be connected to the SAS Expander. The device further includes a processing unit to detect a physical layer attribute of an expanding device and parameters of the physical layer attribute when the expanding device is first connected to the SAS Expander, determine whether a firmware stored in the storage unit corresponds to the detected physical layer attribute, and write the detected parameters into the storage unit to form a new firmware if there is no firmware stored in the storage unit corresponding to the detected physical layer attribute.

Abstract: A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving the clock input signal and the output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving the multiplexed output at a first bus configured to receive the multiplexed output and to reduce an operational frequency of the first bus in response to an increase in an operational frequency of a second bus associated with the memory device.

Abstract: An adjustment device for automatically adjusting an interface expander with a signal port and a firmware is provided. The adjustment device includes a MCU connected to the signal port, a serial port, and an analysis unit connected to the MCU via the serial port. The MCU receives signals output by the signal port and convert the received signals to serial digital signals, and transmits the serial digital signals to the analysis unit. The analysis unit stores a digital signal reflecting a signal standard of the interface expander, and compare the received serial digital signals with the stored digital signal to determine whether the received serial digital signals accord with the stored digital signal, and produces an adjustment signal to the firmware to adjust a register value of the firmware when determining the received serial digital signals do not accord with the stored digital signal.

Abstract: A data-duplicating expander device attachable to a storage topology and a method. The data-duplicating expander device may include a direct-attached SAS expander configured for direct duplication of data from source disks to destination disks by bypassing transfer to or from a host system. The device may include dedicated expander phys and a processor. The device may be configured to receive instructions from an initiator storage-topology-connected device to configure or start a data transfer. The data-duplicating expander device may be configured to receive source data from source disks by utilizing dedicated expander phys and may be configured to transfer destination data directly and simultaneously to the destination disks by utilizing dedicated expander phys, said destination data being associated with the source data. Directly transferring destination data bypasses transfer of the source data or the destination data to or from a host system.

Abstract: An electronic device includes an IOM and a BMC. The IOM includes at least one pair of ports, each port capable of being connected to an external device, and each pair of ports is configured for exchanging data between two external devices connected to two ports of the pair. The BMC is electrically connected to the IOM, to respond to a user input to provide an interface for the user to input commands to control a working mode of each pair of ports of the IOM.

Abstract: The present invention relates to a plug-in module is capable of being inserted in a slot of a motherboard pluggably. The plug-in module includes an addressable element which has a slave address. The addressable element includes an interface address line group and a device-type address line group. When the plug-in module is inserted into the slot of the motherboard, the slot is able to automatically assign a corresponding interface address to the addressable element via the interface address line group. The device type address line group is integrated with a device-type identification code to identify a device type of the plug-in module. The slave address includes the interface address and the device-type identification code. Moreover, the present invention also relates to an electronic system, and a corresponding judging method and a corresponding querying method thereof.

Abstract: Link level load balancing is provided based on time utilization of a link or workload utilization of a device. Time utilization achieves load balancing by giving each device the same amount of connection time to perform Input/Output tasks. Workload utilization achieves load balancing by managing a number of frames or bytes transmitted to each device.

Abstract: The invention is directed to I/O Virtualization via a converged transport, as well as technology including low latency virtualization for blade servers and multi-host hierarchies for virtualization networks. A virtualization pipe bridge is also disclosed, as well as a virtual desktop accelerator, and a memory mapped thin client.

Abstract: A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the first host bus adapter of the first server is coupled to the second host bus adapter of the second server via a SAS connection, and wherein each of the first plurality of storage disks and the second plurality of storage disks are accessible by each of the first server and the second server.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention relate to a (e.g., hybrid) redundant array of independent disks (RAID)-based storage control board having a fiber channel interface controller. Specifically, the present invention relates to a storage control board having a RAID controller with a peripheral component interconnect express (PCI-e) interface and a fiber channel interface controller. In one embodiment, the RAID controller is coupled to an input/output (I/O) hub and a set (at least one) of PCI-e slots, which themselves can receive cards such as a fiber channel (FC) add-on card, a serial attached small component system interface (SAS) add-on card, or a PCI-e bridge add-on card. The I/O hub can be coupled to a set of processors, each of which can be coupled to a main memory module or the like.

Abstract: Techniques for management of target devices are provided. User input for management of a target device may be received. The user input may be converted into a first format. The first format may be encapsulated into a second format and sent over a communications channel. The second format may be un-encapsulated to recover the first format. The first format may be provided to the target devices.

Abstract: A method for configuring fieldbus stations, wherein station names and addresses for the fieldbus stations are executed by reading in a parameter over a first network port of a coupling element, which acts as a topology anchor so as to assign a unique addressing in a subnetwork, i.e., a unique name and a unique IP address, in a PROFINET-IO, such as a fieldbus based on Ethernet.

Abstract: Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.

Abstract: The innovation applies to a switch logic module (1), which can be electrically and mechanically connected to and disconnected from I/O modules (2) that are arranged next to each other, whereby the I/O modules have an electrical contact and the mechanical connection can be established using the electrical contacts. According to the innovation, a multiplex logic is provided that can be used to connect the electrical contacts of the I/O modules cyclically for a predefined switch time to an output (8) of the switch module. This provides a space-saving and cost-effective solution that can be used to cyclically switch multiple electrical signals to one output with little installation effort and great flexibility.

Abstract: The present invention pertains to a graphics processing unit. The graphics processing unit includes a graphics processing core configured for graphics processing. A single-ended I/O interface configured to implement single-ended communication with a frame buffer memory is included in the graphics processing unit. The graphics processing unit further includes a differential I/O interface having a first portion and a second portion. In a first configuration, the first portion and the second portion implement a PCI-Express interface with a computer system. In a second configuration, the first portion implements a PCI-Express interface with the computer system and the second portion implements differential communication with a coupled device.

Abstract: This disk array subsystem includes a data input/output unit for inputting and outputting data in and from the network, a connecting unit for connecting the data input/output unit and a plurality of storage apparatuses, and a control unit for controlling the input and output of data in and from the network. The control unit includes a logical link setting unit for zoning at least one or more physical links among a plurality of physical links for inputting and outputting data between the data input/output unit and the connecting unit, or between the connecting unit and the connecting unit into at least one or more logical links, and setting a plurality of logical links to one physical link; and a link unit for simultaneously multiplexing the data to a plurality of the logical links set with the logical link setting unit, and linking the data to the physical link.

Abstract: An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

Abstract: An apparatus for upgrading a standard PC system to a fail-safe computation system, comprising a plug device for plugging into the computation system, a memory module, a microcontroller, and a first device for generating a first time signal, wherein the microcontroller and the first device interact such that the computation system is provided with the first time signal through the plug device device.

Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester.

Abstract: Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester.

Abstract: A method, system, and connector interface for transferring status information between a media player and an accessory. The method includes determining, by the accessory, when a button event occurs; and transmitting, by the accessory, at least one button status command to the media player, where the one or more button status commands comprise a context-specific button status command and at least one command associated with a particular media type. According to the method and system disclosed herein, the media player and accessory may utilize a plurality of commands in a variety of environments such as within a connector interface system environment to facilitate the transfer of status information.

Abstract: A modularly constructed field device of process automation technology having a basic card with an executable, basic program, wherein the basic card is expandable by at least one expansion card containing at least one, executable, expansion program. For executing the basic program, the basic card comprises at least one computing unit and a first memory unit matched to memory requirement of the executable, basic program, characterized in that the expansion card comprises at least a second memory unit designed for memory requirement of the expansion program, an automatic detecting of the connected expansion card is provided by the basic card, and, for expanding the basic program by the expansion program, a partial and/or intermittent accessing of the second memory unit by the computing unit is provided.

Abstract: A storage assembly includes a physical expander for connection in use to two or more SCSI initiators, and two or more storage devices, wherein the expander is controlled such that it presents plural virtual expanders. A method for connecting two or more storage devices to two or more SCSI initiators within a storage assembly, includes providing a physical expander for connection in use to the two or more SCSI initiators, and two or more storage devices, and controlling the single expander such that it presents plural virtual expanders.

Abstract: The information processing system includes a plurality of information processing apparatuses connected via a network. Each apparatus includes one or more modules interconnected via a system bus. At least one of the modules is a network module having a network communication function. The information processing apparatus that inputs an external timing signal functions as a timing master, and the other information processing apparatuses function as a timing slave. The module in the timing master generates time synchronization information in the form of a packet and in the form of a command according to the timing signal and transmits the command to another module and transmits the packet to the timing slave via the network. The network module in the timing slave receives the packet from the timing master, converts the packet to the command to transmit to another module connected to the system bus and included in the timing slave.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: There is provided an electronic system (10) comprising one or more functionality devices (16, 20, 21) and an electronic device adapted so that the one or more functionality devices (16, 20, 21) are locatable in proximity to the electronic device. The electronic device is operable to recognize the presence of the one or more functionality devices (16, 20, 21). Upon recognition of said one or more functionality devices (16, 20, 21), the electronic device is operable to perform one or more additional functionality features associated with said one or more functionality devices while said one or more functionality devices are in close proximity to the electronic device.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: Methods and systems are described for displaying enabling the transmission, formatting, and display of multimedia data after a hot plug event during a start-up dead period. In particular, approaches for transmission, formatting, and display of multimedia data in the absence or non-operation of a hot plug detect system or signal, so that multimedia information can be displayed in a proper format even during the dead period when no hot plug detect signal is received.

Abstract: A peripheral component interconnect express (PCI-E) system has a reconfigurable link architecture. The system comprises a system slot adapted to receive a PCI-E compatible system controller, a plurality of peripheral slots adapted to receive a plurality of peripheral modules, and a reconfigurable switch fabric configured to create a variable number of PCI-E links between the system slot and the plurality of peripheral slots.

Abstract: An electronic device and an input method are provided.

Abstract: The invention relates to an electronic-board arrangement, comprising at least two electronic boards, particularly integrated circuit boards, which are attached to a backplane which provides electrical interconnection between the at least two electronic boards. An electronic interconnect board providing electrical interconnect between the at least two electronic boards is arranged in a space in between the at least two electronic boards and the backplane.

Abstract: The portable computer includes a PCIe controller, a DisplayPort connector, and a combination switch. The DisplayPort connector includes a hot plug pin. The combination switch is connected between the PCIe controller and the DisplayPort connector. The combination switch includes a selecting pin electronically connected to the hot plug pin. When the DisplayPort connector is electronically coupled to a discrete graphics card using PCIe, the hot plug pin sends a hot plug voltage signal to the selecting pin, and the combination switch electronically connects the DisplayPort connector to the PCIe controller after receiving the signal.

Abstract: Systems and methods of improving computing system interconnects may involve providing an upstream channel and a plurality of downstream channels. A passive matching node can be connected to the upstream channel and the downstream channels, wherein the matching node is configured to couple power between the upstream memory channel and the downstream channels. The matching node may also perform impedance matching as well as isolate two or more signals on the downstream channels from one another. In one example, the matching node includes a power divider/combiner.

Abstract: Systems and methods provide for illuminating a subject using a light pipe that transmits light from a source. A method includes providing a light pipe, the light pipe defining an inner lumen through which the image sensor views the subject; providing a light source in alignment with a proximal portion of the light pipe; and using the light source, projecting a light into the light pipe and through the light pipe, the light pipe including a distal portion for providing a high-angle bright field illumination pattern on the subject with a first portion of the light and for reflecting a second portion of the light for providing a low-angle dark field illumination pattern on the subject.

Abstract: An interface card with extensible input/output interface used for being inserted into a slot of a mainboard and for transmitting a bus signal to a remote backplane having a plurality of input/output interfaces, including a repeater, a serializer, a processor, and an interface unit is disclosed. The repeater is used for enhancing the bus signal. The serializer is connected to the repeater and is used for serializing the bus signal. The processor is connected to both the repeater and the serializer and is used for monitoring the transmission of the bus signal and for compensating the bus signal. The interface unit is connected to both the repeater and the serializer and is used for transmitting the serialized bus signal to the remote backplane.

Abstract: A hard disk expansion apparatus includes a printed circuit board (PCB), a connecting finger, and a signal expander. The connecting finger and the signal expander are both positioned on the PCB. The connecting finger receives a group of hard disk signals from a motherboard. The signal expander expands the group of hard disk signals into multiple-group of hard disk signals, and provides the multiple-group of hard disk signals to at least one hard disk.

Abstract: In a semiconductor storage device 10 included in a liquid container 20, on reception of an encoding request for encoding readout data, a write-read controller 140 changes over the position of a switch 141 to output encoded readout data, which is obtained by an encoding operation in a data encoding circuit 150, to a data signal terminal SDAT. In the case of no reception of the encoding request for encoding the readout data, on the other hand, the write-read controller 140 changes over the position of the switch 141 to output raw data read out from a memory array 100 to the data signal terminal SDAT.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: A method for identifying noise sources for automation devices (1, 2) which have a multiplicity of input/output modules (2a, 2b, . . .

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.