Abstract: A computer main unit and a PCI_Box (#0) are connected to each other in a loop connection manner by two paths. A first path is formed of an SMBus and a PCI_Box connection cable and a second path is formed of another PCI_Box connection cable. A monitoring and control unit (MMB) recognizes a connection path by reading out, through the second path, connection setting information written to the PCI_Box (#0) via the first path.

Abstract: A power supply device which comprises at least two power supply units and the same number of adapter cards, each of the adaptor cards comprising a number of hot swap circuits at least equal to a number of the power supply units is disclosed. In the power supply device power from each of the at least two power supply units is supplied to a respective one of the hot swap circuits within each of the adapter cards.

Abstract: An apparatus to recognize memory devices, the apparatus including a plurality of slaves having the same fixed address, a master controller to supply power to the slaves and to output a signal to select a predetermined slave, and a power control unit to control power supplied to the slaves in response to the selection signal. The apparatus is capable of decreasing production cost by using a plurality of slaves which have the same fixed address, reducing the complexity in the manufacturing process, and providing an easier management of replaceable parts in the apparatus using the replaceable parts which include memory devices. In addition, the same fixed address can be used without changing an existing I2C interface bus, which is a standard interface.

Abstract: The invention is to provide a mode setting method and a system including a PCI bus in the hot plug of a PCI device which is capable of supporting a platform unique function for a PCI device that is hot-added. Therefore, in a system including a PCI bus according to an exemplary embodiment of the invention, a south bridge directly notifies firmware that a PCI device is hot-added and thus, it is possible to support the platform unique function for the hot-added PCI device without modifying an OS or an open hot plug driver.

Abstract: An device bracket for mounting devices to a flat panel display incorporates a device hub able to form a network with devices coupled to it where the device hub associates one or more physical characteristics to devices coupled to it, including locality, orientation and position relative to the device hub. The device hub is conveys data indicating these physical characteristics associated with these devices to one or more of the devices coupled to it, thereby either enabling the devices with those physical characteristics to modify the manner in which they perform their own functions in response to those physical characteristics, or enabling other devices to modify data that they exchange with the devices having those physical characteristics in response to those physical characteristics.

Abstract: In some embodiments a system includes one or more processing nodes, a backplane, and one or more links to couple the one or more processing nodes to the backplane, wherein at least one of the one or more links is configurable as a standard Input/Output link and/or as a proprietary link. Other embodiments are described and claimed.

Abstract: A motherboard which can play an image or a video in a power-off state is disclosed. The motherboard includes a circuit board, a north bridge chipset, a digital photo frame chipset, and a switch unit. The north bridge chipset, the digital photo frame chipset, and the switch unit are disposed on the circuit board. The digital photo frame chipset is activated according to a stand-by power in the power-off state. The switch unit is electrically connected with the north bridge chipset and the digital photo frame chipset, respectively. The switch unit electrically communicates with the north bridge chipset or the digital photo frame chipset according to a triggering signal. The motherboard may utilize the stand-by power in the power-off state to display an image by a display device via the digital photo frame chipset and the north bridge chipset when a computer system is powered off.

Abstract: A memory card connector having user identification functionality is provided. The memory card connector has a connector and a cover. The connector encloses a space in which a memory card module and a user identification module are disposed, wherein a partition disposed in the space separates the memory card module and the user identification module, and wherein the memory card module is adapted for receiving a memory card and the user identification module is for receiving a user identification card. The memory card module has a conductive terminal set at one end thereof and the user identification module has a conductive terminal set at a backside thereof for providing user identification functionality. The cover covers a top of the connector.

Abstract: In one embodiment, provided is a method that includes detecting disconnect of a link at a Universal Serial Bus (USB) device coupled to a USB host via a USB bus, disconnecting the USB device from the USB bus, and modifying a power state of the USB device to a reduced power state. Disconnecting the USB device from the USB bus includes configuring the USB device such that the USB host recognizes the USB device as being disconnected from the USB bus. The reduced power state allows the USB device to monitor a status of the link such that the USB device is able to detect a reconnect of the link.

Abstract: A first SAS expander including at least two phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Abstract: A solid-state disk comprising a board and a plurality of connecting interfaces is provided. The plurality of connecting interfaces comprise a mini peripheral component interconnect express (Mini PCI Express) interface, a serial advanced technology attachment (SATA) interface and an universal serial bus (USB) interface, wherein the Mini PCI Express interface is placed on a side of the board and connects to a expandable memory, the SATA interface is placed on a side of board and connects to a host, the USB interface is placed on a side of the board and is connects to a host.

Abstract: A positioning device for a computer read/write or storage device is provided. The positioning device allows the computer read/write or storage device (such as an optical disk drive, a hard disk drive, or a magnetic disk drive) to be readily installed in a computer chassis and rapidly detached therefrom for replacement without using screws.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing.

Abstract: A scalable computer node includes a first central processing unit (CPU), a memory subsystem, and a socket that is configured to receive a second CPU. An expansion module is mounted in the socket instead of the second CPU, where the expansion module is socket-compatible with the second CPU. The expansion module has a CPU interface to communicate with the first CPU, a memory interface to communicate with the memory subsystem, and a fabric interface to communicate over a communications fabric with an expansion electronic subsystem to expand a capacity of the computer node.

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract: A KVM switch expansion device includes a box disposed with multiple I/O ports thereon and containing a control component connected to those I/O ports; one or a multiple space is disposed to the box for accommodating expansion module at where other than those I/O ports are provided or the expansion module is separately provided in the form of another box to directly create telecommunication connection with the control component by means of a connection interface for the existing KVM switch to provide new user interface with an expansion module.

Abstract: A mother board is disclosed. The mother board includes a first processor and a controlling module. A second processor is electrically coupled to the mother board. The controlling module includes a utilization ratio comparing unit and a controlling unit. The utilization ratio comparing unit is configured for comparing a current utilization ratio of the first processor with a predetermined first utilization ratio, and comparing a current utilization ratio of the second processor with a predetermined second utilization ratio. The controlling unit is configured for controlling the first processor and the second processor to process data together when the current utilization ratio of the first processor is lower than the predetermined first utilization ratio and the current utilization ratio of the second processor is higher than the predetermined second utilization ratio.

Abstract: The present invention is directed to a serial bus extension that provides for a new class of 1394 devices called versaphy devices. A versaphy device has a static (permanent or semi-permanent) address or versaphy label. In addition, the versaphy device has a new register structure called a versaphy register. The versaphy register may contain the versaphy label. The versaphy register can be written to by non-local devices such a controller. New simple versaphy packets are defined to facilitate communication between a versaphy device and a controller. The versaphy device can transmit unsolicited responses. These features reduce the complexity necessary for a device to connect to a 1394 bus and, therefore, reduce the cost of these devices.

Abstract: A circuit for preventing a computer from being powered on before a CPU of the computer has been properly installed, the circuit includes a power supply (70) for the computer, a controller (60) connected to the power supply configured for controlling the power supply, a switch (10) exposed outside the computer for convenient operation, and a switching device (Q1). The controller includes a terminal for receiving a computer startup signal. The switch is connected to the terminal of the controller for sending the computer startup signal to the controller when the switch is triggered, wherein when the computer startup signal is sent to the sensing terminal of the controller, the controller controls the power supply to provide power to the computer. The switching device includes a control terminal configured for sensing if the CPU is installed to control conduction of the switching device.

Abstract: A system and method for personal digital technology forensics. The system and method can provide for the forensic identification, preservation, acquisition, analysis, presentation, exportation, and correlation of evidence obtained personal digital technologies including that obtained from cellular phones, personal digital assistants (PDAs), and smart phones.

Abstract: An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo.

Abstract: An AIO PC has its LVDS link or interface, between the mother board and the LCD, modified by the insertion of an LVDS Switch which can connect to a second LVDS source such as LCD controller which takes its input from a socket mounted on the housing of the AIO PC. The LVDS switch and LCD controller are located within the enclosure or housing of the AIO PC. The LVDS switch is controlled by a physical electromechanical switch.

Abstract: A method and apparatus for downloading content to a large-capacity internal memory in a portable terminal are provided. The method includes performing a booting process of the portable terminal at the occurrence of a booting event, examining whether a Universal Serial Bus (USB) port is enabled during the booting process, if the USB port is enabled, receiving data through the USB port before driver loading, and storing the received data into the large-capacity internal memory and performing the booting process.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.

Abstract: An apparatus and method for coupling a host computer to one or more peripherals or for coupling peripherals to one another. In one example, the apparatus includes a hub having an upstream port for coupling with the host computer and one or more downstream ports for coupling with the one or more peripherals; and a local host dynamically coupled with the upstream port. In one example, when the host computer is not coupled with the upstream port, the local host communicates with the peripherals; and when the host computer is coupled with the upstream port, the local host disconnects from the upstream port so that the host computer communicates with the peripherals through the hub. In this manner, the apparatus may be used to couple peripherals to a host computer, or when a host computer is not present, the data from the peripherals may be communicated through the local host. Other embodiments are also disclosed.

Abstract: Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.

Abstract: Methods and systems are provided for helping maintain isochronous communications with peripheral devices (308), such as USB devices, over a network (302). Some methods for facilitating isochronous IN communication include noting (1906) passage of a predetermined interval without communication (310) from the peripheral device driver (402), and then creating (1908) a dummy communication (312) and sending (1910) it over the network toward the peripheral device to maintain isochronous communication toward the peripheral device. Some methods for facilitating isochronous OUT communication include noting (2006) passage of a predetermined interval without receipt, over the network, of a responsive communication (310) from the peripheral device in response to a first communication, and then creating (2008) a dummy communication (312) and sending (2010) it toward the peripheral device driver to maintain isochronous communication transmissions toward the peripheral device driver.

Abstract: A slot interface access device including a slot management module; a slot control module; and a physical slot to management slot contrast table, the slot management module, the slot control module, and the physical slot to management slot contrast table being provided between an input and output control module and a slot interface lower than the input and output control module. The input and output control module accesses the slot interface using virtual slot identification information. The slot management module converts the virtual slot identification information into physical slot identification information while referring to the physical slot to management slot contrast table, and accesses the slot control module corresponding to the physical slot identification information obtained by conversion, thereby realizing a physical access of the input and output control module to the slot interface.

Abstract: A slot interface access device including a slot management module; a slot control module; and a physical slot to management slot contrast table, the slot management module, the slot control module, and the physical slot to management slot contrast table being provided between an input and output control module and a slot interface lower than the input and output control module. The input and output control module accesses the slot interface using virtual slot identification information. The slot management module converts the virtual slot identification information into physical slot identification information while referring to the physical slot to management slot contrast table, and accesses the slot control module corresponding to the physical slot identification information, thereby realizing a physical access of the input and output control module to the slot interface. The slot interface access device is higher in CPU capability than other devices each including the slot interface.

Abstract: A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed by the two processors, at least one cache memory via which the first processor has access to the memory, at least one bridge via which the second processor has access to the memory.

Abstract: A modeling system and process for computer-aided, block-based modeling by preparing a first block diagram in a first model plane that relates to a first abstraction stage, in which at least one block is placeable in the first model plane and several blocks are connectable to one another by horizontal data transfer devices for horizontally exchanging data. At least one other block diagram is arrangeable on at least one other model plane assigned to the first abstraction stage that is separated from the first model plane. The first block diagram of the first model plane and the other block diagram of the other model plane form an overall block diagram that can be arranged on a selection of at least two model planes from the first model plane and the other model planes, so that a vertical exchange of data between at least two selected model planes can be produced.

Abstract: Techniques are disclosed for enabling a single computer system to execute both operating systems that permit multiple devices to be mapped to a single PCI function and operating systems that do not permit such mapping. Prior to loading and executing an operating system (e.g., during system reset), the computer system determines whether the operating system supports mapping of multiple devices to a single function. If such mapping is supported, the computer system maps multiple devices on a single PCI card to a single function in the PCI configuration space for the card. If such mapping is not supported, the computer system maps each device to a separate PCI function. The computer system then loads and executes the operating system. The operating system is thereby enabled to access all devices on the bus according to the particular device-function mapping scheme supported by the operating system.

Abstract: A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

Abstract: In a communications network, a cluster switch is provided, where the cluster switch has plural individual switches. An abstraction layer is provided in the cluster switch, such that an interface having a set of ports is provided to upper layer logic in the cluster switch. The set of ports includes a collection of ports of the individual switches. Control traffic and data traffic are communicated over virtual tunnels between individual switches of the cluster switch, where each virtual tunnel has an active channel and at least one standby channel.

Abstract: A portable electronic apparatus and a connection method therefore are disclosed. The portable electronic apparatus comprises a connector, a processing circuit, and a switch module. After a plug is plugged into the connector, the processing circuit reads a voltage value of the plug via the switch module. When determining that the voltage value of the plug is within a first voltage range, the processing circuit outputs switch signals to the switch module, so that an input signal of the plug is able to be transmitted to the processing circuit via the connector and the switch module. When determining that the voltage value of the plug is within a second voltage range, the processing circuit outputs other switch signals to the switch module, so that an output signal of the processing circuit is able to be transmitted to the plug via the switch module and the connector.

Abstract: A wireless data terminal device comprises a detachable USB connector and a main circuit board, where at least two redundancy grounding connections are provided between the detachable USB connector and the main circuit board, and the grounding points of the at least two redundancy grounding connections are not adjacent to each other. A method for improving the radio performance of the wireless data terminal device is further provided. With the wireless data terminal device or the method for improving the radio performance of the wireless data terminal device, the connection of the grounding plane of the wireless data terminal device with the grounding plane of a computer is effectively enhanced. Therefore, the radio performance of the wireless data terminal device is improved.

Abstract: A high-speed serial ATA physical layer includes a serial ATA control circuit. A serial ATA multiplexer outputs one of a plurality of serial ATA signals that is selected by the serial ATA control circuit. A serial ATA analog front end provides a first gain and pre-emphasis to the selected one of the plurality of serial ATA signals. The pre-emphasis alters a transmission characteristic of the selected one of the plurality of serial ATA signals.

Abstract: A support identification device comprising a support (BPA), e.g. a rack or backplane of a telecommunication system, and an identity receiver (PCB), e.g. a printed circuit board or card, coupled to an identity transmitter or connector of the support. The identity transmitter has several read pins (id1-id4=R1-R4) each at a logical level (0, 1) to indicate (identify) the type of support. The card (PCB) further has write terminals (W1, W2) coupled to dynamic terminals (D1, D2) of the support (BPA). These dynamic terminals are coupled to one or more of the read pins (id1-id4). The card is also provided with a program that sets the write terminals at a first logical level, reads a first logical level at each read pin (R1-R4), then sets the write terminals at a second logical level, reads a second logical level at each read pin, and determines from the difference between the first and the second read logical levels to which write terminal each read terminal is coupled, or not.

Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager.

Abstract: A method and system for enabling personal digital assistants (PDAs) and protecting stored private data. Specifically, one embodiment in accordance with the present invention includes a removable expansion card about the size of a postage stamp which plugs into a slot of a personal digital assistant. The removable expansion card, referred to as a personality card, is capable of storing all of a user's private information and data which is used within their personal digital assistant. By removing the personality card from the personal digital assistant, all of the user's private information and data may be removed from the personal digital assistant. Furthermore, the personal digital assistant may also be rendered totally or partially useless once the personality card is removed from it. There are several advantages associated with a personality card system in accordance with the present invention.

Abstract: An improved KVM switch is provided which enables computers to be connected to the KVM switch by reduced numbers of cables. It also supports transmission of digital audio signals between the computers and the KVM switch. A single USB port is provided to transmit keyboard, mouse, speaker and microphone signals between the KVM switch and each computer. The improved KVM switch is provided with one or more USB hubs to separate the keyboard/mouse signals and the digital audio signals, and one or more audio codecs to convert the audio signals from a digital form to an analog form and vice versa.

Abstract: Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.

Abstract: An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.

Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

Abstract: The present invention provides a method and apparatus for converting, through add-on hardware and code, any of a variety of types and vintages of general purpose personal, laptop, or notebook computers to be an efficient, secure, dedicated system which run independently of the host system's resident operating system.

Abstract: An external storage device accessible to a host is proposed. The external storage device includes a memory device and a processing unit. The memory device includes a protected area for storing an authentication application, a public area for storing an unlock application, and a reserved area for storing authentication information. The processing unit is used for performing an identification request from the authentication application. When the authentication information is confirmed, the host is allowed to access the protected area of the external storage device, accordingly.

Abstract: A computer capable of automatic bandwidth configuration according to I/O expansion card (e.g., PCI-Express expansion card) type is provided. A motherboard of the computer includes an I/O expansion slot, a chipset, and a configuration setting circuit. When the I/O expansion slot supports different types of I/O expansion cards having multiple interface card slot combinations, a corresponding bandwidth configuration message is generated on the I/O expansion card. The bandwidth configuration message is used to indicate the type of the I/O expansion card that is being used and thereby control the configuration setting circuit to adjust the bandwidth configuration in the chipset.

Abstract: A connector interface system for a communication device is disclosed. The interface includes a docking connector. The docking connector includes first make/last break contacts that minimize internal damage to the internal electronics. The docking connector also includes specific keying arrangement to prevent noncompliant connectors from being plugged in, and thereby minimizes potential damage to the multi-communication device. The connector interface system also includes a remote connector which provides for the ability to output audio, input audio, provides I/O serial protocol, and to provide an output video. Embodiments of the present invention allow for a standard headphone cable to be plugged in but also for special remote control cables, microphone cables, video cables could be utilized in such a system. The connector interface system also includes a serial protocol to control device features. These controls help a user sort and search for data more efficiently within the device.

Abstract: An improved extended cardbus/PC card controller (20) incorporating proprietary Split-Bridge™ high speed serial communication technology for interconnecting a conventional parallel system bus via a high speed serial link with a remote peripheral device. The extend cardbus/PC card controller is adapted to interface the parallel system bus, which may be PCI, PCMCIA, integrated, or some other parallel I/O bus architecture, with peripheral devices via PC cards, and now optionally via a high speed serial link using the proprietary serial Split-Bridge™ technology. The serial Split-Bridge™ technology provides real time interconnection between the parallel system bus and the remote device which may also be based on a parallel system data bus architecture, over a serial link, which serial link appears to be transparent between the buses and thus facilitates high speed data transfer exceeding data rates of 1.0 GigaHertz.