Bus Expansion Or Extension Patents (Class 710/300)
  • Patent number: 7383371
    Abstract: A physical layer circuit including: a VBUS detection circuit which makes a VBUS detection signal VBDET active when a VBUS voltage has exceeded a predetermined voltage; a receiver circuit which performs reception processing using signals DP and DM; and a reception control circuit which outputs an enable signal to the receiver circuit. When the signal VBDET is inactive, the reception control circuit makes the enable signals COMPENB, SEENB1 and SEENB2 inactive and disables the receiver circuit. When signals FCOMPENB, FSEENB1 and FSEENB2 set by a processing section are active but the signal VBDET is inactive, the reception control circuit makes the signals COMPENB, SEENB1 and SEENB2 inactive.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: June 3, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Shoichiro Kasahara
  • Publication number: 20080126654
    Abstract: The present invention is directed to a serial bus extension that provides for a new class of 1394 devices called versaphy devices. A versaphy device has a static (permanent or semi-permanent) address or versaphy label. In addition, the versaphy device has a new register structure called a versaphy register. The versaphy register may contain the versaphy label. The versaphy register can be written to by non-local devices such a controller. New simple versaphy packets are defined to facilitate communication between a versaphy device and a controller. The versaphy device can transmit unsolicited responses. These features reduce the complexity necessary for a device to connect to a 1394 bus and, therefore, reduce the cost of these devices.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Inventors: Richard Mourn, Barry Walker
  • Publication number: 20080126653
    Abstract: A portable web server that is connectable to a terminal through a USB port. The terminal is any device that can make HTTP requests to and receive HTTP responses from the portable web server. The portable web server includes a web server program and one or more web application programs. When the web server is connected to the terminal, a user of the terminal or an application on the terminal may access the web application that is contained on the portable web server. The web application is accessed using a web browser on the terminal. Data may be stored in a data storage area on the portable web server. The portable web server may be disconnected from the terminal and moved to a different terminal.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Applicant: Icon Global, Ltd.
    Inventors: Andrew E. King, Korey Calmettes
  • Patent number: 7376775
    Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Stanley Steven Kulick, Dean A Mulla, Ashish Gupta, Keith R. Pflederer, Shivnandan D. Kaushik, Mohan J. Kumar, James B. Crossland
  • Publication number: 20080114918
    Abstract: A method for providing multiple configurations for a computer system. The method provides interconnection of processor boards in a first configuration and a second configuration. In the first configuration, a first plurality of processor boards are interconnected through a first backplane. In a second configuration, a second plurality of processor boards are interconnected through a second backplane. The first and second pluralities of processor boards are interchangeable with each other.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Inventors: Ravi B. Bingi, Ranger H. Lam, Thomas Madaelil, Lloyd W. Gauthier, Brian E. Longhenry, Kristy M. Cates, Christopher E. Tressler
  • Patent number: 7370134
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 7366864
    Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey R. Jobs, Thomas A. Stenglein
  • Publication number: 20080098147
    Abstract: A bus repeater lying within a demodulation IC performs a bus repeat operation after a repeat operation has been made effective, and terminates the repeat operation on an autonomous basis when a stop condition for each serial data is detected. During the repeater operation, control on the direction of data transfer of a master-side IIC bus and control on the direction of data transfer of a tuner-side IIC bus corresponding to a repeat destination are performed by a master-side IIC bus transaction while they are being synchronized with each other. Therefore, the CPU-side IIC bus and the tuner-side IIC bus seem to be through-connected as the flow of the serial data. Further, data transfer can be done only when the swapping of the data with the tuner side is needed.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 24, 2008
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Shigeru Amano
  • Patent number: 7363441
    Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines and includes a non-volatile memory, a command packet decoder, and a control unit such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-vo
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-kyoon Yim, Sang-kil Lee
  • Patent number: 7355438
    Abstract: An electronic circuit for terminating a plurality of conductors at a node of a network, including means to detect current flowing through one of the conductors and means to switch between a continuing circuit, whereby continuity of the network is maintained, on detecting current above a first predetermined threshold, and a terminating circuit, whereby the network is terminated with an appropriate terminating circuit, upon detection of current at, or below, a second predetermined threshold.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: April 8, 2008
    Assignee: Moore Industries-International, Inc.
    Inventor: Hassan El Sayed
  • Patent number: 7356715
    Abstract: When a host 101 is connected to a device 102 via a USB cable 103, the ID terminal on the device 102 is short-circuited to the GND line, hence to reduce the voltage level of the ID terminal. Since power feeding means 109 starts feeding power to the VBUS terminal when detecting that the voltage level of the ID terminal turns from “H” to “L”, the power is supplied to the host 101 through the VBUS line of the USB cable 103.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 8, 2008
    Assignee: TDK Corporation
    Inventor: Kaoru Okayasu
  • Publication number: 20080082714
    Abstract: Systems, methods and apparatus are provided through which, in some embodiments, a USB flash memory storage device includes a plurality of interfaces to external devices. An apparatus to store data can include a non-volatile computer memory coupled by a male interface to an external device, such as a computer, and a by a female interface to another external device, such as another apparatus to store data. Thus, multiple apparatus may be coupled together in daisy-chain fashion to create a single, larger memory device that can be accessed by the computer.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: NASA HQ's.
    Inventor: Michael G. HINCHEY
  • Patent number: 7346728
    Abstract: Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional signals allow optimization of power distribution for powering attached devices, and for detecting and handling illegal connection configurations. In another approach, improvements are realized through use of alternative signaling techniques which eschew reflective and high-speed common-mode signaling. Described are various configuration, media and signal-protocol combinations, including implementations containing embedded hubs. Methods ensuring reliable system behavior are also described, including determination of extension path delay and use of topology-enforcement hubs.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventor: Daniel Kelvin Jackson
  • Patent number: 7346719
    Abstract: The present invention provides systems, methods, and bus controllers (12) for monitoring an event of interest via a network bus (14) and creating an asynchronous event trigger on the network bus indicating that the event occurred. Importantly, the systems, methods, and bus controllers (12) of the present invention use either one or several network devices (16, 18) that are connected to the network bus (14) and monitor the occurrence of an event of interest. These network devices (16, 18) are configure through commands from the bus controller (12) to indicate on the network bus (14) typically by a pulse signal, when the event of interest has occurred. The indication from the network device (16, 18) that the event has occurred is used by the bus controller (12) and other network devices (16, 18, 20) on the network bus (14) to configure timing for commands or to perform desired actions in synchronization with the occurrence of the event of interest.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: March 18, 2008
    Assignee: The Boeing Company
    Inventors: Philip J. Ellerbrock, Daniel W. Konz, Christian J. Noll
  • Patent number: 7346710
    Abstract: An apparatus for expanding I/O is described in which no additional strobes or enable lines are necessary from the host controller. By sequencing data in a specific way when output to two existing data or select lines, an expansion I/O device can generate a strobe or enable signal internally. This internal strobe or enable signal is then used to store output data or enable input data. The host controller needs software or firmware to perform the data sequencing, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 18, 2008
    Inventor: Stephen Waller Melvin
  • Patent number: 7343436
    Abstract: The present invention is carried out to provide a system controller, a control system and a system control method which are inexpensive, highly stable, capable of storing all information and past record at a time when one of the devices is down and capable of switching the devices without any time lag. The system controller comprises a bus arbiter and a non-volatile memory and has only periodically executed functions and passive functions. The system includes a bus employing a center arbitration method, from which devices can be detached from and to which the detached devices can be attached again as power being supplied. Even if one of the devices is down, processes can be immediately continued by switching from the down device to other device by utilizing the system controller and the bus.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: March 11, 2008
    Assignee: Kabushiki Kaisha Forks
    Inventor: Kunio Atago
  • Patent number: 7340537
    Abstract: A memory agent may include a link interface having bit lanes and may utilize more than one bit lane to determine if another memory agent is also connected to the same link interface.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventor: Pete D. Vogt
  • Patent number: 7337255
    Abstract: The distributed data handling and processing resources system of the present invention includes a) a number of data handling and processing resource nodes that collectively perform a desired data handling and processing function, each data handling and processing resource node for providing a data handling/processing subfunction; and, b) a low latency, shared bandwidth databus for interconnecting the data handling and processing resource nodes. In the least, among the data handling and processing resource nodes, is a processing unit (PU) node for providing a control and data handling/processing subfunction; and, an input/output (I/O) node for providing a data handling/processing subfunction for data collection/distribution to an external environment. The present invention preferably uses the IEEE-1394b databus due to its unique and specialized low latency, shared bandwidth characteristics.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: February 26, 2008
    Assignee: The Boeing Company
    Inventor: Gary A. Kinstler
  • Patent number: 7334151
    Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: February 19, 2008
    Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
    Inventors: Kenji Kubo, Wataru Tanaka, Hiroyuki Maemura
  • Patent number: 7327581
    Abstract: A circuit device includes plural semiconductor circuit devices that are formed on independent substrates, respectively, and communicate with each other. Each of the semiconductor circuit devices includes: plural modules of an identical type, functions of which are substitutable for one another; a module selecting unit that selects, among the plural modules, usable modules that are a part of the plural modules; and a circuit block including an interface unit for the modules selected by the module selecting unit to exchange signals with the other semiconductor circuit devices. A logic module included in one of the semiconductor circuit devices belongs to a different type, a function of which is not substitutable for a function of a logic module included in at least one of the other semiconductor circuit devices.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: February 5, 2008
    Assignee: Sony Corporation
    Inventor: Mutsuhiro Ohmori
  • Patent number: 7324231
    Abstract: The present invention is a computing system typically but not necessarily used in a printer, which includes a processor for managing operation of a print engine, expansion buses, and bridge devices between expansion buses. A bus bridge is described which can operate in an expansion bus environment. The bus bridge uses a nontransparent PCI bridge in a nonstandard manner to emulate a transparent bus bridge. Processes are included for detecting overall bus topology in the system and for creating configuration cycles on the secondary side of any bridge found.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: January 29, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Brett L. Davis, Daniel J. Martin
  • Patent number: 7321946
    Abstract: An apparatus comprises a first plug to couple the apparatus to a host connection and a second plug to couple the apparatus to a display connection. The apparatus further comprises a metallic transmission medium coupled to the first plug and link extender circuitry coupled to the metallic transmission medium and the second plug. The link extender circuitry including equalization circuitry coupled to the metallic transmission medium to restore voltage levels on signals transmitted on the metallic transmission medium, differential signaling receive circuitry coupled to the equalization circuitry; and differential signaling transmit circuitry coupled to the differential signaling receive circuitry and the second plug.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: January 22, 2008
    Assignee: InFocus Corporation
    Inventor: Jorell A. Olson
  • Patent number: 7320043
    Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: January 15, 2008
    Assignee: Avocent Huntsville Corporation
    Inventors: Remigius G. Shatas, Robert R. Asprey, Christopher L. Thomas, Greg O'Bryant, Greg Luterman, Jeffrey E. Choun
  • Patent number: 7319705
    Abstract: A high-speed serial ATA physical layer transmits data over a communications medium using a serial ATA protocol. A serial ATA control circuit controls operation of the serial ATA physical layer. A serial ATA multiplexer outputs a serial ATA signal and has a plurality of input lines for receiving input data and a control input that communicates with the serial ATA control circuit. A serial ATA analog front end includes a first differential driver that communicates with the serial ATA multiplexer and provides a first gain to the serial ATA signal and a serial ATA pre-emphasis circuit that provides pre-emphasis to the serial ATA signal to alter a transmission characteristic of the serial ATA signal.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: January 15, 2008
    Assignee: Marvell International Ltd.
    Inventors: Lei Wu, Timothy Hu
  • Patent number: 7315456
    Abstract: An enclosure for an input-output (IO) subsystem comprises: a backplane; a plurality of first slots for accepting corresponding IO option modules; a second slot for accepting an IO controller module; a plurality of first connectors corresponding to the plurality of first slots for connecting the corresponding IO option modules to the backplane; a second connector corresponding to the second slot for connecting the IO controller module to the backplane; and wherein the backplane includes communication links for interconnecting the second connector to each of the plurality of first connectors.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: January 1, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert M. Mondor, Jeffrey Michael Lewis, Stuart Allen Berke
  • Patent number: 7313680
    Abstract: One of the ground pins on a conventional floppy drive host connector is coupled to an input of a computer system and to a supply potential via a pull-up resistor. When a floppy drive is connected to the floppy drive host connector, the pin is pulled to ground by virtue of the ground connections within the floppy drive device. When a floppy drive is not connected to the floppy drive host connector, the pin remains at the supply potential. BIOS firmware or another system within the computer may detect the presence of the floppy drive by simply reading the value of the input.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 25, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Kyle, Greg P. Ziarnik
  • Publication number: 20070294460
    Abstract: A multi-layer universal serial bus (USB) input/output (I/O) system comprising a chipset, at least one USB port, and an I/O port. The chipset controls data transmission. The I/O control chip is coupled between the system chipset and the USB port. The chipset controls data transmission of the USB port through the I/O control chip.
    Type: Application
    Filed: December 14, 2006
    Publication date: December 20, 2007
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chao-Sheng Huang
  • Publication number: 20070294452
    Abstract: An external multimedia expansion device suitable for being electrically connected to a portable computer is provided. An express card is inserted into the portable computer, and the external multimedia expansion device is suitable for being electrically connected to the portable computer through the express card. The external multimedia expansion device includes a first circuit board and a transmitting cable. The first circuit board is suitable for being electrically connected to at least one processing unit, and to the express card through the transmitting cable. The transmitting cable is suitable for transmitting at least one of a high-speed signal and a universal serial bus (USB) signal, so that the performance of the portable computer can be enhanced through operating the processing unit. Since the external multimedia expansion device is suitable for transmitting the high-speed signal, the portable computer can enhance performance of its hardware through an external expansion card.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 20, 2007
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Nai-Wei Chiu, Yu-Liang Liu, Kuo-Chung Kao, Yu-Hsuan Lai
  • Patent number: 7307987
    Abstract: A payload module (202) includes a payload subunit (212) coupled to the payload module, where the payload module has one of a 3U form factor, a 6U form factor and a 9U form factor. At least one multi-gigabit connector (218) is coupled to a rear edge (219) of the payload module and to the payload subunit, where the at least one multi-gigabit connector is coupled to communicatively interface the payload subunit to a backplane (204), where the backplane includes a switched fabric (206) coincident with at least one of a VMEbus network and a PCI network, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload subunit through the at least one multi-gigabit connector.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 11, 2007
    Assignee: Motorola, Inc.
    Inventors: Robert C. Tufford, Jeffrey M. Harris, Douglas L. Sandy
  • Patent number: 7305038
    Abstract: A peripheral device includes a data port having high and low impedance terminations, a transmitter having a data signal generator and a receiver detector. The data signal generator is electrically coupled to the low impedance termination of the data port when in a low impedance operating mode, and to the high impedance termination when in a high impedance operating mode. The receiver detector includes a noise detector adapted to detect a presence or an absence of rail-to-rail noise at the data port when the transmitter is in the high impedance operating mode.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: December 4, 2007
    Assignee: LSI Corporation
    Inventors: Donald C. Grillo, Prashant Singh
  • Patent number: 7305506
    Abstract: A method, system, and connector interface for transferring status information between a media player and an accessory. The method includes determining, by the accessory, when a button event occurs; and transmitting, by the accessory, at least one button status command to the media player, where the one or more button status commands comprise a context-specific button status command and at least one command associated with a particular media type. According to the method and system disclosed herein, the media player and accessory may utilize a plurality of commands in a variety of environment such as within a connector interface system environment to facilitate the transfer of status information.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: December 4, 2007
    Assignee: Apple Inc.
    Inventors: Gregory T. Lydon, Lawrence G. Bolton, Emily C. Schubert, Jesse Dorogusker, Donald J. Novotney, John B. Filson, David Tupman
  • Patent number: 7295986
    Abstract: By installing a device control module (DCM), a functional component module (FCM), and a guarantee card FCM of a digital video cassette recorder (DVCR) into an integrated receiver decoder (IRD), the IRD is able to control the DVCR. The guarantee card FCM is used for accessing an electronic guarantee card stored in a non-volatile memory of the DVCR. The IRD stores purchase information or repair information of the DVCR into the non-volatile memory of the DVCR via an IEEE-1394 serial bus in response to an instruction from a requester. The IRD also reads the purchase information or the repair information from the non-volatile memory of the DVCR via the IEEE-1394 serial bus.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: November 13, 2007
    Assignee: Sony Corporation
    Inventor: Koichi Hayakawa
  • Patent number: 7293122
    Abstract: A connector interface system is disclosed. The connector interface system includes an interface and a protocol in communication with which allows a media player to communicate with external devices over a transport link. The protocol includes a core protocol functionality and a plurality of accessory lingoes. The accessory lingoes comprise a microphone lingo, a simple remote lingo, a display remote lingo, a RF transmitter lingo and an extended interface lingo.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 6, 2007
    Assignee: Apple Inc.
    Inventors: Emily C. Schubert, Wang Chun Leung, Gregory T. Lydon, Scott Krueger, Paul Holden, John Archibald, Lawrence G. Bolton, Donald J. Novotney, John B. Filson, David Tupman
  • Patent number: 7277971
    Abstract: A data processing apparatus comprising: (1) a plurality of data processing boards; (2) a bus connecting the boards with each other; and wherein each board comprises a communication utility for communicating data over the bus to another board through a plurality of channels, and wherein at least one of the channels has a user-redefinable configuration. For enhancing the user-definability of the apparatus, it is preferred that a user interface is provided through which the user can define one or more communication parameters.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: October 2, 2007
    Assignee: The Boeing Company
    Inventors: Albert F. Winkeler, III, Kirk D. Ellett
  • Patent number: 7275120
    Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 25, 2007
    Inventors: Michael Ou, Lyle E. Adams, Edward Yan
  • Patent number: 7269674
    Abstract: A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred from the controller to the expander and then to HDD. In this connection, the controller and the expander transfers a set of transfer data in a plurality of the HDD-side physical links. The controller-side physical link integrates the transfer data, and multiplexes them to transfer. A plurality of HDDs-side physical links separates the transfer data to transfer in parallel.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 11, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Chikusa, Satoru Yamaura, Toshio Tachibana, Takehiro Maki, Hirotaka Honma
  • Patent number: 7269691
    Abstract: A device for managing removable storage media includes a first management unit and a control unit. The first management unit is adapted to update first media management information which is held in said device and which includes at least a first datum that is used to detect that one removable storage medium has been replaced with a second removable storage medium, when the second removable storage medium is connected to said device, the first datum being information other than a user-input password. The control unit is adapted to test a command from an external device for consistency with the first datum and to execute the command if the first datum is consistent with second media management information contained in the command.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: September 11, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinji Onishi
  • Patent number: 7262961
    Abstract: According to one embodiment, an information processing apparatus includes, a body, a bay portion provided in the body and in which a one of a first device having a first relay board and a second device having a second relay board is removably inserted, a first controller which communicates with the first device, a second controller which communicates with the second device, and a connector provided in the bay portion and connected to the first relay board or the second relay board, and including a plurality of first signal pins connected to the first controller via a first bus, a plurality of second signal pins connected to the second controller via a second bus, two ground pins connected to a common ground, a first power supply pins and a second power supply pins, and one of the second signal pins locates between the two ground pins.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: August 28, 2007
    Inventors: Hironori Motoe, Shingo Koide, Daisuke Maehara
  • Patent number: 7257659
    Abstract: According to embodiments of the present invention, indicators on a PCI/PCI-X controlled by a Standard Hot-Plug Controller (SHPC) have non-fifty percent duty cycle blinking patterns that communicate to an operator a particular command being processed, whether the command was processed successfully, whether a “hard” or “soft” error occurred if the command was processed successfully, and whether power was applied to the slot if the command was not processed successfully.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Peter N. Martin, Buck W. Gremel
  • Publication number: 20070180181
    Abstract: A USB interface provided with USB host/device function and its control method is disclosed. The USB interface includes a control unit, a USB host, a USB device, a memory, a port router and a plurality of connection ports. The control unit is used to define the connection ports to be either an upstream port or downstream port. It also controls signal flows within the USB control interface. The signal flows are provided for the USB host and the USB device. The memory is used to store data during the operation of the USB control interface. The USB host is coupled to an external device via the port router, and the USB device is coupled to an external host via the port router.
    Type: Application
    Filed: January 25, 2007
    Publication date: August 2, 2007
    Inventors: Po-Ching Chen, Yun-Kuo Lee
  • Patent number: 7251701
    Abstract: A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred from the controller to the expander and then to HDD. In this connection, the controller and the expander transfers a set of transfer data in a plurality of the HDD-side physical links. The controller-side physical link integrates the transfer data, and multiplexes them to transfer. A plurality of HDDs-side physical links separates the transfer data to transfer in parallel.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: July 31, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Chikusa, Satoru Yamaura, Toshio Tachibana, Takehiro Maki, Hirotaka Honma
  • Patent number: 7242109
    Abstract: The invention relates to a bus system comprising a bus line, to which electronic devices (26–36) can be connected. According to the invention, at least one electronic device (36) can be connected via a detachable interface (38) to the bus line, said interface (38) having a first connection (42) that is connected to a first section (12) of the bus line and a second connection (44) that is connected to a second section (14) of the bus line. To prevent an interruption of the bus line when the interface (38) is free, a bypass device (40) automatically creates a connection between the first section (12) of the bus line and the second section (14) of the bus line, if no electronic device (36) is connected to the interface (38).
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: July 10, 2007
    Assignee: John Deere Fabriek Horst B.V.
    Inventor: Joseph M. H. Beeren
  • Patent number: 7237054
    Abstract: In an external disk drive system comprising a disk drive, a bridge controller comprising a plurality of Bridge Controller Host (BCH) interfaces adapted to establish communication between the external disk drive system and an external device via a plurality of different communication mediums, a method for switching from a first BCH-interface communicating with the external device via a first communication medium to a second BCH-interface during the operation of the external disk drive system. The method comprising sensing a connecting of a second communication medium to the external disk drive system via the second BCH-interface; determining an interface priority of the second communication medium over an interface priority of the first communication medium; dismounting the disk drive from the first communication medium based on the determining; and mounting the disk drive to the second communication medium wherein the external disk drive system remains operational during the dismounting an mounting.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 26, 2007
    Assignee: Western Digital Technologies, Inc.
    Inventors: William C. Cain, Barry L. Klein, Kevin W. McLaughlin
  • Patent number: 7234031
    Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines, and includes a non-volatile memory, a command packet decoder, and a control unit, such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-
    Type: Grant
    Filed: June 12, 2004
    Date of Patent: June 19, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-kyoon Yim, Sang-kil Lee
  • Patent number: 7228265
    Abstract: A method and system of emulating serial com port communication. A computer processing system has computer-executable operating system instructions including first instructions that interact with a first serial device according to a predefined input/output (I/O) hardware interface. A first serial device has a receive port and a transmit port and has the predefined (I/O) hardware interface. A second serial device has a receive port and a transmit port. The transmit port of the first serial device is in serial communication with the receive port of the second serial device, and the receive port of the first serial device is in serial communication with the transmit port of the second serial device. Computer-executable instructions emulate serial communication port device communication and include instructions that transmit information over another medium in response to receive requests from the second serial device.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: June 5, 2007
    Assignee: Egenera, Inc.
    Inventors: Neil Haley, Justin Maynard
  • Patent number: 7228366
    Abstract: A method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule are disclosed herein. A work item is removed from an enabled expansion bus schedule data structure and a coherency signal is then generated utilizing an expansion bus host controller. The work item is then reclaimed in response to the generation of the coherency signal. In one embodiment, the enabled expansion bus schedule data structure is a Universal Serial Bus (USB) asynchronous schedule including a plurality of queue heads.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Darren L. Abramson, John S. Howard
  • Patent number: 7228374
    Abstract: A data transmission system is described that connects a controller with drives in machine tools and production machines. The controller can be connected via an internal data bus with at least one internal drive, wherein the same data bus profiles are used for the internal data bus as for an external data bus. A user then sees the same data interface both for a central control topology and a drive-based control topology. This allows the user to readily interchange the two topologies and port existing applications to the various control topologies.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 5, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Hammer, Gerhard Heinemann, Martin Kiesel, Rolf-Dieter Pavlik, Guido Seeger
  • Patent number: 7221261
    Abstract: A system and method indicates the configuration of power to be provided over Ethernet cabling.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 22, 2007
    Assignee: Vernier Networks, Inc.
    Inventors: James B Klingensmith, Brent Dimick, Elton Armstrong
  • Patent number: 7222210
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: May 22, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 7219180
    Abstract: A system and apparatus providing power management and legacy support. An uninterruptable power supply is combined with a bus control module. The bus control module provides legacy support through a single connectivity. The bus control module monitors and controls power distribution within the system. A bus hub unit is coupled to the bus control module and provides a plurality of ports to which bus functions may be coupled.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: May 15, 2007
    Assignee: Digi International Inc.
    Inventor: Andrew Frank