Abstract: A system includes a device, a device driver associated with the device, and an operating system (OS). The OS is configured to receive, from the device driver, a testing address to a register, obtain a testing value associated with the testing address, receive a memory read request, read device memory associated with the memory read request to obtain a value, and compare the value to an error pattern to determine a first status of the memory read as one of matching and mismatching the error pattern. Responsive to determining the first status as matching, the operating system is further configured to read the testing address to determine a second status of the testing value as one of matching and mismatching the error pattern. Responsive to determining the second status as matching, the operating system is configured to return an error to the device driver.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: An advanced PCI express board assembly is mountable in a PCI express slot. The assembly includes a main board that is attached to an adapter board by a connector section that includes mechanical and electrical connectors. When the main board is attached to the adapter board, the plane defined by the main board is parallel to, and laterally offset from, the plane defined by the adapter board. The adapter board is connectable to a female PCI express connector in the PCI slot. When the adapter board is connected to the female PCI express connector, the main board plane is perpendicular to the motherboard and is laterally offset from the PCI express slot. More and larger components can be placed on the main board while the assembly remains within the reserved PCI express space.

Abstract: A simulation switching device of computer control chips is disclosed, including an addin card body, a plurality of computer control chips having different operation frequencies arranged on the addin card body, a graphics processing device in information connection with each of the computer control chips, an operation control device in information connection with each of the computer control chips and the graphics processing device, and an inspection module in information connection with the operation control device. To use, the operation control device detects a voltage of the graphics processing device. If the voltage is in an unstable condition, then the inspection module performs simulation to inspect a condition that will be generated by driving another one of the computer control chips that has a relatively high operation frequency, and automatic switching is made to the computer control chip having the relatively high operation frequency to make the voltage stable.

Abstract: A modular embedded controller includes an enclosure with an external interface, a generic motherboard, and an external device-specific input/output daughterboard. The generic motherboard has a supervisory processor and a plurality of daughterboard seats and is supported in the enclosure. The external device-specific input/output daughterboard is supported in one of the daughterboard seats, connects the external interface to the motherboard supervisory processor, and has an input/output processor translate data communicated between the motherboard supervisory processor and a device connected to the external interface. Embedded engine controllers and gas turbine engines with embedded controllers are also described.

Abstract: A connectivity card insertable into a connector of a host system is provided. The connectivity card includes a plurality of Peripheral Component Interconnect Express (PCIe) connectors configured to provide external PCIe ports on the connectivity card, each of the plurality of PCIe connectors capable of carrying PCIe traffic. The connectivity card also includes a PCIe switch circuit configured to communicatively couple the plurality of connectors to a shared connectivity interface carried over a host connector of the connectivity card. The connectivity card further includes control circuitry configured to monitor for connectivity issues that arise with regard to the plurality of PCIe connectors, and responsively mitigate the connectivity issues by at least reconfiguring a communication pathway in the PCIe switch circuit for at least a portion of the PCIe traffic affected by the connectivity issues.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: A method of managing memory descriptors for a plurality of commands to a non-volatile semiconductor storage device includes requesting memory descriptors from a host system for each of the plurality of commands stored in a first memory, storing the memory descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a second memory of the non-volatile semiconductor storage device, and maintaining a dynamic descriptor list in the second memory for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the second memory having associated memory descriptors. At least one of the occupied descriptor regions includes multiple memory descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.

Abstract: Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable memory. A front end processor connected to a Peripheral Component Interconnect Express (PCIe) switch performs as a front end interface to the block addressable I/O device to emulate byte addressability. A PCIe device, such as a graphics processing unit (GPU), can directly access the necessary bytes via the front end processor from the block addressable I/O device. The PCIe compatible devices can access data from the block I/O devices without having to go through system memory and a host processor. In an implementation, a system can include block addressable I/O, byte addressable I/O and hybrids thereof which support direct access to byte addressable memory by the host processor, GPU and any other PCIe compatible device.

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.

Abstract: A service redirect operation mode allows a tester device to perform software burn-in, firmware upgrade, and other related device interrogation via a USB Type-C connection. The service redirect operation mode is implemented by modifying a termination state of the configuration channel pins of the USB Type-C receptacle of the device under test. Software and/or hardware executing on the device under test re-configure the resistive arrangement of the configuration channel pins, causing one pin to be connected to a reference voltage via a pull-up resistor and the other pin to be connected to ground via a pull-down resistor. When operating in the service redirect operating mode, two additional signal lines of the USB Type-C receptacles may be used to exchange information between the tester and the device under test using a user-specified interface protocol.

Abstract: The electronic system according to the invention comprises a set of electronic devices, each electronic device comprising a memory and a communication module for communicating with one or more other devices of the set. This electronic system comprises a module for verifying the compatibility of each device with the other complementary device(s) with which said device is adapted to communicate, and a module for generating at least one deviation indicator when an incompatibility is detected between two devices. The memory comprises a compatibility table with said other complementary device(s), each compatibility table comprising a minimum required version number for each of the other complementary devices, and each verification module is adapted for comparing a version number of each other complementary devices with the minimum required version number.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

Abstract: A method of improving throughput of a secure digital (SD) bus is described. The method includes accessing, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command. The method also includes reading a read packet over the data lines of the SD bus from the SD client with a second SD direct command. The method further includes storing the read packet in a host buffer allocated according to the read metadata.

Abstract: The present disclosure provides an operation instruction response control method and terminal for a human-machine interface. An operation instruction is compared with an operation instruction at the tail of an operation instruction queue while the human-machine interface is in a busy state, and stored in the operation instruction queue while the operation instruction is inequivalent to the operation instruction at the tail of the operation instruction queue; the operation instruction is stored in the operation instruction queue directly while the human-machine interface is not in the busy state. The present disclosure is capable of keeping receiving operation instructions while the human-machine interface is busy, and filtering out invalid operation instructions to avoid the backlog, which shortens the delay time of the response to the operation instructions.

Abstract: A data access method and a related apparatus and system, where the data access method includes receiving, by a non-volatile memory express (NVMe) from a processor, a first key-value command whose format meets an NVMe interface standard, where the first key-value command carries a first operation manner indicator and a first operation object type indicator, and an operation object type indicated by the first operation object type indicator includes a value, obtaining, by the NVMe, N keys corresponding to the first key-value command, and performing, by the NVMe on a value corresponding to each of the N keys, an operation indicated by the first operation manner indicator. Hence, the data access method is helpful in promoting a data access manner in an NVMe technology.

Abstract: A data processing device has a communicator that receives, from a data overwriter, first device-specific information that identifies one of the plural same-ID data processing devices as a data overwrite object device having data to be overwritten by the data overwriter. Then, a device-specific information generator in the data processing device generates second device-specific information that is used to determine whether a subject data processing device is the data overwrite object device. Then, a specifier in the subject data processing device specifies that (i) the subject data processing device is the data overwrite object device or (ii) one of other plural same-ID data processing devices other than the subject data processing device is the data overwrite object device, based on a matching between (a) the first device-specific information received from the data overwriter, and (b) the second device-specific information generated by the device-specific information generator.

Abstract: This start limiting device (1) is provided with a start prohibiting means (11) which prohibits starting a device (2) when movement of said device (2) is detected, and a start prohibition releasing means (14) which releases the prohibition by the start prohibiting means (11) on starting the device (2); when movement of said device (2) is detected, the start prohibiting means (11) prohibits starting the device (2) such that the prohibition on starting the device can be released by the start prohibition releasing means (14). This start limiting device (1) is provided with a command receiving means (12) which receives a prescribed command, and the start prohibition releasing means (14) is configured to release the prohibition on starting the device until it is determined that a prescribed time condition has been satisfied from the time that the command receiving means (12) receives the aforementioned command.

Abstract: The disclosure relates to access relationships, more particularly to controlling access relationships between entities in a computerized system. In the disclose arrangement a first access relationship between a first entity and a second entity is determined. At least one intermediate entity is selected for routing of a second access relationship between the first entity and the second entity via the at least one intermediate entity. The second access relationship is created, the second access relationship comprising a chain of access relationships via the first entity, the at least one intermediate entity and the second entity.

Abstract: The present invention discloses an intermediate circuit including: a detection circuit generating a detection result indicating a memory card signal conforming to one of a first and a second voltage specifications which specify a higher first operation voltage and a lower second operation voltage respectively; a control circuit generating a conversion control signal and a selection control signal according to the detection result; a conversion circuit converting the memory card signal into a card-to-system conversion signal conforming to the second voltage specification according to the conversion control signal when the memory card signal conforms to the first voltage specification; and a selection circuit outputting the card-to-system conversion signal according to the selection control signal when the memory card signal conforms to the first voltage specification, and outputting the memory card signal according to the selection control signal when the memory card signal conforms to the second voltage speci

Abstract: The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.

Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.

Abstract: A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.

Abstract: An information handling system includes a host processing complex and a wireless management system. The host processing complex instantiates a hosted processing environment and includes a first general-purpose processing unit (GPU) and a GPU hot-plug module that enables a hot-plug operation to replace the first GPU with a second GPU while power is provided to the host processing complex. The hosted processing environment instantiates a first workload on the first GPU. The wireless management system operates out of band from the hosted processing environment, directs the hosted processing environment to halt the first workload, and directs the GPU hot-plug module to perform the hot-plug operation.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

Abstract: Examples of adapters for transmitting signals are disclosed. In one example implementation according to aspects of the present disclosure, an adapter may include a first connector communicatively couplable to PCIe port of a computing system via a first plurality of pins and a second connecter communicatively couplable to an electronic device via a second plurality of pins. The first plurality of pins is communicatively coupled to the second plurality of pins. Additionally, signals of a first type are transmittable between the computing system and the electronic device via a first subset of the first and the second pluralities of pins and signals of a second type are transmittable between the computing system and the electronic device via a second subset of the first and the second pluralities of pins. The second subset of the first plurality of pins and the second plurality of pins conforms to the SFF 8639 standard.

Abstract: Systems and methods are disclosed for configuring multi-line serial computer expansion bus communication links. A controller for a data storage device may receive one or more signals indicative of bifurcation settings from a configuration component or a host bus adapter may provide one or more signals indicative of bifurcation settings to the controller. The controller may receive configuration data from the BIOS based on the one or more signals and may configure the multi-line serial computer expansion bus communication links based on the configuration data.

Abstract: A risk assessment system and method are provided that may be implemented as an embedded hardware based system and method that provide real-time pre-trade risk assessments for multiple parties, in addition to real-time market data and trading connectivity to a variety of liquidity venues. The liquidity venues may include regulated exchanges, ECNs and other financial institutions listing securities, options, futures, commodities, foreign exchange and other financial instruments.

Abstract: A method for a power receiver for protecting a power receiver from being taken without permission while charged wirelessly includes receiving wireless power from a power transmitter and performing wireless charging in a security mode by the power receiver; detecting whether the wireless charging is interrupted without receiving a security code for authorization; and starting a protection function if the power receiver detects that the wireless charging is interrupted without receiving the security code for authorization.

Abstract: A network. At least some embodiments are a network including a first root node connected to a first port of a first switch and a second root node connected to a first port of a second switch. A first link is connected to a second port of the first switch and connected to a second port of the second switch. A second link is connected to a third port of a first switch and connected to a third port of the second switch.

Abstract: An information processing apparatus includes: a communication unit that performs communication with a power supply controller controlling supply and shutoff of power supply of a device; an operation receiving unit that receives input of user operation; an instructing unit that instructs the power supply controller via the communication unit to supply or shut off power supply in response to user operation concerning supply or shutoff of power supply of the device; a setting unit that sets power supply specified to be not permitted to shut off in response to user operation to specify the power supply to be not permitted to shut off; and an instruction disabling unit that disables an instruction to shut off power supply by the instructing unit when the power supply set to be not permitted to shut off is a target of the instruction to shut off power supply by the instructing unit.

Abstract: A transceiver-receiving system, such as a network switch with pluggable transceivers, is built with hardware and machine logic so that power to certain components is turned off when the pluggable transceiver is not present in its plug in slot. The machine logic for handling the turning off an on of power is present on a processor on the board to which the plug-in slot is attached. The other hardware for handling the turning on and off of the power includes a communication line from the plug-in slot to the processor, and a set of switch(es) located on the power path for the component(s) to be turned on and off according to the presence of absence of the transceiver.

Abstract: Embodiments of the present invention provide a docking station and an external device control method and system utilizing the docking station, which are capable of implementing simultaneous working of devices of two types of protocols through a same multiplexing interface. The external device control method includes: utilizing a docking station, where the docking station includes: a first protocol/second protocol multiplexing interface for connecting to a main device; at least one first protocol device interface for connecting to a first protocol external device; and at least one second protocol device interface for connecting to a second protocol external device. The method is: receiving first protocol data sent by the first protocol external device through the first protocol device interface; and converting the first protocol data into second protocol data, and sending the second protocol data to the main device through the first protocol/second protocol multiplexing interface.

Abstract: Memory card adapters and/or a memory apparatuses may be provided. For example, a memory card adapter including a main housing section that corresponds to a memory card socket of a first standard, the main housing section including a card housing section, the card housing section configured to house a memory card of a second standard different from the first standard therein, a first surface of the main housing section defining a through-hole, the through-hole configured to expose a connection pin of the memory card to be housed in the housing section to an outside of the housing section, and a second surface of the main housing section defining a card insertion hole, the second surface being different from the first surface, the card insertion hole configured to receive the memory card into the card housing section may be provided.

Abstract: An image sensor including an optoelectronic conversion circuit, a read circuit, a timing control and a serial interface is provided. The optoelectronic conversion circuit is configured to store a charge amount. The read circuit is coupled to the optoelectronic conversion circuit via a bit line. The timing control is configured to send at least one control signal to control the optoelectronic conversion circuit to store the charge amount and control the read circuit to read the charge amount stored in the optoelectronic conversion circuit. The serial interface is coupled to the timing control and configured to send a trigger signal to the timing control to activate the timing control to send the at least one control signal.

Abstract: Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. Additional apparatus and methods are disclosed.

Abstract: An integrated input control and output rendering system for a processor-driven user device is provided. The system integrates input sensors (such as a keyboard, mouse, touchpad, camera, etc.) and output actuators (such as a display panel, speaker, robot, etc.) into a device independently of the user device and the applications running on the user device. The system includes an input logic engine to interpret input signals from various input devices together with an output rendering engine to output appropriate output signals in response to the input signals.

Abstract: The disclosed method includes, at a storage controller of a storage system, receiving host instructions to modify configuration settings corresponding to a first memory portion of a plurality of memory portions. The method includes, in response to receiving the host instructions to modify the configuration settings, identifying the first memory portion from the host instructions and modifying the configuration settings corresponding to the first memory portion, in accordance with the host instructions. The method includes, after modifying the configuration settings corresponding to the first memory portion, sending one or more commands to perform memory operations having one or more physical addresses corresponding to the first memory portion and receiving a failure notification indicating failed performance of at least a first memory operation of the one or more memory operations. The method includes, in response to receiving the failure notification, executing one or more error recovery mechanisms.

Abstract: An interface switching control method, a portable terminal and a portable mobile device using the method are disclosed. The method is applied in a portable terminal including a first device and a second device. The first device is connected to a shared device via a first interface, and the second device is connected to the shared device via a second interface. The portable terminal has a first state in which the first device and the second device are connected, and a second state in which the first device and the second device are disconnected. The method includes detecting a state of the portable terminal; and when the detection result indicates that the portable terminal is in the first state, controlling the first interface to be in an enabled state and controlling the second interface to be in a disabled state. The method achieves a real-time switching control over the interfaces for the shard device, and optimizes the interface control for the hybrid-system portable terminal.

Abstract: The present invention provides a data migration method and apparatus, where the method includes: after a second control board is inserted into a second control board slot, receiving, by a first control board, type information from the second control board, and determining whether the type information of the second control board and type information of the first control board are the same; and when determining that the type information of the second control board and the type information of the first control board are different, sending, by the first control board, configuration data stored by the first control board itself to the second control board, so that the second control board utilizes the configuration data to perform a configuration.

Abstract: A removable device is removably attachable to an image forming apparatus main body. The removable device includes an information storage device, a holder, and a low frictional structure. The information storage device includes: an information storage unit that stores information to be communicated between the apparatus main body and the removable device; a terminal to be contacted with an apparatus main-body terminal, for communicating information with the apparatus main body; and a substrate that holds the information storage unit and the terminal and that includes a guide to be fitted to a protrusion provided on the apparatus main body. The holder holds the substrate such that the substrate can move, when the removable device approaches the apparatus main-body terminal, on a virtual plane intersecting with a moving direction of the removable device. The low frictional structure is arranged on a contact area between the substrate and the holder.

Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Abstract: A low cost, energy monitoring system comprises a plurality of remote sensors for monitoring energy consumption in specific circuits, or by specific appliances, a adapter that communicates with the remote sensors over a wireless network, and a host device with a display. The remote sensors monitor energy consumption in specific circuits, or by specific appliances, and report the energy consumption by the monitored circuits or appliances to the remote adapter. The adapter stores the energy consumption data in memory and generates output images for display by the host device. The output images are based on display templates stored in the memory of the adapter and define how the energy consumption data is formatted and displayed for the user.

Abstract: An all-in-one SATA interface storage device comprising: an interface board installed on a motherboard; a first memory card slot which is a CFast slot fixed on the interface board for installation of a CFast card; a second memory card slot fixed on the interface board and available to CF-SATA and CFEX cards for installation of either a CF-SATA card or a CFEX card. As such, the present invention facilitates applications of multiple storage devices via its SATA interfaces linking a host system, providing a user more convenient new storage devices, and creating higher value-added services by lowering costs.

Abstract: A flash drive includes a storage module, a switching module, and a transforming mechanism. The storage module has a storage unit and a first interface electrically connected to each other. The switching module has a second interface and a third interface which are in different types but are electrically connected to each other, and the first interface corresponds to the second interface. The transforming mechanism is located at a first position or a second position relative to the storage module, and the switching module is located in the transforming mechanism. When the transforming mechanism is located at the first position, the first interface is electrically connected to the second interface, so that the storage unit is electrically connected to a host through the third interface. When the transforming mechanism is located at the second position, the first interface of the storage unit is electrically connected to the host.

Abstract: A removable tray integrated smart card and a mobile terminal adopting the same are provided. The smart card includes: a case configured to be removable into/from a smart card insertion slot of a mobile terminal; and a secure element provided in the case, wherein the case is removable into/from the smart card insertion slot without being placed on a tray. Accordingly, the smart card such as a USIM-card can be inserted into the mobile terminal without using the tray. In addition, since the size of the smart card increases as the smart card is unified with the tray, many high performance antennas and wireless modules can be inserted into the smart card and thus wireless communication performance of the smart card can be enhanced.

Abstract: Examples may include receiving, at a switch, an Ethernet frame having an Ethernet header that may indicate the Ethernet frame includes a network controller sideband interface (NC-SI) control packet from a management controller at a compute node coupled to the switch. In some examples, a response to a command included in a received NC-SI control packet that was encapsulated in an Ethernet frame may be processed at the switch and sent to the management controller.

Abstract: A computer server rack for mechanically supporting and electrically powering computer servers is provided. The rack includes DC-to-DC conversion circuits which are configured to convert a relatively high DC facility voltage (e.g. 380 volts DC provided throughout a data center on busways and/or appropriate wiring) to DC voltage useable directly by a computer server (e.g. 12 volts DC). The conversion circuits are highly efficient and convert substantially all of power input to the circuits at the input voltage and input DC current to a high DC output current at a lower output voltage.

Abstract: A distributed switchless system characterized by full mesh connectivity is disclosed. The full mesh distributed switchless system allows direct and indirect communication between a source node and a destination node. In direct communication, data propagates via links connecting the source and destination nodes. In indirect communication, data is first sent to an intermediate node via links connecting the source and intermediate nodes. The intermediate node sends the data to the destination node via links connecting the intermediate node and the destination node. The traffic can be divided into all available links across the nodes, rather than only the links connecting the source and destination nodes. Because indirect communication uses more links compared to direct communication, the traffic in each link is smaller. Consequently, the switchless distributed interconnect system can operate with fewer links between any two nodes and links with smaller bandwidth.

Abstract: An information processing apparatus includes an interface configured to be connected with a connection apparatus, an acquisition unit configured to acquire apparatus information including a configuration or an operation specification of the connection apparatus connected with the interface, a determination unit configured to determine a control program to control the connection apparatus according to the apparatus information, and a control unit configured to use the determined control program to control the connection apparatus, wherein the connection apparatus includes an expansion connection unit and an expansion apparatus connected with the expansion connection unit, and the acquisition unit includes a first acquisition unit configured to acquire first information including a configuration or an operation specification of the expansion connection unit connected with the interface, and a second acquisition unit configured to acquire second information including a configuration or an operation specification