Abstract: A communication system, a communication apparatus, and an electronic appliance are provide. The communication system, a communication apparatus and an electronic appliance can operate at a high data transfer rate without raising the frequency of the data transfer clock. In a communication apparatus, which is a card-shaped semiconductor memory apparatus, eleventh, twelfth, thirteenth and fourteenth belt-like terminals T (T11, T12, T13 and T14) are provided in addition to the third, fourth, fifth and seventh belt-like terminals T (T3, T4, T5 and T7) arranged at an end of the cabinet as terminals for transmitting data to and receiving data from a digital still camera. With this arrangement, the number of terminals that can be used for exchanging data with the digital still camera is increased from four to eight to make it possible to improve the data transfer rate without raising the frequency of the data transfer clock.

Abstract: A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.

Abstract: The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

Abstract: PCI Express bus utilization is monitored for one or more predetermined thresholds to adjust the width of the bus in accordance with the utilization to provide power savings with minimal impact on performance. For instance, a performance monitor of a graphics controller tracks bus utilization with registers to adjust bus width between one, eight and sixteen lanes. Reduced numbers of active lanes are used at low utilization, such as one lane when a desktop graphic is presented on the display, increased numbers of active lanes are used at moderate utilization, such as eight lanes when a video image is presented on the display, and all lanes are active at high utilization, such as for presentation of three dimensional images.

Abstract: A device (e.g., an ultra-wideband device) is added to a system including a legacy wired bus (e.g., a MIL-STD 1553 bus). The legacy bus has a legacy bus signal with a center frequency, and the device has a carrier signal with a frequency that is substantially higher than the center frequency. Adding the device to the system includes coupling the device to the bus, and adding equipment for superimposing the device carrier signal on the legacy bus signal.

Abstract: A method for link bandwidth management between two devices in communication through a bandwidth-adjustable bus in a computer system determines which of a speed negotiation priority and a width negotiation priority is higher when the change condition is activated. An original width of the bus is changed to a target width first while remaining an original speed of the bus unchanged when the width negotiation priority is higher, and then optionally changing the original speed to a target speed. On the other hand, an original speed of the bus is changed to the target speed first while remaining the original width of the bus unchanged when the speed negotiation priority is higher, and then optionally changing the original width to the target width. The bus operates at a target bandwidth with the target width and the target speed without disabling the link state or powering down the computer system.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array. The interconnects and/or data processing elements may be synchronous or asynchronous. The data processing elements may operate in a fixed manner, or they may be programmable, and selectable data processing elements in the array may be bypassed. The interconnects and data processing elements may be configured to handle data in a digit-serial manner, with tags for each digit identifying whether the digit is the first and/or last digit in a data word. The data processing elements may be coupled to a system bus that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements.

Abstract: A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device.

Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.

Abstract: An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.

Abstract: A method for dynamically allocating lanes to a plurality of PCI Express connectors is disclosed that may comprise identifying whether a PCI Express device is installed into each PCI Express connector, identifying historic data traffic for each PCI device installed into the plurality of PCI Express connectors, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. The method may also comprise identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors. Moreover, the method may comprise creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors. Furthermore, the method may comprise receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors.

Abstract: A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.

Abstract: Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i?l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i?1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

Abstract: A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.

Abstract: A method for link bandwidth management between two devices in communication through a bus in a computer system. Whether a change condition of the bus having a link is activated is monitored. Change a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated. The bus will operate at the target bandwidth without disabling the link or powering down the computer system if subsequent failure speed management and unreliable speed management have passed.

Abstract: A dynamic lane management system comprises at least one downstream device of a computer system configured to dynamically initiate a lane width re-negotiation operation with at least one upstream device of the computer system in response to a detection of at least one power-related event associated with the computer system.

Abstract: A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of a first PCI-E slot with large lane width and a second PCI-E slot with small lane width in a computer system, to determine whether the first and second PCI-E slots hold any inserted expansion card; if the detection module detects an inserted expansion card in the first PCI-E slot rather than the second PCI-E slot, a switch control signal output is generated, to control the switch operation performed by the switch module, that is, transferring lane availability from the second PCI-E slot to the first PCI-E slot, with a view to enhancing the use of PCI-E lanes, speeding up data transmission, and overcoming a known drawback of PCI-E buses, that is, inflexible design.

Abstract: A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts within the PCI Express connector is connected to the PCI Express controller while the other contacts are opened.

Abstract: A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of four beats during each of four consecutive cycles of the bus clock. The data signal group may include multiple data strobes, such as first and second data strobes for latching first and third doublewords and third and fourth data strobes for latching second and fourth doublewords during each cycle of the bus clock. Each doubleword may be provided on first and second data portions of the data signal group. The first and second data strobes may latch data on the first data portion and the third and fourth data strobes may latch data on the second data portion.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus.

Abstract: A mechanism is provided for selecting IDLE patterns based on data being transmitted on the different ports of a wide lane serial attached small computer system interface cable. The mechanism examines the frequency content of the data bearing lanes and selects a DWORD to transmit for an IDLE that has a different frequency content to reduce spikes in electromagnetic interference emissions at a given frequency.

Abstract: Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

Abstract: Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes).

Abstract: A method for communicating between a first bus and a second bus is disclosed. The method generally includes the steps of (A) recognizing a read operation code in a read frame (i) received from the first bus and (ii) communicated with a first-bus protocol, (B) initiating a read transaction on the second bus using a second-bus protocol different than the first-bus protocol, wherein the initiating occurs earlier than a turn around time in the first-bus protocol that provides a plurality of bit times to respond to the read operation code and (C) transmitting read data received from the second bus on the first bus immediately after the turn around time.

Abstract: A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a write merge system (200), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (220 and 221), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of the data. A value representative of at least the number of buffers that are nearly empty of data as compared to a predetermined threshold is determined, and the transmission rate of the input path is adjusted according to the value. Preferably, the buffers are display pipes provided in a graphics controller IC for interfacing between one or more hosts and a graphics display device.

Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines and includes a non-volatile memory, a command packet decoder, and a control unit such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-vo

Abstract: Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port and use a configurable physical layer on the host. These configurable lanes pass through an external switch or crossbar that connects the lanes from the host to one or more of the slots. The direct-connect lanes can be the first lanes to a slot while the configurable lanes are the higher-numbered lanes.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: A digital television system, a memory controller, and a method for data access are provided. The digital television system comprises a memory and the memory controller. The memory controller writes a data packet to or reads a data packet from the memory. The memory controller comprises a register, a data packet adjuster, a burst length determination unit, and a frequency determination unit. The register sets a data bus width. The data packet adjuster adjusts the data packet according to the data bus width. The burst length determination unit determines a burst length according to the data bus width. The frequency determination unit determines an operating frequency of the memory controller according to the data bus width. The memory controller writes or reads the adjusted data packet in response to the burst length and the operating frequency.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Abstract: In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines connected to a bus master unit and bus slave unit. The control command lines of the buses are connected to a common control command bus to control command information on the buses. The data lines of the buses are connected via a data conversion unit to perform bit width conversion between the buses. An arbitration circuit is provided to perform arbitration of bus right for the buses in response arbitration request. Upon transfer of data between the buses, by obtaining of bus right by sender side bus, write access and rear access between buses is performed.

Abstract: A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.

Abstract: A first internal resource has a first register which is accessible from an external bus via an internal bus and has a same data width as that of the internal bus which is larger than that of the external bus. A second internal resource has a second register which has a same data width as that of the external bus and is accessible from the external bus via the internal bus. A bus interface circuit implements a data transmitting operation between the external bus and the internal bus. The bus interface circuit is constituted of a write buffer and a read buffer which have a same data width as that of the external bus and are accessible from the external bus.

Abstract: Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.

Abstract: An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible in different device and circuit configurations.

Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.

Abstract: Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Abstract: A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.