Abstract: A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.

Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Abstract: Method, apparatus, and computer program products for dynamically allocating lanes to a plurality of PCI Express connectors are disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. Dynamically allocating lanes to a plurality of PCI Express connectors may also include identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors.

Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.

Abstract: A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.

Abstract: An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of isochronous channels. The isochronous data pipe is a programmable sequencer that operates on the stream of isochronous data as it passes through the isochronous data pipe. The isochronous data pipe is programmed by an application to perform specific operations on the stream of data before the data is either transmitted across the bus structure or sent to the application, thereby pre-processing and manipulating the data before it is delivered to its destination. The operations are performed on both the packet header and the data field of the data packet. The isochronous data pipe can be stopped and started on the occurrence of specific events.

Abstract: A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile register (NVR) data from the EEPROM (or MCU) via the I2C bus, the module causes an I2C interface circuit of the PHY unit to forcedly toggle and send a clock signal to the EEPROM (or MCU) via the I2C bus to make the EEPROM (or MCU) recognize that interrupted communications via the I2C bus are pseudo completed.

Abstract: A home-control platform and architecture includes a plurality of serial buses that provide communications among processing devices that are connected to the home-control platform. A bus control unit is configured to allocate the buses among the devices that request communications services. The platform supports one or more control processors that provide an interface to legacy devices, user and network interfaces, browsers, and the like. The platform also accepts optional plug-in cards that perform as coprocessors for specific tasks, such as MPEG encoding and decoding, signal processing, video and audio CODECs, and so on. The software architecture employed to support this platform includes the use of a real-time microkernel Operating System (OS) at the control processors that interfaces with the task coprocessors, and interfaces with a standard OS, such as Vxworks, WinCE, or LINUX.

Abstract: A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.

Abstract: The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer. A system bus control apparatus includes a system bus that is a path of data transferred from a bus master, a bus condition monitoring section that monitors a used condition or unused condition of the system bus, a bus allocating section that allocates a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request, and a bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width. Accordingly, the bus width of the data to be transferred is changed in accordance with the bus width permitted to be used, whereby the transfer request is not brought into a stand-by condition.

Abstract: Several local IEEE1394 buses are bridged together over a second bus type to create a global bus wherein each local bus node is able to address nodes across the global bus without the local nodes being aware of the bridging operation. A bridging device operates by translating local bus node addresses to a global bus for communication over the second bus type. Alternatively, the local bus node identification process is controlled by the bridging device operating as the root node to cause the local nodes to be identified with a node address that is unique for the global network. The second bus type operates as a backbone for the global network and can be any type of communication bus or network with capability to transport the local bus traffic. The bridging devices that interface the local IEEE1394 buses to the backbone contain portals specific to each bus type that can communicate data between the dissimilar buses.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines, and includes a non-volatile memory, a command packet decoder, and a control unit, such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-

Abstract: Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored jointly to determine whether the hardware resource it represents is in use by a software thread. The bits in the same register bit location of all the semaphore registers are monitored jointly to determine the ID number of the software thread currently using the hardware resource. The limited-width test bus comprises of bit lines representing each semaphore registers and bit lines representing the contents of the semaphore registers. Semaphore protocol steps are used in addition to changes monitored by the limited-width test bus to determine current usage of each hardware resource and to identify the ID number of the software thread using a hardware resource.

Abstract: A semiconductor manufacturing apparatus includes: a calculation unit having at least one computer for processing semiconductor design information; a control unit for controlling radiation of an electron in accordance with a processing result of the semiconductor design information; a writing unit for radiating an electron in accordance with instructions of the control unit; and at least one storage device. The semiconductor manufacturing apparatus permits a communication between the storage device, the calculation unit, the control unit, and the writing unit. The semiconductor manufacturing apparatus further includes a communication pass through which the storage device can be controlled.

Abstract: Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is performed by a method wherein address administration means holds address information in relationship with each group of a series of data written in the buffer means and data is output from the buffer means.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2N primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2N primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.

Abstract: Universal network interfaces for a home network connect disparate components to the network, such as relatively complex components (TVs, computers) and relatively simple components (audio boom boxes).

Abstract: An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs. A method of accessing data in a memory device is also disclosed.

Abstract: A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.

Abstract: An electronic device having a MultiMediaCard host connected to a MultiMediaCard card via a bus system having a plurality of signal lines and a plurality of data lines, wherein the host is operable in a number of data modes. At least in one of the data modes the number of data lines used to convey data between the host and card is smaller than the number of data lines available on the bus system, leaving some unused data lines. An embedded module in the card is used to generate a clock signal, a command signal and further data to be conveyed between the host and the card on some or all of the unused data lines. When the electronic device is operable in an SPI mode, the CS line can be used for sending a command signal from the card to the host.

Abstract: In a data processor including a master circuit that issues an access request and slave circuits that perform processing in response to the access request received from the master circuit, the disclosed invention enables the master circuit to access all data areas of the slave circuits even if the master circuit does not have an access command in data size suitable for accessing the slave circuit. An access size control unit that can convert access size input from the master circuit to data size in which the slave circuit accepts access is installed between the master circuit and the slave circuit. The access size control unit retains at least one address for access size setting. As the master circuit accesses the appropriate address for access size setting, the access size conversion procedure can be carried out.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Abstract: The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.

Abstract: In an arrangement in which a CPU transmits data such as audio data through a 32-bit data bus, a format conversion device and a format conversion program are a are newly prepared. Further, input data having a first bit-width (32 bit width) is converted to output data having a second bit-width (24 bit width) in accordance with a predetermined system so that the efficiency of use of the bus at the time of transmitting data is improved; thus, it becomes possible to reduce a data memory area required for multi-media processes.

Abstract: A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width of 128 bits, via a selector. The first to third buffer circuits are connected to a circuit such as a signal processing circuit by buses having a bit width of 32 bits. Since part of the circuitry is connected by buses having a bit width of 32 bits, the wiring is simple. By executing various processing in parallel, it is possible to prevent prolongation of the time required to record image data on a memory card.

Abstract: An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the host device via the host bus, where the address has a first width. Next, the interface converts the received address from the first width into one or more address components each having a second width. Then, the circuit accesses the target device by driving the one or more address components onto the target bus. Such an interface allows for a simple, direct communication path between the host bus, such as a system bus, and a target bus, such as an LPC bus. The interface consolidates several tasks into one general purpose interface, providing savings in components used, design complexity, and overall cost of implementation. Further, the length of time required for communications between interfaced busses is substantially reduced.

Abstract: A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Abstract: A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more external devices. The interface accomplishes this function by serializing bus transactions in one device, transferring the serial transaction between devices via one interface port, and de-serializing the transaction in the external device. The general features include low pin count (as few as three signals), simple packet based transfer protocol for memory mapped access, symmetric operation, simple block code formatting, supports both host to peripheral and peer to peer transactions, and support multiple outstanding transactions.

Abstract: A switching transistor is placed between a serial port of a RS232 device and a parallel port of a TTL microcontroller. Selective activation of the switching transistor permits a high voltage signal to be transmitted from the power supply rail of the TTL microcontroller to the RXD pin of the RS232 device, where the signal is interpreted as a logical low. This step takes advantage of the fact that the RS232 standard interprets any voltage received at the RXD pin greater than a receiver threshold value to be a logical low. Selective deactivation of the switching transistor isolates the RS232 port from the non-RS232 device, permitting negative voltage signal output by the TXD pin of the idling RS232 port to be conveyed back to the RS232 port at the RXD pin. This negative voltage signal is interpreted by the RS232 port as a logical high signal.

Abstract: The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.

Abstract: A modular switch, comprising a plurality of backplane sub-buses; a plurality of cards which are each allocated one or more of the backplane sub-buses; and a controller which dynamically allocates the backplane sub-buses to the plurality of cards, based on the bandwidth needs of the cards. Preferably, the bandwidth capacity of substantially all the backplane sub-buses is less than the sum of the maximal transmission bandwidth capacities of the cards.

Abstract: A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.

Abstract: The present invention comprises a method and apparatus for selectively providing pre-emphasis to the output of a first driver during an initial portion of certain data transitions while transmitting data along a data bus from a source to a destination, with the certain data transitions being determined as a function of the content of the history of prior transmitted data cells. In the preferred embodiment, a pre-emphasis driver is connected in parallel to a normal driver and the pre-emphasis driver is activated preferably during the initial portion of a data transition to provide pre-emphasis in response to a control signal being applied to the pre-emphasis driver. The preferred embodiment of the present invention also comprises a sequence detector and control for monitoring the data cells or bits that are inputted to the normal driver to provide a history of the voltage levels of the data bits that are input to the normal driver.

Abstract: Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the interconnect state machine that may cause the interconnect state machine to prolong one or more phases of the transaction.

Abstract: An external bus controller which is configured such that, when an external device having a data width smaller than that of an external bus is connected to the external bus, the signal lines of the external bus can be freely selected. This external bus controller includes a first exchange, which converts the data width of input/output data so as to compensate for differences between the data width of the internal bus and the data width of an external device, and a second exchange, which exchanges signal lines between the first exchange and the used signal lines. The signal lines to be used are set for each external device using configuration pins or similar means.

Abstract: A semiconductor manufacturing apparatus includes: a calculation unit having at least one computer for processing semiconductor design information; a control unit for controlling radiation of an electron in accordance with a processing result of the semiconductor design information; a writing unit for radiating an electron in accordance with instructions of the control unit; and at least one storage device. The semiconductor manufacturing apparatus permits a communication between the storage device, the calculation unit, the control unit, and the writing unit. The semiconductor manufacturing apparatus further includes a communication pass through which the storage device can be controlled.

Abstract: The invention relates to a method for adjusting the data transmission rate in a fieldbus system (10) which is suitable to control safety-critical processes and which comprises at least one subscriber (12, 14) connected to a fieldbus (20), wherein in a first phase the subscriber/subscribers log on at a unit (30/central unit) centrally connected to the fieldbus with a first low data transmission rate. In a second phase the central unit (30) sets the data transmission rate at the subscriber/subscribers (12, 14) to a predetermined higher second value. In a third phase the subscriber/subscribers (12, 14) log on again at the central unit with a higher data transmission rate; and the central unit (30) shuts down the fieldbus (20) if it detects a deviation of the number of subscribers (12, 14) logged on in the first and the third phase.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: A semiconductor memory device with adjustable I/O bandwidth includes a plurality of data I/O buffers connected one by one to a plurality of I/O ports, a switch array including a plurality of switches for connecting the plurality of data I/O buffers to a plurality of sense amplifier arrays, and a switch control unit for receiving external control signals to control the data I/O buffer and the plurality of switches.

Abstract: A pipelined Universal Serial Bus (USB) parallel frame delineator and non-return to zero invert (NRZI) decoder is described. Using a three-stage pipeline and parallel data stream processing, a USB transceiver delineates received asynchronous frame boundaries within a USB peripheral NRZI data stream. Using asynchronous parallel data stream processing the USB transceiver concurrently decodes received NRZI encoded data.

Abstract: In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.